On Tue, 08 Oct 2024 02:41:37 PDT (-0700), zhangchun...@iscas.ac.cn wrote:
These patches are all simple fixes with no strong dependency though,
I hope that making them a patchset will be more convenient for merge.
It doesn't: there's two RISC-V fixes and two MM cleanups, which makes
stuff likel
ommit_memory
+ fi
# va high address boundary switch test
ARCH_ARM64="arm64"
Acked-by: Palmer Dabbelt
(I'm taking the first two as they're RISC-V bits)
-by: Palmer Dabbelt
In case that helps, but this has nothing to do with RISC-V so you might
need to re-send it so someone else notices. Though +Andrew, in case
that's enough...
On Mon, 24 Jun 2024 01:21:41 PDT (-0700), alexgh...@rivosinc.com wrote:
We cannot delay the icache flush after patching some functions as we may
have patched a function that will get called before the icache flush.
The only way to completely avoid such scenario is by flushing the icache
as soon
On Tue, 18 Jun 2024 02:55:32 PDT (-0700), a...@ghiti.fr wrote:
Hi Andy,
On 13/06/2024 09:11, Andy Chiu wrote:
arch_stack_walk() is called intensively in function_graph when the
kernel is compiled with CONFIG_TRACE_IRQFLAGS. As a result, the kernel
logs a lot of arch_stack_walk and its sub-funct
The following changes since commit e49d033bddf5b565044e2abe4241353959bc9120:
Linux 5.12-rc6 (2021-04-04 14:15:36 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.12-rc8
for you to fetch changes up to 7ae1163
On Fri, 16 Apr 2021 03:47:19 PDT (-0700), a...@ghiti.fr wrote:
Hi Anup,
Le 4/16/21 à 6:41 AM, Anup Patel a écrit :
On Thu, Apr 15, 2021 at 4:34 PM Alexandre Ghiti wrote:
If CONFIG_STRICT_KERNEL_RWX is not set, we cannot set different permissions
to the kernel data and text sections, so make
On Tue, 30 Mar 2021 02:47:30 PDT (-0700), ge...@linux-m68k.org wrote:
Hi Palmer,
On Tue, Mar 30, 2021 at 7:08 AM Palmer Dabbelt wrote:
On Sat, 13 Mar 2021 00:45:05 PST (-0800), a...@ghiti.fr wrote:
> When KASAN vmalloc region is populated, there is no userspace process and
> the page ta
these in this cycle if possible.
This LGTM, but it's pretty far out of my area of expertise. I'm happy
to take them via my tree, but I'd prefer to get an Ack from someone.
Al, get_maintainer suggests you?
Acked-by: Palmer Dabbelt
On Sun, 11 Apr 2021 09:41:44 PDT (-0700), a...@ghiti.fr wrote:
This is a preparatory patch for relocatable kernel and sv48 support.
The kernel used to be linked at PAGE_OFFSET address therefore we could use
the linear mapping for the kernel mapping. But the relocated kernel base
address will be
On Mon, 12 Apr 2021 06:32:27 PDT (-0700), christoph...@gmail.com wrote:
On Sun, Apr 11, 2021 at 11:11 PM Palmer Dabbelt wrote:
On Wed, 24 Mar 2021 05:53:51 PDT (-0700), a...@brainfault.org wrote:
> On Wed, Mar 24, 2021 at 6:08 PM Peter Zijlstra wrote:
>>
>> On Wed, Mar 24, 202
On Mon, 29 Mar 2021 11:16:24 PDT (-0700), jszha...@mail.ustc.edu.cn wrote:
From: Jisheng Zhang
Current riscv's kprobe handlers are run with both preemption and
interrupt enabled, this violates kprobe requirements. Fix this issue
by keeping interrupts disabled for BREAKPOINT exception.
Fixes: c
On Mon, 29 Mar 2021 11:12:26 PDT (-0700), jszha...@mail.ustc.edu.cn wrote:
From: Jisheng Zhang
These two functions are used to implement the kprobes feature so they
can't be kprobed.
Fixes: c22b0bcb1dd0 ("riscv: Add kprobes supported")
Signed-off-by: Jisheng Zhang
---
arch/riscv/kernel/traps
On Mon, 29 Mar 2021 11:14:40 PDT (-0700), jszha...@mail.ustc.edu.cn wrote:
From: Jisheng Zhang
Currently, the riscv's kprobes(powerred by ftrace) handler is
preemptible. Futher check indicates we miss something similar as the
commit c536aa1c5b17 ("kprobes/ftrace: Add recursion protection to the
On Mon, 29 Mar 2021 11:04:16 PDT (-0700), jszha...@mail.ustc.edu.cn wrote:
From: Jisheng Zhang
Add riscv specific info dump in both handler_pre() and handler_post().
Signed-off-by: Jisheng Zhang
---
samples/kprobes/kprobe_example.c | 8
1 file changed, 8 insertions(+)
diff --git a/
On Sun, 28 Mar 2021 18:55:09 PDT (-0700), l...@jiuyang.me wrote:
This patch implements flush_cache_vmap and flush_cache_vunmap for
RISC-V, since these functions might modify PTE. Without this patch,
SFENCE.VMA won't be added to related codes, which might introduce a bug
in some out-of-order micro
On Thu, 25 Mar 2021 15:38:04 PDT (-0700), nat...@kernel.org wrote:
Hi all,
This series fixes function tracing with clang.
Patch 1 adjusts the mcount regex in scripts/recordmcount.pl to handle
the presence of PLT relocations, which happen with clang. Without this,
the mcount_loc section will not
On Thu, 25 Mar 2021 14:51:56 PDT (-0700), nat...@kernel.org wrote:
Currently, the VDSO is being linked through $(CC). This does not match
how the rest of the kernel links objects, which is through the $(LD)
variable.
When linking with clang, there are a couple of warnings about flags that
will n
ch introduces a ticket lock implementation for riscv, along the
> > same lines as the implementation for arch/arm & arch/csky.
> >
> > Signed-off-by: Guo Ren
> > Cc: Catalin Marinas
> > Cc: Will Deacon
> > Cc: Peter Zijlstra
> > Cc: Palmer Dabbelt
&
On Wed, 31 Mar 2021 02:21:58 PDT (-0700), pbonz...@redhat.com wrote:
On 30/03/21 07:48, Anup Patel wrote:
It seems Andrew does not want to freeze H-extension until we have virtualization
aware interrupt controller (such as RISC-V AIA specification) and IOMMU. Lot
of us feel that these things ca
The following changes since commit a5e13c6df0e41702d2b2c77c8ad41677ebb065b3:
Linux 5.12-rc5 (2021-03-28 15:48:16 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.12-rc6
for you to fetch changes up to 1adbc29
On Tue, 30 Mar 2021 13:31:45 PDT (-0700), ma...@orcam.me.uk wrote:
On Mon, 29 Mar 2021, Palmer Dabbelt wrote:
> --- /dev/null
> +++ b/arch/riscv/include/uapi/asm/setup.h
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
&g
On Tue, 30 Mar 2021 15:40:34 PDT (-0700), Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the risc-v tree got a conflict in:
arch/riscv/mm/kasan_init.c
between commits:
f3773dd031de ("riscv: Ensure page table writes are flushed when initializing KASAN
vmalloc")
78947bdfd752
clock-names = "pcie_aux";
+ clocks = <&prci PRCI_CLK_PCIE_AUX>;
+ pwren-gpios = <&gpio 5 0>;
+ perstn-gpios = <&gpio 8 0>;
+ resets = <&prci 4>;
+ status = "okay";
+ };
};
};
Acked-by: Palmer Dabbelt
I'm happy to take these all through the RISC-V tree if that helps, but
as usual I'd like reviews or acks from the subsystem maintainers. It
looks like there are some issues so I'm going to drop this from my
inbox.
On Mon, 29 Mar 2021 20:36:12 PDT (-0700), greentime...@sifive.com wrote:
Stephen Boyd 於 2021年3月30日 週二 上午3:14寫道：
Quoting Greentime Hu (2021-03-17 23:08:09)
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 71ab75a46491..f094df93d911 100644
> --- a/drivers/reset/Kconfig
> +++
Regards,
Jiuyang
On Tue, 16 Mar 2021 at 09:17 PM Palmer Dabbelt wrote:
We're trying to avoid this sort of thing, instead relying on the generic kernel
functionality to batch up page table modifications before we issue the fences.
If you're seeing some specific issue then I'd b
On Tue, 30 Mar 2021 11:39:10 PDT (-0700), a...@ghiti.fr wrote:
Le 3/30/21 à 2:26 AM, Vitaly Wool a écrit :
On Tue, Mar 30, 2021 at 8:23 AM Palmer Dabbelt wrote:
On Sun, 21 Mar 2021 17:12:15 PDT (-0700), vitaly.w...@konsulko.com wrote:
Introduce XIP (eXecute In Place) support for RISC-V
On Sun, 21 Mar 2021 17:12:15 PDT (-0700), vitaly.w...@konsulko.com wrote:
Introduce XIP (eXecute In Place) support for RISC-V platforms.
It allows code to be executed directly from non-volatile storage
directly addressable by the CPU, such as QSPI NOR flash which can
be found on many RISC-V platf
On Mon, 22 Mar 2021 01:38:36 PDT (-0700), yang@linux.alibaba.com wrote:
Eliminate the following coccicheck warning:
./arch/riscv/mm/kasan_init.c:219:2-3: Unneeded semicolon
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
arch/riscv/mm/kasan_init.c | 2 +-
1 file changed, 1 insertion(+
On Wed, 17 Mar 2021 06:42:23 PDT (-0700), rost...@goodmis.org wrote:
On Tue, 16 Mar 2021 21:21:08 -0700 (PDT)
Palmer Dabbelt wrote:
Thanks, this is on fixes.
What does this mean? Is there a tree that spelling fixes go through now?
I had already pulled this patch into my queue for the next
On Wed, 17 Mar 2021 01:17:25 PDT (-0700), yuzi...@ict.ac.cn wrote:
* In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by ope
On Tue, 16 Mar 2021 12:34:20 PDT (-0700), a...@ghiti.fr wrote:
Increase COMMAND_LINE_SIZE as the current default value is too low
for syzbot kernel command line.
Reported-by: Dmitry Vyukov
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/uapi/asm/setup.h | 8
1 file changed, 8 i
the page table, which harmonizes the code.
In addition, make use of set_pgd that goes through all unused page table
levels, contrary to p*d_populate functions, which makes this function work
whatever the number of page table levels.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Palmer Dabbelt
On Tue, 16 Mar 2021 09:02:43 PDT (-0700), m...@carlosedp.com wrote:
Make 'make tar-pkg' and 'tarbz2-pkg' work on riscv.
Signed-off-by: Carlos de Paula
---
scripts/package/buildtar | 8
1 file changed, 8 insertions(+)
diff --git a/scripts/package/buildtar b/scripts/package/buildtar
in
On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote:
This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
It is rebased on v5.12-rc1 and depends on clock support.
Only MMC and ethernet drivers are enabled via this series.
The idea here is to add the foundational patch
x no prototype warnings
riscv: time: Fix no prototype for time_init
riscv: syscall_table: Reduce W=1 compilation warnings noise
riscv: process: Fix no prototype for show_regs
riscv: ftrace: Use ftrace_get_regs helper
riscv: process: Fix no prototype for arch_dup_task_st
On Tue, 16 Mar 2021 02:30:54 PDT (-0700), musamaan...@gmail.com wrote:
There is a spelling mistake in a comment. Fix it.
Signed-off-by: Muhammad Usama Anjum
---
arch/riscv/kernel/smp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kern
On Mon, 15 Mar 2021 04:04:59 PDT (-0700), Anup Patel wrote:
The sbi_init() already prints SBI version before detecting
various SBI extensions so we don't need to print SBI version
for all detected SBI extensions.
Signed-off-by: Anup Patel
---
arch/riscv/kernel/sbi.c | 6 +++---
1 file changed,
From: Palmer Dabbelt
Without this I get a missing prototype warning.
Reported-by: kernel test robot
Fixes: e178d670f251 ("riscv/kasan: add KASAN_VMALLOC support")
Cc: sta...@vger.kernel.org
Signed-off-by: Palmer Dabbelt
---
arch/riscv/mm/kasan_init.c | 2 +-
1 file changed, 1 inser
On Sat, 13 Mar 2021 01:26:47 PST (-0800), a...@ghiti.fr wrote:
Hi Palmer,
Le 3/9/21 à 9:54 PM, Palmer Dabbelt a écrit :
On Thu, 25 Feb 2021 00:04:50 PST (-0800), a...@ghiti.fr wrote:
I decided to split sv48 support in small series to ease the review.
This patchset pushes the kernel mapping
On Sat, 13 Mar 2021 00:45:04 PST (-0800), a...@ghiti.fr wrote:
Make sure that writes to kernel page table during KASAN vmalloc
initialization are made visible by adding a sfence.vma.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Palmer Dabbelt
---
arch/riscv/mm/kasan_init.c | 2 ++
1 file
On Fri, 12 Mar 2021 07:46:34 PST (-0800), ge...@linux-m68k.org wrote:
init_resources() allocates an array of resources, based on the current
total number of memory regions and reserved memory regions. However,
allocating this array using memblock_alloc() might increase the number
of reserved mem
On Thu, 11 Mar 2021 08:47:09 PST (-0800), Anup Patel wrote:
This series primarily does two things:
1. Allows RISC-V IPI provider to specificy whether IPI operations are
suitable for remote TLB flush (PATCH1)
2. Improve remote TLB flush to use IPIs whenever possible (PATCH2)
3. Allow irqchip dr
On Thu, 11 Mar 2021 01:40:22 PST (-0800), colin.k...@canonical.com wrote:
From: Colin Ian King
There is a spelling mistake in a comment, fix it.
Signed-off-by: Colin Ian King
---
arch/csky/kernel/probes/ftrace.c | 2 +-
arch/riscv/kernel/probes/ftrace.c | 2 +-
arch/x86/kernel/kprobes/ftrac
On Tue, 09 Mar 2021 22:22:46 PST (-0800), l...@jiuyang.me wrote:
From: Jiuyang Liu
This patch inserts SFENCE.VMA after modifying PTE based on RISC-V
specification.
arch/riscv/include/asm/pgtable.h:
1. implement pte_user, pte_global and pte_leaf to check correspond
attribute of a pte_t.
2. ins
On Wed, 10 Mar 2021 01:22:35 PST (-0800), vitaly.w...@konsulko.com wrote:
Introduce XIP (eXecute In Place) support for RISC-V platforms.
It allows code to be executed directly from non-volatile storage
directly addressable by the CPU, such as QSPI NOR flash which can
be found on many RISC-V platf
other architectures(powerpc, mips,
arm, hexagon, openrisc, sh) have supported the infrastructure to
deal with Power Management issues.
Signed-off-by: Guo Ren
Cc: Arnd Bergmann
Cc: Thomas Gleixner
Cc: Daniel Lezcano
Cc: Anup Patel
Cc: Atish Patra
Cc: Palmer Dabbelt
Cc: Greentime Hu
---
arch
Cc: Christoph Hellwig
Cc: Palmer Dabbelt
Tested-by: Guo Ren
Signed-off-by: Guo Ren
Link:
https://lore.kernel.org/lkml/CAHk-=wjM+kCsKqNdb=c0hKsv=J7-3Q1zmM15vp6_=8s5xfg...@mail.gmail.com/
---
drivers/clocksource/timer-riscv.c | 4 ++--
include/linux/cpuhotplug.h| 1 -
2 files changed, 2
: Linus Torvalds
Cc: Palmer Dabbelt
Cc: Anup Patel
Cc: Atish Patra
Cc: Christoph Hellwig
Tested-by: Guo Ren
Signed-off-by: Guo Ren
Link:
https://lore.kernel.org/lkml/CAHk-=wjM+kCsKqNdb=c0hKsv=J7-3Q1zmM15vp6_=8s5xfg...@mail.gmail.com/
---
drivers/irqchip/irq-riscv-intc.c | 2 +-
drivers
On Sun, 28 Feb 2021 03:10:22 PST (-0800), julia.law...@inria.fr wrote:
From: kernel test robot
Use BUG_ON instead of a if condition followed by BUG.
Generated by: scripts/coccinelle/misc/bugon.cocci
Fixes: c22b0bcb1dd0 ("riscv: Add kprobes supported")
CC: Guo Ren
Reported-by: kernel test rob
On Fri, 05 Mar 2021 03:33:23 PST (-0800), sunnany...@huawei.com wrote:
Fix some compilation warnings,improve code style
Nanyong Sun (9):
riscv: traps: Fix no prototype warnings
riscv: irq: Fix no prototype warning
riscv: sbi: Fix comment of __sbi_set_timer_v01
riscv: ptrace: Fix no proto
On Fri, 05 Mar 2021 03:33:24 PST (-0800), sunnany...@huawei.com wrote:
Fix all W=1 compilation warnings:'no previous prototype for' in
arch/riscv/kernel/traps.c:
arch/riscv/kernel/traps.c:96:15: warning: no previous prototype for
‘do_trap_unknown’ [-Wmissing-prototypes]
96 | DO_ERROR_INFO(do
instead.
This reduces code duplication and makes it cleaner.
Cc: Russell King
Cc: Catalin Marinas
Cc: Will Deacon
Cc: Thomas Bogendoerfer
Cc: "James E.J. Bottomley"
Cc: Helge Deller
Cc: Michael Ellerman
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Paul Walmsley
Cc: Palmer D
On Tue, 09 Mar 2021 11:28:39 PST (-0800), ati...@atishpatra.org wrote:
On Mon, Mar 8, 2021 at 2:55 AM Anup Patel wrote:
On Mon, Mar 8, 2021 at 1:19 PM Atish Patra wrote:
>
> On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
> >
> > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
wrote:
On Fri, 05 Mar 2021 23:52:29 PST (-0800), yangtie...@loongson.cn wrote:
copy_{to,from}_user() returns the amount left to copy, it should return
-EFAULT error code if copy {to,from} user failed, just like the return
value is an error code when {put,get}_user() failed, this is to make the
return va
On Mon, 01 Mar 2021 22:36:48 PST (-0800), jiapeng.ch...@linux.alibaba.com wrote:
Fix the following coccicheck warnings:
./arch/riscv/mm/kasan_init.c:217:2-3: Unneeded semicolon.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
arch/riscv/mm/kasan_init.c | 2 +-
1 file changed, 1 ins
On Mon, 01 Mar 2021 03:58:33 PST (-0800), Anup Patel wrote:
The SBI SRST extension provides a standard way to poweroff and
reboot the system irrespective to whether Linux RISC-V S-mode
is running natively (HS-mode) or inside Guest/VM (VS-mode).
The SBI SRST extension is available in latest SBI v
On Thu, 25 Feb 2021 00:04:50 PST (-0800), a...@ghiti.fr wrote:
I decided to split sv48 support in small series to ease the review.
This patchset pushes the kernel mapping (modules and BPF too) to the last
4GB of the 64bit address space, this allows to:
- implement relocatable kernel (that will c
up, or if you want me to do it. Either way,
Reviewed-by: Palmer Dabbelt
Thanks!
Signed-off-by: Alexandre Ghiti
---
Changes in v2:
- Quiet kernel test robot warnings about missing prototypes by declaring
the introduced functions as static.
arch/riscv/mm/kasan_init.c | 61 +---
4
x86/include/asm/pgtable.h:#ifdef CONFIG_NUMA_BALANCING
x86/include/asm/pgtable.h:#endif /* CONFIG_NUMA_BALANCING */
On the other hand, setup_numabalancing() is implemented in mm/mempolicy.c
which doesn't depend on architectures.
Cc: Mel Gorman
Cc: Paul Walmsley
Cc: Palmer Dabbelt
Cc: Alb
ndconfig build
failures.
Anup Patel (1):
RISC-V: Enable CPU Hotplug in defconfigs
Kefeng Wang (1):
riscv: Cleanup setup_bootmem()
Palmer Dabbelt (1):
RISC-V: Make NUMA depend on SMP
arch/riscv/Kconfig| 1 +
arc
On Mon, 08 Feb 2021 21:46:20 PST (-0800), Anup Patel wrote:
The CPU hotplug support has been tested on QEMU, Spike, and SiFive
Unleashed so let's enable it by default in RV32 and RV64 defconfigs.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_def
On Fri, 26 Feb 2021 19:41:40 PST (-0800), hu...@google.com wrote:
On Fri, 26 Feb 2021, Palmer Dabbelt wrote:
On Fri, 26 Feb 2021 17:31:40 PST (-0800), hu...@google.com wrote:
> On Fri, 26 Feb 2021, Andrew Morton wrote:
> > On Fri, 26 Feb 2021 12:17:20 -0800 Palmer Dabbelt
> > wr
On Fri, 26 Feb 2021 17:03:53 PST (-0800), wangkefeng.w...@huawei.com wrote:
On 2021/2/27 4:25, Palmer Dabbelt wrote:
From: Palmer Dabbelt
In theory these are orthogonal, but in practice all NUMA systems are
SMP. NUMA && !SMP doesn't build, everyone else is coupling them, and I
On Fri, 26 Feb 2021 17:31:40 PST (-0800), hu...@google.com wrote:
On Fri, 26 Feb 2021, Andrew Morton wrote:
On Fri, 26 Feb 2021 12:17:20 -0800 Palmer Dabbelt wrote:
> From: Palmer Dabbelt
>
> This is only useful under CONFIG_NUMA. IIUC skipping the check is the
> right thing to
From: Palmer Dabbelt
In theory these are orthogonal, but in practice all NUMA systems are
SMP. NUMA && !SMP doesn't build, everyone else is coupling them, and I
don't really see any value in supporting that configuration.
Fixes: 4f0e8eef772e ("riscv: Add numa suppo
From: Palmer Dabbelt
This is only defined (and useful) for CONFIG_NUMA, but isn't
conditionally declared. This makes users a bit more of a headache to
track down.
Signed-off-by: Palmer Dabbelt
---
include/linux/topology.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/
From: Palmer Dabbelt
This is only useful under CONFIG_NUMA. IIUC skipping the check is the
right thing to do here, as without CONFIG_NUMA there will never be any
large node distances on non-NUMA systems.
I expected this to manifest as a link failure under (!CONFIG_NUMA
g and stack dump output
riscv: Add dump stack in show_regs
riscv: Improve __show_regs
initrd: Add the preprocessor guard in initrd.h
initramfs: Provide a common initrd reserve function
riscv: Covert to reserve_initrd_mem()
riscv: Remove unnecessary declaration
Nylon Che
d")
Fixes: dcdc7a53a890 ("RISC-V: Implement ptrace regs and stack API")
For the RISC-V stuff
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Thanks!
Signed-off-by: Arnd Bergmann
---
Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +-
Documentation/f
On Wed, 24 Feb 2021 23:48:13 PST (-0800), a...@ghiti.fr wrote:
Le 2/25/21 à 2:42 AM, Alexandre Ghiti a écrit :
Populate the top-level of the kernel page table to implement KASAN_VMALLOC,
lower levels are filled dynamically upon memory allocation at runtime.
Co-developed-by: Nylon Chen
Signed-o
On Mon, 22 Feb 2021 18:31:43 PST (-0800), Damien Le Moal wrote:
On 2021/02/23 11:19, Palmer Dabbelt wrote:
From: Palmer Dabbelt
The rest of these are alphabetically sorted, and leaving it this way
causes a merge conflict.
Signed-off-by: Palmer Dabbelt
---
I missed this when reviewing these
On Sun, 21 Feb 2021 05:42:08 PST (-0800), a...@ghiti.fr wrote:
Hi,
Le 2/8/21 à 2:30 PM, Alexandre Ghiti a écrit :
This small series contains some improvements for the riscv KASAN code:
- it brings a better readability of the code (patch 1/2)
- it fixes oversight regarding page table population
On Mon, 22 Feb 2021 00:07:34 PST (-0800), a...@ghiti.fr wrote:
kasan_mem_to_shadow translates virtual addresses to kasan shadow
addresses whereas for_each_mem_range returns physical addresses: it is
then required to use __va on those addresses before passing them to
kasan_mem_to_shadow.
Fixes: b
From: Palmer Dabbelt
The rest of these are alphabetically sorted, and leaving it this way
causes a merge conflict.
Signed-off-by: Palmer Dabbelt
---
I missed this when reviewing these patches, but happened across it when
test merging from Linus' tree. It goes back a way so I'm h
:150:1: error: no return statement in function
returning non-void
Sorry for the oversight. The return statement is missing.
@Palmer Dabbelt : Can you fix it in for-next or should I send a v2 ?
I just fixed it up.
On Fri, 19 Feb 2021 10:53:43 PST (-0800), dvyu...@google.com wrote:
On Fri, Feb 19, 2021 at 6:01 PM Alex Ghiti wrote:
Hi Dmitry,
Le 2/18/21 à 6:36 AM, Dmitry Vyukov a écrit :
> On Thu, Feb 18, 2021 at 8:54 AM Alex Ghiti wrote:
>>
>> Hi Dmitry,
>>
>>> On Wed, Feb 17, 2021 at 5:36 PM Alex Ghit
On Mon, 08 Feb 2021 21:46:20 PST (-0800), Anup Patel wrote:
The CPU hotplug support has been tested on QEMU, Spike, and SiFive
Unleashed so let's enable it by default in RV32 and RV64 defconfigs.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_def
On Wed, 10 Feb 2021 04:47:34 PST (-0800), sch...@linux-m68k.org wrote:
On Feb 04 2021, Palmer Dabbelt wrote:
From: Palmer Dabbelt
VSC8541 phys need a special reset sequence, which the driver doesn't
currentlny support. As a result enabling the reset via GPIO essentially
guarnteees tha
equired for this phy.
--------
Palmer Dabbelt (1):
Revert "dts: phy: add GPIO number and active state used for phy reset"
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 1 -
1 file changed, 1 deletion(-)
On Mon, 08 Feb 2021 15:37:24 PST (-0800), sk...@linuxfoundation.org wrote:
On 2/5/21 12:57 AM, Tobias Klauser wrote:
On 2021-02-05 at 08:06:37 +0100, Palmer Dabbelt wrote:
On Thu, 04 Feb 2021 06:50:42 PST (-0800), tklau...@distanz.ch wrote:
[...]
Reviewed-by: Palmer Dabbelt
Acked-by
The following changes since commit 1048ba83fb1c00cd24172e23e8263972f6b5d9ac:
Linux 5.11-rc6 (2021-01-31 13:50:09 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.11-rc7
for you to fetch changes up to de5f4b8
On Wed, 03 Feb 2021 21:26:43 PST (-0800), Atish Patra wrote:
SBI v0.2 functions can return an error code from SBI implementation.
We are already processing the SBI error code and coverts it to the Linux
error code.
Propagate to the error code to the caller as well. As of now, kvm is the
only use
defined(__riscv__) || defined(__riscv)
#define VDSO_VERSION 5
#define VDSO_NAMES 1
+#if __riscv_xlen == 32
#define VDSO_32BIT 1
+#endif
#else /* nds32 */
#define VDSO_VERSION 4
#define VDSO_NAMES 1
Reviewed-by: Palmer Dabbelt
Acked-by
On Wed, 03 Feb 2021 06:23:43 PST (-0800), wangkefeng.w...@huawei.com wrote:
The numa feature is useless for riscv32 platform(MAXPHYSMEM_1GB if 32bit),
I'm not convinced of that. There's no reason NUMA shouldn't work on 32-bit, it
doesn't depend on having a large amount of memory just having no
SATP CSR are not implemented on Spike and SiFive
Unleashed board so we don't see any change in performance. On real HW
having all ASID bits implemented, the performance gains will be much
more due improved sharing of TLB among different processes.
Signed-off-by: Anup Patel
Reviewed-by: Palm
From: Palmer Dabbelt
VSC8541 phys need a special reset sequence, which the driver doesn't
currentlny support. As a result enabling the reset via GPIO essentially
guarnteees that the device won't work correctly.
This reverts commit a0fa9d727043da2238432471e85de0bdb8a8df65.
Fixes: a0
On Thu, 04 Feb 2021 02:16:54 PST (-0800), sch...@linux-m68k.org wrote:
On Jan 13 2021, Palmer Dabbelt wrote:
On Tue, 10 Nov 2020 07:22:09 PST (-0800), sagar.ka...@sifive.com wrote:
HiFive Unleashed is having VSC8541-01 ethernet phy device and requires a
specific reset sequence of 0-1-0-1 in
On Sat, 30 Jan 2021 01:33:20 PST (-0800), a...@ghiti.fr wrote:
Hi Palmer,
On 1/4/21 2:58 PM, Alexandre Ghiti wrote:
This patchset, contrary to the previous versions, allows to have a single
kernel for sv39 and sv48 without being relocatable.
The idea comes from Arnd Bergmann who suggested to d
On Mon, 01 Feb 2021 21:51:59 PST (-0800), yang@linux.alibaba.com wrote:
Eliminate the following coccicheck warning:
./arch/riscv/mm/kasan_init.c:103:2-3: Unneeded semicolon
Reported-by: Abaci Robot
Signed-off-by: Yang Li
---
arch/riscv/mm/kasan_init.c | 2 +-
1 file changed, 1 insertion(+
On Fri, 29 Jan 2021 11:00:36 PST (-0800), Atish Patra wrote:
.init section permission should only updated to non-execute if
STRICT_KERNEL_RWX is enabled. Otherwise, this will lead to a kernel hang.
Fixes: 19a00869028f ("RISC-V: Protect all kernel sections including init early")
Suggested-by: Ge
On Fri, 29 Jan 2021 11:00:38 PST (-0800), Atish Patra wrote:
MAXPHYSMEM_1GB option was added for RV32 because RV32 only supports 1GB
of maximum physical memory. This lead to few compilation errors reported
by kernel test robot which created the following configuration combination
which are not us
On Tue, 02 Feb 2021 18:27:42 PST (-0800), Palmer Dabbelt wrote:
On Fri, 29 Jan 2021 05:52:51 PST (-0800), ge...@linux-m68k.org wrote:
Hi Atish,
On Thu, Jan 28, 2021 at 9:09 PM Atish Patra wrote:
On Wed, Jan 27, 2021 at 7:18 PM Randy Dunlap wrote:
> I took a riscv-32 .config from kernel t
On Fri, 29 Jan 2021 11:00:37 PST (-0800), Atish Patra wrote:
From: Sebastien Van Cauwenberghe
Allows the sections to be aligned on smaller boundaries and
therefore results in a smaller kernel image size.
Signed-off-by: Sebastien Van Cauwenberghe
Reviewed-by: Atish Patra
---
arch/riscv/inclu
On Fri, 29 Jan 2021 09:31:05 PST (-0800), a...@ghiti.fr wrote:
virt_addr_valid macro checks that a virtual address is valid, ie that
the address belongs to the linear mapping and that the corresponding
physical page exists.
Add the missing check that ensures the virtual address belongs to the
l
ODE);
- local_flush_tlb_all();
-#endif
+ set_mm(next, cpu);
flush_icache_deferred(next);
}
So I know we'd said before that we weren't going to take this until there's
hardware, but I think the QEMU support is good enough -- I don't really care if
the ISA says this might change, it's been in there for long enough.
Aside from the assertions
Reviewed-by: Palmer Dabbelt
LMK if you're going to send a v5 or you want me to just fix it up.
Thanks!
On Fri, 29 Jan 2021 05:52:51 PST (-0800), ge...@linux-m68k.org wrote:
Hi Atish,
On Thu, Jan 28, 2021 at 9:09 PM Atish Patra wrote:
On Wed, Jan 27, 2021 at 7:18 PM Randy Dunlap wrote:
> I took a riscv-32 .config from kernel test robot (it was for a clang build)
> and did a "make olddefconfig"
On Mon, 01 Feb 2021 19:51:07 PST (-0800), rdun...@infradead.org wrote:
On 2/1/21 7:36 PM, Palmer Dabbelt wrote:
On Wed, 27 Jan 2021 19:55:33 PST (-0800), rdun...@infradead.org wrote:
Fix build warnings in the arch_numa common code:
../include/linux/kern_levels.h:5:18: warning: format
("Faking a node at [mem %#018Lx-%#018Lx]\n", start, end - 1);
Fixes: ae3c107cd8be ("numa: Move numa implementation to common code")
Signed-off-by: Randy Dunlap
Reported-by: kernel test robot
Cc: Atish Patra
Cc: Palmer Dabbelt
---
drivers/base/arch_numa.c | 13 +++-
The following changes since commit 19c329f6808995b142b3966301f217c831e7cf31:
Linux 5.11-rc4 (2021-01-17 16:37:05 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
tags/riscv-for-linus-5.11-rc6
for you to fetch changes up to 336e8eb
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