On Wed, Aug 30, 2017 at 1:32 AM, Bjorn Helgaas wrote:
> On Tue, Aug 29, 2017 at 11:02:23AM +0530, Oza Oza wrote:
>> On Tue, Aug 29, 2017 at 3:17 AM, Bjorn Helgaas wrote:
>> > On Thu, Aug 24, 2017 at 10:34:25AM +0530, Oza Pawandeep wrote:
>> >> PCIe spec r3.1, s
On Tue, Aug 29, 2017 at 3:17 AM, Bjorn Helgaas wrote:
> On Thu, Aug 24, 2017 at 10:34:25AM +0530, Oza Pawandeep wrote:
>> PCIe spec r3.1, sec 2.3.2
>> If CRS software visibility is not enabled, the RC must reissue the
>> config request as a new request.
>>
>> - If CRS software visibility is enable
On Tue, Aug 29, 2017 at 3:23 AM, Bjorn Helgaas wrote:
> On Thu, Aug 24, 2017 at 10:34:23AM +0530, Oza Pawandeep wrote:
>> PCI: iproc: Retry request when CRS returned from EP Above patch adds
>> support for CRS in PCI RC driver, otherwise if not handled at lower
>> level, the user space PMD (poll m
On Tue, Aug 29, 2017 at 1:24 AM, Bjorn Helgaas wrote:
> On Tue, Aug 29, 2017 at 01:09:53AM +0530, Oza Oza wrote:
>> On Tue, Aug 29, 2017 at 12:47 AM, Bjorn Helgaas wrote:
>> > On Thu, Aug 24, 2017 at 10:34:25AM +0530, Oza Pawandeep wrote:
>> >> PCIe spec r3.1, s
On Tue, Aug 29, 2017 at 12:47 AM, Bjorn Helgaas wrote:
> On Thu, Aug 24, 2017 at 10:34:25AM +0530, Oza Pawandeep wrote:
>> PCIe spec r3.1, sec 2.3.2
>> If CRS software visibility is not enabled, the RC must reissue the
>> config request as a new request.
>>
>> - If CRS software visibility is enabl
On Wed, Aug 23, 2017 at 11:30 PM, Bjorn Helgaas wrote:
> On Wed, Aug 23, 2017 at 09:32:06PM +0530, Oza Oza wrote:
>> On Wed, Aug 23, 2017 at 9:22 PM, Sinan Kaya wrote:
>> > Hi Oza,
>> >
>> >> In working Enumuration case I get following:
>> >> [
On Wed, Aug 23, 2017 at 9:22 PM, Sinan Kaya wrote:
> Hi Oza,
>
>> In working Enumuration case I get following:
>> [9.125976] pci :00:00.0: bridge configuration invalid ([bus
>> 00-00]), re-configuring
>> [9.134267] where=0x0 val=0x0001
>> [9.146946] where=0x0 val=0x0001
>>
On Wed, Aug 23, 2017 at 7:21 PM, Bjorn Helgaas wrote:
> On Wed, Aug 23, 2017 at 03:57:02PM +0530, Oza Oza wrote:
>> On Wed, Aug 23, 2017 at 2:03 AM, Bjorn Helgaas wrote:
>> > [+cc Sinan, Timur, Alex]
>> >
>> > Hi Oza,
>> >
>> > On Mon,
On Wed, Aug 23, 2017 at 2:03 AM, Bjorn Helgaas wrote:
> [+cc Sinan, Timur, Alex]
>
> Hi Oza,
>
> On Mon, Aug 21, 2017 at 09:28:43PM +0530, Oza Pawandeep wrote:
>> PCIe spec r3.1, sec 2.3.2
>> If CRS software visibility is not enabled, the RC must reissue the
>> config request as a new request.
>>
On Mon, Aug 21, 2017 at 2:55 AM, Bjorn Helgaas wrote:
> On Sun, Aug 20, 2017 at 09:06:51AM +0530, Oza Oza wrote:
>> On Sun, Aug 20, 2017 at 2:34 AM, Bjorn Helgaas wrote:
>> > On Fri, Aug 04, 2017 at 09:18:16PM +0530, Oza Pawandeep wrote:
>> >> PERST must be ass
On Sun, Aug 20, 2017 at 1:56 AM, Bjorn Helgaas wrote:
> On Sun, Aug 20, 2017 at 01:02:09AM +0530, Oza Oza wrote:
>> On Sat, Aug 19, 2017 at 11:56 PM, Bjorn Helgaas wrote:
>
>> > I think you should do something like this instead so you don't do the
>> > MMIO
On Sun, Aug 20, 2017 at 2:34 AM, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 09:18:16PM +0530, Oza Pawandeep wrote:
>> PERST must be asserted around ~500ms before the reboot is applied.
>>
>> During soft reset (e.g., "reboot" from Linux) on some iproc based SOCs
>> LCPLL clock and PERST both go
On Sat, Aug 19, 2017 at 11:56 PM, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 09:18:15PM +0530, Oza Pawandeep wrote:
>> PCIe spec r3.1, sec 2.3.2
>> If CRS software visibility is not enabled, the RC must reissue the
>> config request as a new request.
>>
>> - If CRS software visibility is enabl
On Sat, Aug 19, 2017 at 11:56 PM, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 09:18:15PM +0530, Oza Pawandeep wrote:
>> PCIe spec r3.1, sec 2.3.2
>> If CRS software visibility is not enabled, the RC must reissue the
>> config request as a new request.
>>
>> - If CRS software visibility is enabl
On Sat, Aug 19, 2017 at 10:40 PM, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 09:18:14PM +0530, Oza Pawandeep wrote:
>> PCI: iproc: Retry request when CRS returned from EP
>> Above patch adds support for CRS in PCI RC driver, otherwise if not
>> handled at lower level, the user space PMD (poll
On Wed, Aug 9, 2017 at 11:13 AM, Oza Oza wrote:
> On Wed, Aug 9, 2017 at 10:57 AM, Ray Jui wrote:
>>
>>
>> On 8/8/2017 10:22 PM, Oza Oza wrote:
>>>
>>> On Tue, Aug 8, 2017 at 7:50 PM, Rob Herring wrote:
>>>>
>>>> Please send bindin
On Wed, Aug 9, 2017 at 10:57 AM, Ray Jui wrote:
>
>
> On 8/8/2017 10:22 PM, Oza Oza wrote:
>>
>> On Tue, Aug 8, 2017 at 7:50 PM, Rob Herring wrote:
>>>
>>> Please send bindings to DT list.
>>
>> Sure, will do that.
>>
>>> On Mon
On Tue, Aug 8, 2017 at 7:50 PM, Rob Herring wrote:
> Please send bindings to DT list.
Sure, will do that.
>
> On Mon, Aug 7, 2017 at 11:44 PM, Oza Pawandeep wrote:
>> Add description for optional device tree property
>> 'brcm,pci-hotplug' for PCI hotplug feature.
>>
>> Signed-off-by: Oza Pawand
On Fri, Aug 4, 2017 at 7:07 PM, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 11:29:29AM +0530, Oza Oza wrote:
>> On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas wrote:
>> > On Thu, Aug 03, 2017 at 01:50:29PM +0530, Oza Oza wrote:
>> >> On Thu, Aug 3, 2017 at
On Fri, Aug 4, 2017 at 6:57 PM, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 11:40:46AM +0530, Oza Oza wrote:
>> On Fri, Aug 4, 2017 at 11:29 AM, Oza Oza wrote:
>> > On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas wrote:
>> >> On Thu, Aug 03, 2017 at 01:50:29PM +
On Fri, Aug 4, 2017 at 7:07 PM, Bjorn Helgaas wrote:
> On Fri, Aug 04, 2017 at 11:29:29AM +0530, Oza Oza wrote:
>> On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas wrote:
>> > On Thu, Aug 03, 2017 at 01:50:29PM +0530, Oza Oza wrote:
>> >> On Thu, Aug 3, 2017 at
On Fri, Aug 4, 2017 at 11:29 AM, Oza Oza wrote:
> On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas wrote:
>> On Thu, Aug 03, 2017 at 01:50:29PM +0530, Oza Oza wrote:
>>> On Thu, Aug 3, 2017 at 2:34 AM, Bjorn Helgaas wrote:
>>> > On Thu, Jul 06, 2017 at 08:39:4
On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas wrote:
> On Thu, Aug 03, 2017 at 01:50:29PM +0530, Oza Oza wrote:
>> On Thu, Aug 3, 2017 at 2:34 AM, Bjorn Helgaas wrote:
>> > On Thu, Jul 06, 2017 at 08:39:41AM +0530, Oza Pawandeep wrote:
>> >> For Configuration Req
On Thu, Aug 3, 2017 at 2:34 AM, Bjorn Helgaas wrote:
> On Thu, Jul 06, 2017 at 08:39:41AM +0530, Oza Pawandeep wrote:
>> For Configuration Requests only, following reset it is possible for a
>> device to terminate the request but indicate that it is temporarily unable
>> to process the Request, bu
Hi Robin,
My apology for noise.
I have taken care of your comments.
but these whole patch-set, (specially PCI patch-set) inbound memory
addition depends on Lorenzo's patch-set
.
So I will be posting version 8 patches for IOVA reservation soon after
Lorenzo's patches are made in.
Regards,
Oza.
O
On Wed, Jul 5, 2017 at 9:21 AM, Ray Jui wrote:
> Hi Oza,
>
> It looks like you missed my comments during the internal review. See my
> comments inline below.
>
>
>
> On 7/4/2017 8:08 PM, Oza Pawandeep wrote:
>>
>> PERST must be asserted around ~500ms before the reboot is applied.
>>
>> During soft
On Thu, Jun 15, 2017 at 7:11 PM, Bjorn Helgaas wrote:
> On Wed, Jun 14, 2017 at 10:24:11AM +0530, Oza Oza wrote:
>> On Tue, Jun 13, 2017 at 5:13 AM, Bjorn Helgaas wrote:
>> > On Sun, Jun 11, 2017 at 09:35:38AM +0530, Oza Pawandeep wrote:
>> >> PERST# must be
On Tue, Jun 20, 2017 at 4:09 AM, Bjorn Helgaas wrote:
> On Tue, Jun 13, 2017 at 09:58:22AM +0530, Oza Oza wrote:
>> On Tue, Jun 13, 2017 at 5:00 AM, Bjorn Helgaas wrote:
>> > Please wrap your changelogs to use 75 columns. "git log" indents the
>> > changel
On Tue, Jun 13, 2017 at 5:13 AM, Bjorn Helgaas wrote:
> On Sun, Jun 11, 2017 at 09:35:38AM +0530, Oza Pawandeep wrote:
>> PERST# must be asserted around ~500ms before
>> the reboot is applied.
>>
>> During soft reset (e.g., "reboot" from Linux) on some iProc based SoCs
>> LCPLL clock and PERST bot
On Tue, Jun 13, 2017 at 9:58 AM, Oza Oza wrote:
> On Tue, Jun 13, 2017 at 5:00 AM, Bjorn Helgaas wrote:
>> Please wrap your changelogs to use 75 columns. "git log" indents the
>> changelog by four spaces, so if your text is 75 wide, it will still
>> fit without
On Tue, Jun 13, 2017 at 5:00 AM, Bjorn Helgaas wrote:
> Please wrap your changelogs to use 75 columns. "git log" indents the
> changelog by four spaces, so if your text is 75 wide, it will still
> fit without wrapping.
>
> On Sun, Jun 11, 2017 at 09:35:37AM +0530, Oza Pawandeep wrote:
>> For Conf
On Thu, Jun 1, 2017 at 11:41 PM, Ray Jui wrote:
> Hi Oza,
>
> On 5/31/17 10:27 PM, Oza Pawandeep wrote:
>> PERST# must be asserted around ~500ms before
>> the reboot is applied.
>>
>> During soft reset (e.g., "reboot" from Linux) on some iProc based SoCs
>> LCPLL clock and PERST both goes off simu
On Thu, Jun 1, 2017 at 10:38 PM, Bjorn Helgaas wrote:
> On Wed, May 31, 2017 at 11:17 AM, Oza Oza wrote:
>> On Wed, May 31, 2017 at 4:12 AM, Bjorn Helgaas wrote:
>>> On Mon, May 22, 2017 at 11:39 AM, Oza Pawandeep
>>> wrote:
>>>> This patch adds support
On Wed, May 31, 2017 at 4:12 AM, Bjorn Helgaas wrote:
> On Mon, May 22, 2017 at 11:39 AM, Oza Pawandeep wrote:
>> This patch adds support for inbound memory window
>> for PCI RC drivers.
>>
>> It defines new function pci_create_root_bus2 which
>> takes inbound resources as an argument and fills i
On Tue, May 23, 2017 at 12:48 AM, Alex Williamson
wrote:
> On Mon, 22 May 2017 22:09:39 +0530
> Oza Pawandeep wrote:
>
>> iproc based PCI RC and Stingray SOC has limitaiton of addressing only 512GB
>> memory at once.
>>
>> IOVA allocation honors device's coherent_dma_mask/dma_mask.
>> In PCI case
On Fri, May 5, 2017 at 9:21 PM, Robin Murphy wrote:
> On 04/05/17 19:52, Oza Oza wrote:
>> On Thu, May 4, 2017 at 11:50 PM, Robin Murphy wrote:
>>> On 03/05/17 05:46, Oza Pawandeep wrote:
>>>> this patch reserves the iova for PCI masters.
>>>> ARM64
On Thu, May 18, 2017 at 12:43 AM, Arnd Bergmann wrote:
> On Tue, May 16, 2017 at 7:22 AM, Oza Pawandeep wrote:
>> current device framework and OF framework integration assumes
>> dma-ranges in a way where memory-mapped devices define their
>> dma-ranges. (child-bus-address, parent-bus-address, le
On Thu, May 18, 2017 at 12:43 AM, Arnd Bergmann wrote:
> On Tue, May 16, 2017 at 7:22 AM, Oza Pawandeep wrote:
>> current device framework and OF framework integration assumes
>> dma-ranges in a way where memory-mapped devices define their
>> dma-ranges. (child-bus-address, parent-bus-address, le
On Wed, May 17, 2017 at 10:40 PM, Bjorn Helgaas wrote:
> On Tue, May 16, 2017 at 10:52:05AM +0530, Oza Pawandeep wrote:
>> current device framework and OF framework integration assumes
>
> s/current/The current/
>
>> dma-ranges in a way where memory-mapped devices define their
>> dma-ranges. (chil
On Wed, May 17, 2017 at 10:41 PM, Bjorn Helgaas wrote:
> On Tue, May 16, 2017 at 10:52:06AM +0530, Oza Pawandeep wrote:
>> this patch reserves the IOVA for PCI masters.
>> ARM64 based SOCs may have scattered memory banks.
>> such as iproc based SOC has
>>
>> <0x 0x8000 0x0 0x8000>,
On Sat, May 6, 2017 at 11:00 AM, Oza Oza wrote:
> On Fri, May 5, 2017 at 8:55 PM, Robin Murphy wrote:
>> On 04/05/17 19:41, Oza Oza wrote:
>> [...]
>>>>> 5) leaves scope of adding PCI flag handling for inbound memory
>>>>> by the new function.
>
On Mon, May 15, 2017 at 2:45 PM, Sagi Grimberg wrote:
>
>>> Hi,
>
>
> Hi Oza,
>
>>> we are configuring interrupt coalesce for NVMe, but right now, it uses
>>> module param.
>>> so the same interrupt coalesce settings get applied for all the NVMEs
>>> connected to different RCs.
>>>
>>> ideally it
On Mon, May 15, 2017 at 2:04 PM, Oza Oza wrote:
> Hi,
>
> we are configuring interrupt coalesce for NVMe, but right now, it uses
> module param.
> so the same interrupt coalesce settings get applied for all the NVMEs
> connected to different RCs.
>
> ideally it should b
Hi,
we are configuring interrupt coalesce for NVMe, but right now, it uses
module param.
so the same interrupt coalesce settings get applied for all the NVMEs
connected to different RCs.
ideally it should be with sysctl.
for e.g.
sysctl should provide interface to change
Per-CPU IO queue pairs, i
On Fri, May 5, 2017 at 9:21 PM, Robin Murphy wrote:
> On 04/05/17 19:52, Oza Oza wrote:
>> On Thu, May 4, 2017 at 11:50 PM, Robin Murphy wrote:
>>> On 03/05/17 05:46, Oza Pawandeep wrote:
>>>> this patch reserves the iova for PCI masters.
>>>> ARM64
On Fri, May 5, 2017 at 8:55 PM, Robin Murphy wrote:
> On 04/05/17 19:41, Oza Oza wrote:
> [...]
>>>> 5) leaves scope of adding PCI flag handling for inbound memory
>>>> by the new function.
>>>
>>> Which flags would ever actually matter? DMA windo
On Thu, May 4, 2017 at 11:50 PM, Robin Murphy wrote:
> On 03/05/17 05:46, Oza Pawandeep wrote:
>> this patch reserves the iova for PCI masters.
>> ARM64 based SOCs may have scattered memory banks.
>> such as iproc based SOC has
>>
>> <0x 0x8000 0x0 0x8000>, /* 2G @ 2G */
>> <0x
On Thu, May 4, 2017 at 11:32 PM, Robin Murphy wrote:
> [apologies for the silence - I've been on holiday]
>
> On 03/05/17 05:46, Oza Pawandeep wrote:
>> current device framework and of framework integration assumes
>> dma-ranges in a way where memory-mapped devices define their
>> dma-ranges. (chi
On Thu, May 4, 2017 at 11:50 PM, Robin Murphy wrote:
> On 03/05/17 05:46, Oza Pawandeep wrote:
>> this patch reserves the iova for PCI masters.
>> ARM64 based SOCs may have scattered memory banks.
>> such as iproc based SOC has
>>
>> <0x 0x8000 0x0 0x8000>, /* 2G @ 2G */
>> <0x
On Thu, May 4, 2017 at 11:32 PM, Robin Murphy wrote:
> [apologies for the silence - I've been on holiday]
>
> On 03/05/17 05:46, Oza Pawandeep wrote:
>> current device framework and of framework integration assumes
>> dma-ranges in a way where memory-mapped devices define their
>> dma-ranges. (chi
I will send v2 after removing GERRIT details from
commit message. My apologies for the noise.
Regards,
Oza
I will send v2 after removing GERRIT details from
commit message. My apologies for the noise.
Regards,
Oza
I will send v2 after removing GERRIT details from
commit message. My apologies for the noise.
Regards,
Oza
On Mon, Apr 24, 2017 at 7:50 PM, Rob Herring wrote:
> On Sat, Apr 22, 2017 at 3:08 AM, Oza Pawandeep wrote:
>> current device frmework and of framework integration assumes dma-ranges
>> in a way where memory-mapped devices define their dma-ranges.
>> dma-ranges: (child-bus-address, parent-bus-add
On Tue, Mar 28, 2017 at 7:43 PM, Rob Herring wrote:
> On Tue, Mar 28, 2017 at 12:27 AM, Oza Oza wrote:
>> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep
>>> wrote:
>>>> it is possible that PC
On Wed, Mar 29, 2017 at 10:13 AM, Oza Oza wrote:
> On Tue, Mar 28, 2017 at 7:59 PM, Robin Murphy wrote:
>> On 28/03/17 06:27, Oza Oza wrote:
>>> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>>>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep
>>>
On Tue, Mar 28, 2017 at 7:59 PM, Robin Murphy wrote:
> On 28/03/17 06:27, Oza Oza wrote:
>> On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
>>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep
>>> wrote:
>>>> it is possible that PCI device supports 64
On Mon, Mar 27, 2017 at 8:16 PM, Rob Herring wrote:
> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
>> it is possible that PCI device supports 64-bit DMA addressing,
>> and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
>> however PCI host bridge may have limitations on the
please find my comments inline.
On Mon, Mar 27, 2017 at 8:15 PM, Robin Murphy wrote:
> Hi Rob,
>
> On 27/03/17 15:34, Rob Herring wrote:
>> On Sat, Mar 25, 2017 at 12:31 AM, Oza Pawandeep wrote:
>>> it jumps to the parent node without examining the child node.
>>> also with that, it throws "no d
Hi Robin,
I have made 3 separate patches now, which gives clear idea about the
changes.
we can have discussion there.
Regards,
Oza.
-Original Message-
From: Robin Murphy [mailto:robin.mur...@arm.com]
Sent: Monday, March 20, 2017 9:14 PM
To: Oza Oza
Cc: Joerg Roedel; linux
Hi Robin,
Please find my comments inline.
Regards,
Oza.
-Original Message-
From: Robin Murphy [mailto:robin.mur...@arm.com]
Sent: Monday, March 20, 2017 9:14 PM
To: Oza Oza
Cc: Joerg Roedel; linux-...@vger.kernel.org;
io...@lists.linux-foundation.org; linux-kernel@vger.kernel.org;
linux
+ linux-pci
Regards,
Oza.
-Original Message-
From: Oza Pawandeep [mailto:oza@broadcom.com]
Sent: Friday, March 17, 2017 11:41 AM
To: Joerg Roedel; Robin Murphy
Cc: io...@lists.linux-foundation.org; linux-kernel@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; devicet...@vger.ke
the commit message)
There are some minor glitches it remains with, which is open for feedback
and improvement.
And this could be split later into separate patches, once you see it as a
potential scope for solving the problem statement end to end.
Regards,
Oza.
-Original Message-
From: Oza
Hi,
There are certain areas which requires contemplation.
And this problem requires more attention from Pci of framework and iommu,
and integration of both.
Regards,
Oza.
-Original Message-
From: Oza Pawandeep [mailto:oza@broadcom.com]
Sent: Friday, March 17, 2017 11:41 AM
To: Joerg
[ 20.161036] [] generic_handle_irq+0x24/0x38
[ 20.166962] [] __handle_domain_irq+0x5c/0xb8
[ 20.172977] [] gic_handle_irq+0xbc/0x168
Regards,
Oza.
-Original Message-
From: Oza Oza [mailto:oza@broadcom.com]
Sent: Tuesday, March 14, 2017 5:16 PM
To: 'Robin Murphy'; 'J
My responses inline:
-Original Message-
From: Robin Murphy [mailto:robin.mur...@arm.com]
Sent: Tuesday, March 14, 2017 4:27 PM
To: Oza Pawandeep; Joerg Roedel
Cc: io...@lists.linux-foundation.org; linux-kernel@vger.kernel.org;
linux-arm-ker...@lists.infradead.org;
bcm-kernel-feedback-l...@
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