On 27-02-2019 21:05, Mark Brown wrote:
> On Wed, Feb 27, 2019 at 08:41:46PM +0100, Olliver Schinagl wrote:
>> On 25-02-2019 18:25, Mark Brown wrote:
>>> If you find you need to describe what the fields are it would be much
>>> more constructive to add a comment at the t
On 25-02-2019 18:25, Mark Brown wrote:
> On Sat, Feb 23, 2019 at 09:37:01PM +0100, Olliver Schinagl wrote:
>
>> In any case, you seem like a smart person that reads and writes hex and
>> bits often enough. This is not true for everyone. I can just as easily
>> reverse your
On 23-02-2019 13:54, Axel Lin wrote:
>> I will not disagree that it may be extra work to look up the define
>> (especially if there is no tool tip or split view in the editor) but
>> reading the whole lot of code, with only the magic values, you still
>> have to look up the meaning of each magic va
On 21-02-2019 10:42, Mark Brown wrote:
> On Thu, Feb 21, 2019 at 08:22:53AM +0800, Axel Lin wrote:
>> Olliver Schinagl 於 2019年2月21日 週四 上午6:57寫道：
>>> On February 20, 2019 5:50:13 PM GMT+01:00, Axel Lin
>>> wrote:
>>>> The AXP20X_xxx_START/END/STEPS
Hey Axel,
On February 20, 2019 5:50:13 PM GMT+01:00, Axel Lin wrote:
>The AXP20X_xxx_START/END/STEPS defines make the code hard to read and
>very hard to check the linear range settings because it needs to check
>the defines one-by-one.
>The original code without the defines is very good in reada
Hey Marcus,
On 29-07-17 16:17, codekip...@gmail.com wrote:
From: Marcus Cooper
Hi All,
please find attached a series of patches to bring i2s support to the
Allwinner H3 SoC. This has been tested with the following setups:
A20 Olimex EVB connected to a pcm5102
But that's not an H3 is it? :)
Hey Priit,
On 07/13/17 21:23, Priit Laes wrote:
> On Mon, Jul 10, 2017 at 11:45:32AM +0200, Olliver Schinagl wrote:
>> Hi Pleas,
>>
>> again, but this time with content :)
>>
>> On 04-07-17 22:04, Priit Laes wrote:
>>> Introduce a clock controller dri
Hey Jonathan,
since I reported this to you on IRC, it's only fair that you can have my:
Tested-by: Olliver Schinagl
For those interessted, I've tested it on an Olimex OLinuXino Lime2 with
their 4.3 LCD.
Olliver
On 10-07-17 08:55, Jonathan Liu wrote:
The drm_driver lastclose c
Hi Maxime,
On 10-07-17 13:55, Maxime Ripard wrote:
On Mon, Jul 10, 2017 at 01:23:51PM +0200, Olliver Schinagl wrote:
Hi Pleas,
On 04-07-17 22:05, Priit Laes wrote:
Convert sun7i-a20.dtsi to new CCU driver.
Tested on Cubietruck.
Signed-off-by: Priit Laes
---
arch/arm/boot/dts/sun7i-a20
Hi Pritt,
On 04-07-17 22:05, Priit Laes wrote:
Convert sun4i-a10.dtsi to new CCU driver.
Tested on Gemei G9 tablet.
Signed-off-by: Priit Laes
---
arch/arm/boot/dts/sun4i-a10.dtsi | 646 +++-
1 file changed, 73 insertions(+), 573 deletions(-)
diff --git a/arch/arm
Hi Pleas,
On 04-07-17 22:05, Priit Laes wrote:
Convert sun7i-a20.dtsi to new CCU driver.
Tested on Cubietruck.
Signed-off-by: Priit Laes
---
arch/arm/boot/dts/sun7i-a20.dtsi | 719 +++-
1 file changed, 84 insertions(+), 635 deletions(-)
diff --git a/arch/arm/boot
Hi Pleas,
again, but this time with content :)
On 04-07-17 22:04, Priit Laes wrote:
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.
Signed-off-by: Priit Laes
---
drivers/clk/sunxi-ng/Kconfig | 14 +-
drivers/clk/sunxi-ng/Makefile |1
Hey Plaes,
On 04-07-17 22:04, Priit Laes wrote:
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes
---
drivers/clk/sunxi-ng/ccu_div.c | 18 --
drivers/clk/sunxi-ng/ccu_div.h | 3 ++-
2 files changed, 18 insertions(+)
Hey Tim,
On 04-05-17 05:51, Tim Kryger wrote:
On Wed, May 3, 2017 at 8:40 AM, Olliver Schinagl wrote:
Hey Tim,
Ok, so as far as I understand (from the datasheet) the intended way to do
this would be to check for the BUSY IRQ & USR[0] IRQ and if it is busy,
(re-write) the LCR. We no lo
Hey Tim,
On 03-05-17 16:22, Tim Kryger wrote:
On Wed, May 3, 2017 at 4:26 AM, Olliver Schinagl wrote:
Hey Chen-Yu
On 03-05-17 12:40, Chen-Yu Tsai wrote:
On Wed, May 3, 2017 at 6:17 PM, Olliver Schinagl
wrote:
Hey Jamie,
Several years ago you wrote the glue-code [0] for the DW 8250 IP
Hey Chen-Yu
On 03-05-17 12:40, Chen-Yu Tsai wrote:
On Wed, May 3, 2017 at 6:17 PM, Olliver Schinagl wrote:
Hey Jamie,
Several years ago you wrote the glue-code [0] for the DW 8250 IP. Over the
years various 'fixes' have been applied to resolve certain 'weird' problems
t
Hey Jamie,
Several years ago you wrote the glue-code [0] for the DW 8250 IP. Over
the years various 'fixes' have been applied to resolve certain 'weird'
problems that Tim tried to fix with [1].
After going over the datasheets and code with a comb several times now,
I think I may have found o
Hey Andy,
On 30-03-17 11:56, Andy Shevchenko wrote:
On Wed, 2017-03-29 at 20:44 +0200, Olliver Schinagl wrote:
It seems that at some point, someone made the assumption that the UART
Interrupt ID Register was a bitfield and started to check if certain
bits where set.
Actually however the
7;ll turn it into a set.
Again, sorry for the inconvenience,
Olliver
-Original Message-
From: Laxman Dewangan
Sent: Thursday, March 30, 2017 3:48 PM
To: Olliver Schinagl ; Greg Kroah-Hartman
; Jiri Slaby ; Stephen
Warren ; Thierry Reding
; Alexandre Courbot
Cc: linux-ser...@vger.
Hey Ted,
On 30-03-17 16:11, Theodore Ts'o wrote:
While you're fixing this, there's a bug in samples/vfio-mdev/mtty.c:
u8 ier = mdev_state->s[index].uart_reg[UART_IER];
*buf = 0;
mutex_lock(&mdev_state->rxtx_lock);
/* Interrupt pri
Hey Vignesh,
On March 30, 2017 9:57:19 AM CEST, Vignesh R wrote:
>
>
>On Thursday 30 March 2017 12:13 PM, Olliver Schinagl wrote:
>>
>>
>> On March 30, 2017 8:15:29 AM CEST, Vignesh R wrote:
>>> Hi,
>>>
>>> On Thursday 30 March 2017 12:14
Hey Jon,
On March 30, 2017 3:42:19 PM CEST, Jon Hunter wrote:
>
>On 29/03/17 19:48, Olliver Schinagl wrote:
>> The tegra serial IP seems to be following the common layout and the
>> interrupt ID's match up nicely. Replace the magic values to match the
>> common
On March 30, 2017 8:15:29 AM CEST, Vignesh R wrote:
>Hi,
>
>On Thursday 30 March 2017 12:14 AM, Olliver Schinagl wrote:
>> diff --git a/include/uapi/linux/serial_reg.h
>b/include/uapi/linux/serial_reg.h
>> index 5db76880b4ad..489522389a10 100644
>> --- a/include/ua
The tegra serial IP seems to be following the common layout and the
interrupt ID's match up nicely. Replace the magic values to match the
common serial_reg defines, with the addition of the Tegra unique End of
Data interrupt.
Signed-off-by: Olliver Schinagl
---
Note I do not own any
IR_EXT_MASK for these two bits.
This patch then goes over all UART_IIR_* users and changes the code from
bitfield checking, to ID checking instead.
Signed-off-by: Olliver Schinagl
---
Note, that I do not have all this hardware and used the fact that UART_IIR_*
yields ID's rather then bitfiel
Some very minor code cleanups, such as including the bitops header for
DW_UART_MCR_SIRE, use the BIT() macro as suggested by checkpatch and
removed a white space to match other invocations.
Signed-off-by: Olliver Schinagl
---
Changes since v1:
Split up these non-code changing changes into a
Hey Doug,
On 29-03-17 19:10, Olliver Schinagl wrote:
Hey Doug,
On 29-03-17 17:50, Doug Anderson wrote:
Hi,
On Wed, Mar 29, 2017 at 3:04 AM, Olliver Schinagl
wrote:
Commit 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from
bogus rx timeout interrupt")
added a bi
Hey Doug,
On 29-03-17 17:50, Doug Anderson wrote:
Hi,
On Wed, Mar 29, 2017 at 3:04 AM, Olliver Schinagl wrote:
Commit 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout
interrupt")
added a bit check with quite a wide mask. To be concise with the
ic value/mask.
Some very minor code cleanups, such as including the bitops header for
DW_UART_MCR_SIRE, use the BIT() macro as suggested by checkpatc and
removed a whitespace to match other invocations.
Signed-off-by: Olliver Schinagl
---
drivers/tty/serial/8250/8250_dw.c | 25 +
Hey Andy,
On 29-03-17 11:11, Andy Shevchenko wrote:
On Wed, Mar 29, 2017 at 10:58 AM, Olliver Schinagl wrote:
On 07-02-17 00:30, Douglas Anderson wrote:
First of all I didn't get why people from Cc list are suddenly
disappeared. Check your mail client settings.
Returning back some of
Hey Douglas,
On 07-02-17 00:30, Douglas Anderson wrote:
On a Rockchip rk3399-based board during suspend/resume testing, we
found that we could get the console UART into a state where it would
print this to the console a lot:
serial8250: too much work for irq42
Followed eventually by:
NMI wa
tleast function properly
according to its parameters?
Olliver
On 01-03-17 14:58, Olliver Schinagl wrote:
Hey all,
We found a bug in the design of a board that we use. This board (Olimex
OLinuXino Lime2) features a PMIC (AXP209) and has an LDO, LDO3, that
needs special treatment.
The bug is
Hey all,
We found a bug in the design of a board that we use. This board (Olimex
OLinuXino Lime2) features a PMIC (AXP209) and has an LDO, LDO3, that
needs special treatment.
The bug is, that there is too much capacitance on the output of LDO3,
which causes the PMIC to shutdown when enabelin
Hey Alexandre,
Sorry for the very slow reply. We just bought a house so have been
offline for 6+ weeks!
On 03-01-17 17:44, Alexandre Belloni wrote:
On 03/01/2017 at 16:56:16 +0100, Olliver Schinagl wrote :
Hey Alexandre,
I've sent several patches regarding pwm a while ago, sadly you
Hey Alexandre,
I've sent several patches regarding pwm a while ago, sadly you never
responded [0]. So I guess this is a follow up from that?
I couldn't quickly find the resubmitted version however.
Anyway, see below for my comments.
On 03-01-17 15:57, Alexandre Belloni wrote:
Most of the ca
Hey Maxime,
Happy new year! I'm sorry that I missed your previous mail! I completely
looked over it. Sorry!
On 12-12-16 13:24, Maxime Ripard wrote:
On Thu, Dec 08, 2016 at 02:23:39PM +0100, Olliver Schinagl wrote:
Hey Maxime,
first off, also sorry for the slow delay :) (pun not int
On za, 2016-09-24 at 22:25 +0200, Maxime Ripard wrote:
> Hi Oliver,
>
> Sorry for the slow answer.
>
> On Fri, Sep 09, 2016 at 11:01:08AM +0200, Olliver Schinagl wrote:
> >
> > >
> > > >
> > > > >
> > > > > >
>
, it may be contemplated to use a
half period + a little bit to ensure we get passed the transition.
Signed-off-by: Olliver Schinagl
---
drivers/pwm/pwm-sun4i.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 03a99a5
On di, 2016-09-06 at 21:51 +0200, Maxime Ripard wrote:
> On Tue, Sep 06, 2016 at 09:12:56AM +0200, Olliver Schinagl wrote:
> >
> > Hi Maxime!,
> >
> > On za, 2016-08-27 at 00:19 +0200, Maxime Ripard wrote:
> > >
> > > On Thu, Aug 25, 201
Hi Anders,
On ma, 2016-09-05 at 13:02 +0200, Anders Darander wrote:
> Hi,
>
> * Olliver Schinagl [160504 10:10]:
> >
> > On 04-05-16 09:55, Anders Darander wrote:
> > >
> > > * Jacek Anaszewski [160504 09:28]:
> > > >
> > >
Hi Maxime!,
On za, 2016-08-27 at 00:19 +0200, Maxime Ripard wrote:
> On Thu, Aug 25, 2016 at 07:50:10PM +0200, Olliver Schinagl wrote:
> >
> > When we inform the PWM block to stop toggeling the output, we may
> > end up
> > in a state where the output is not wha
Checkpatch warns about not using the BIT() macro. Replace 1 << bit with
BIT().
Signed-off-by: Olliver Schinagl
---
Hi Thierry,
I submitted this patch a year ago and you said you didn't much care for it.
After a year however, have you changed your mind? I notice it's becoming
m
From: Olliver Schinagl
The pwm-block of some of the sunxi chips feature a 'ready' flag to
indicate the software that it is ready for new commands.
Right now, when we call pwm_config and set the period, we write the
values to the registers, and turn off the clock to the IP. Because of
xtra delay (of one bus clock cycle?) is overkill.
Changes since v1:
- Split patch series into several smaller patch series
- Added driver author
Olliver Schinagl (2):
pwm: sunxi: allow the pwm to finish its pulse before disable
pwm: sunxi: Yield some time to the pwm-block to be
transition.
Signed-off-by: Olliver Schinagl
---
drivers/pwm/pwm-sun4i.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 03a99a5..5e97c8a 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -8,6 +8,7 @@
#include
The lpc18xx driver currently manipulates the pwm_device struct directly
rather then using the pwm_set_chip_data. While the current method may
save a clock cycle or two, it is more obvious that data is set to
the local chip data pointer.
Signed-off-by: Olliver Schinagl
---
Hi,
This is a resend
On 15-07-16 10:39, stefan.mavrod...@gmail.com wrote:
Hi Olliver,
Why are you using nRST signal?
What I mean is this pin is inactive on this eMMC chip. To use the signal
byte 162 of ECSD registers should be written.
Then that sounds like a bug in the mmc layer I would say (or a missing
attribute
commit 27dd9af6bc000ab21fd ("ARM: dts: sunxi: Add a olinuxino-lime2-emmc")
added the new emmc equipped lime2 but forgot its Makefile.
This patch adds an entry to the Makefile.
Signed-off-by: Olliver Schinagl
---
Changes since v1:
Added proper commit reference (again).
Change
and now i'm embarrassed and ashamed. Teaches me not to rush things,
right? i'll correct it and take some time to do it right. sorry maxime!
On 13-05-16 09:48, Maxime Ripard wrote:
Hi Olliver,
On Thu, May 12, 2016 at 12:10:51PM +0200, Olliver Schinagl wrote:
commit 27dd9af6bc (ARM:
commit 27dd9af6bc (ARM: dts: sunxi: Add a olinuxino-lime2-emmc added the new
emmc equipped) lime2 but forgot its Makefile.
This patch adds an entry to the Makefile.
Signed-off-by: Olliver Schinagl
---
Changes since v0:
Added proper commit reference.
arch/arm/boot/dts/Makefile | 1 +
1 file
old you that I will review
this yesterday, but I did not have the time , sorry
Regards!
On 22 Apr 2016 09:21, "Olliver Schinagl" wrote:
Hi Ricardo,
On 20-04-16 11:17, Ricardo Ribalda Delgado wrote:
Hello again
On Wed, Apr 20, 2016 at 11:06 AM, Olliver Schinagl
wrote:
The devil is
old you that I will review
this yesterday, but I did not have the time , sorry
Regards!
On 22 Apr 2016 09:21, "Olliver Schinagl" wrote:
Hi Ricardo,
On 20-04-16 11:17, Ricardo Ribalda Delgado wrote:
Hello again
On Wed, Apr 20, 2016 at 11:06 AM, Olliver Schinagl
wrote:
The devil is
ARM: dts: sunxi: Add a olinuxino-lime2-emmc added the new emmc equipped
lime2 but forgot its Makefile. This patch adds an entry to the Makefile.
Signed-off-by: Olliver Schinagl
---
Hi list,
would it be possible to squash or atleast add this patch with/to my previous
patch, ARM: dts: sunxi: Add
ARM: dts: sunxi: Add a olinuxino-lime2-emmc added the new emmc equipped
lime2 but forgot its Makefile. This patch adds an entry to the Makefile.
Signed-off-by: Olliver Schinagl
---
Maxime, I'm sorry for ommitting the Makefile initially, if it is not merged yet,
maybe just squash it wit
Michael,
On 04-05-16 17:18, Olliver Schinagl wrote:
Hi Michael,
On 28-04-16 20:18, Olliver Schinagl wrote:
Hi Michael,
I know i'm a little late to the party, but why did you not name the
directory/driver pn53x? I don't think we should debate wether a 533 is a
532 with a USB added,
Hey Maxime,
On 08-05-16 20:09, Maxime Ripard wrote:
On Thu, May 05, 2016 at 11:08:52AM +0200, Olliver Schinagl wrote:
There are 3 kinds of OLinuXino Lime2 boards.
One without any on board storage, one with NAND storage and one with
eMMC storage. This patch adds the eMMC variant of boards
shares pins with
the NAND module and with the second SPI port.
Changeslog:
v4:
Add board compatibles
v3:
Add pwr-seq-emmc with the reset gpio
v2:
Remove unsupported no-1.8-v property, add vqmmc property
v1:
Initial bare bone version
Signed-off-by: Olliver Schinagl
---
.../boot/dts
Hi Michael,
I know this is an old patch already applied, but I noticed the following:
On 25-03-16 15:46, Michael Thalmeier wrote:
This adds the I2C phy interface for the pn533 driver. This way the driver can
be used to interact with I2C connected pn532.
Signed-off-by: Michael Thalmeier
---
Hi Michael,
On 28-04-16 20:18, Olliver Schinagl wrote:
Hi Michael,
I know i'm a little late to the party, but why did you not name the
directory/driver pn53x? I don't think we should debate wether a 533 is a
532 with a USB added, or wether a 532 is a 533 with the USB stripped,
shares pins with
the NAND module and with the second SPI port.
Signed-off-by: Olliver Schinagl
---
.../boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts| 81 ++
1 file changed, 81 insertions(+)
create mode 100644 arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
diff --git
Hey Radoslav,
On 04-05-16 14:30, Radoslav Kolev wrote:
2016-05-03 10:25 GMT+03:00 Chen-Yu Tsai :
On Tue, May 3, 2016 at 3:21 PM, Olliver Schinagl wrote:
+ bus-width = <4>;
Only 4 bits? We normally see eMMC with 8 bits. 4 bits are some kind of
embedded SD card.
On A20 as wel
Hey Jacek,
On 04-05-16 09:55, Anders Darander wrote:
Hi,
Thanks for the info.
* Jacek Anaszewski [160504 09:28]:
Please note that there has already been an attempt to add
the support for inverted output polarity to this driver and related
discussion [1]. This thread remains quiet for around
Hey all,
On 03-05-16 17:02, christo.ra...@gmail.com wrote:
On Tuesday, May 3, 2016 at 4:14:41 PM UTC+3, Maxime Ripard wrote:
Hi,
On Tue, May 03, 2016 at 4:12:06 PM UTC+3, Christo Radev wrote:
Hi to All,
I have already solved and tested this issue on Armbian build. Find
patches for both lega
shares pins with
the NAND module and with the second SPI port.
Signed-off-by: Olliver Schinagl
---
.../boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts| 64 ++
1 file changed, 64 insertions(+)
create mode 100644 arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
diff --git
Hey Chen,
On 03-05-16 05:33, Chen-Yu Tsai wrote:
Hi,
On Thu, Apr 28, 2016 at 3:19 PM, Olliver Schinagl wrote:
There are 3 kinds of OLinuXino Lime2 boards.
One without any on board storage, one with NAND storage and one with
eMMC storage. This patch adds the eMMC variant of boards.
eMMC
Hi Michael,
I know i'm a little late to the party, but why did you not name the
directory/driver pn53x? I don't think we should debate wether a 533 is a
532 with a USB added, or wether a 532 is a 533 with the USB stripped, I
was just curious. As for the pn533-i2c, in the KConfig, I'd probably
shares pins with
the NAND module and with the second SPI port.
Signed-off-by: Olliver Schinagl
---
.../boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts| 64 ++
1 file changed, 64 insertions(+)
create mode 100644 arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
diff --git
On April 22, 2016 3:09:35 PM CEST, Rob Herring wrote:
>On Fri, Apr 22, 2016 at 7:38 AM, Olliver Schinagl
>wrote:
>> Hey Rob,
>>
>> On 21-04-16 17:07, Rob Herring wrote:
>>>
>>> On Tue, Apr 19, 2016 at 09:40:49AM +0200, Olliver Schinagl wrote:
>>
Hey Rob,
On 21-04-16 17:07, Rob Herring wrote:
On Tue, Apr 19, 2016 at 09:40:49AM +0200, Olliver Schinagl wrote:
When leds are connected in a totem-pole configuration, they can be
connected either in a active-high, or active-low manor. The driver
currently always assumes active-high. This
Hi Ricardo,
On 20-04-16 11:17, Ricardo Ribalda Delgado wrote:
Hello again
On Wed, Apr 20, 2016 at 11:06 AM, Olliver Schinagl wrote:
The devil is in the details :)
:)
Saving mode2 sounds like a good compromise then.
But I still believe that we should limit the lock to ledout. No matter
Hey,
On 20-04-16 11:17, Ricardo Ribalda Delgado wrote:
Hello again
On Wed, Apr 20, 2016 at 11:06 AM, Olliver Schinagl wrote:
The devil is in the details :)
:)
Saving mode2 sounds like a good compromise then.
But I still believe that we should limit the lock to ledout. No matter
what we
On 20-04-16 10:56, Ricardo Ribalda Delgado wrote:
Hi
On Wed, Apr 20, 2016 at 10:51 AM, Olliver Schinagl wrote:
As I said before, the reason for this proposal is that the code NEVER
clears PCA963X_MODE2_DMBLNK, only sets it.
Unfortunately I do not have the HW to test this change.
The code
Hey Ricardo,
On 20-04-16 10:01, Ricardo Ribalda Delgado wrote:
Hi Ollivier
On Wed, Apr 20, 2016 at 9:21 AM, Olliver Schinagl wrote:
What I am propossing is at probe():
replace:
if (pdata) {
/* Configure output: open-drain or totem pole (push-pull) */
if (pdata->out
Hey Ricardo,
On 19-04-16 15:42, Ricardo Ribalda Delgado wrote:
Hi again
On Tue, Apr 19, 2016 at 3:27 PM, Olliver Schinagl wrote:
Hey Ricardo,
Without actually looking at the code right now, but the driver does a
read/modify/write on the register, and a register is shared among several
leds
lusive/easy to use.
But I can remove unused defines if desired.
For PCA963X_LEDOUT_LDR. Do not forget the parenthesis around led_num.
Also replace %4 with &3 to be consisten.t
Yeah, i'll check and fix that.
Regards!
On Tue, Apr 19, 2016 at 11:39 AM, Olliver Schinagl wrote
Hey Hans,
On 19-04-16 13:22, Hans de Goede wrote:
Hi,
On 19-04-16 11:42, Olliver Schinagl wrote:
Hi Ulf,
On 19-04-16 11:29, Ulf Hansson wrote:
On 19 April 2016 at 09:12, Olliver Schinagl wrote:
In patch 81f8a7be66 Hans de Goede added a patch to allow marking an
mmc
device as to having an
Hey Sergei,
On 19-04-16 12:52, Sergei Shtylyov wrote:
Hello.
On 4/19/2016 10:12 AM, Olliver Schinagl wrote:
In patch 81f8a7be66 Hans de Goede added a patch to allow marking an mmc
scripts/checkpatch.pl now enforces certain commit citing style, the
commit summary should be specified too
Hey Jaehoon,
On 19-04-16 11:49, Jaehoon Chung wrote:
Hi
On 04/19/2016 06:42 PM, Olliver Schinagl wrote:
Hi Ulf,
On 19-04-16 11:29, Ulf Hansson wrote:
On 19 April 2016 at 09:12, Olliver Schinagl wrote:
In patch 81f8a7be66 Hans de Goede added a patch to allow marking an mmc
device as to
Hi Ulf,
On 19-04-16 11:29, Ulf Hansson wrote:
On 19 April 2016 at 09:12, Olliver Schinagl wrote:
In patch 81f8a7be66 Hans de Goede added a patch to allow marking an mmc
device as to having an broken HPI implementation. After talking some
with Hans, we now think it is actually the mmc
whole set.
Olliver
On 04/19/2016 09:40 AM, Olliver Schinagl wrote:
Using the pca963x for a while, I noticed something that may look like
some
i2c accessing issues where sometimes data was incorrectly written to
the bus,
possibly because we where not properly locking the i2c reads. Thoug
introduce any binary changes.
Signed-off-by: Olliver Schinagl
---
drivers/leds/leds-pca963x.c | 53 -
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/leds/leds-pca963x.c b/drivers/leds/leds-pca963x.c
index 85dd506..5c4bf77 100644
--- a
This patch uses the newly introduced defines to further reduce magic
values and magic shifts. These changes have a slightly bigger impact as
they do introduce binary changes. There should be no logical changes
however.
Signed-off-by: Olliver Schinagl
---
drivers/leds/leds-pca963x.c | 32
or rather, that the behavior is inverted to what
is normally expected.
Signed-off-by: Olliver Schinagl
---
Documentation/devicetree/bindings/leds/pca963x.txt | 1 +
drivers/leds/leds-pca963x.c| 20 +---
include/linux/platform_data/leds-pca963x.h | 1
Re-order headers so they are in alphabetical order.
Signed-off-by: Olliver Schinagl
---
drivers/leds/leds-pca963x.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/leds/leds-pca963x.c b/drivers/leds/leds-pca963x.c
index 407eba1..8dabf7a 100644
--- a
does some cleanups to please checkpatch, and
removes a few magic values.
Olliver Schinagl (6):
leds: pca963x: Alphabetize headers
leds: pca963x: Lock i2c r/w access
leds: pca963x: Add defines and remove some magic values
leds: pca963x: Reduce magic values
leds: pca963x: Inform the output
This patch adds some more defines so that the driver can receive
a little more future work. These new defines are then used throughout the
existing code the remove some magic values.
This patch does not produce any binary changes.
Signed-off-by: Olliver Schinagl
---
drivers/leds/leds-pca963x.c
A pca963x device can have multiple leds with a single i2c channel to
access them. Some of the registers are shared between each other. To
ensure all i2c operations are atomic within an instance, we move some
mutex locks slightly around to guard these access.
Signed-off-by: Olliver Schinagl
n-hpi, which allows us to
mark a broken hpi implementation on the host level.
Signed-off-by: Olliver Schinagl
---
drivers/mmc/core/host.c | 2 ++
drivers/mmc/core/mmc.c | 2 +-
include/linux/mmc/host.h | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/core/hos
So far it seems all sunxi MMC controllers have a broken HPI. Until
proved otherwise, mark all sunxi mmc controllers as having a broken HPI.
Signed-off-by: Olliver Schinagl
---
drivers/mmc/host/sunxi-mmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host
those should in theory be
removed from the boards in question in a separate patch when in agreement, as
technically, the eMMC module supports HPI just fine and thus the we are lying
about what really is broken.
This was tested on an OLinuXino Lime2 with 4GB industrial grade Micron eMMC
flash.
Ol
Hey Thierry,
On 06-11-15 17:05, Thierry Reding wrote:
On Fri, Nov 06, 2015 at 04:46:54PM +0100, Olliver Schinagl wrote:
Hey Thierry,
On 06-11-15 16:18, Thierry Reding wrote:
On Mon, Oct 26, 2015 at 10:32:39PM +0100, Olliver Schinagl wrote:
From: Olliver Schinagl
Some hardware PWM's
Hey Thierry,
On 06-11-15 16:18, Thierry Reding wrote:
On Mon, Oct 26, 2015 at 10:32:39PM +0100, Olliver Schinagl wrote:
From: Olliver Schinagl
Some hardware PWM's have the possibility to only send out one (or more)
pulses. This can be quite a useful feature in case one wants or needs
o
red or not.
Olliver
On 06-11-15 15:46, Thierry Reding wrote:
On Mon, Oct 26, 2015 at 10:32:35PM +0100, Olliver Schinagl wrote:
From: Olliver Schinagl
The pwm header defines bits manually while there is a nice bitops.h with
a BIT() macro. Use the BIT() macro to set bits in pwm.h
Signed-off-by: Ollive
Hey Rob,
On October 27, 2015 8:42:48 AM CET, Rob Herring wrote:
>On Mon, Oct 26, 2015 at 4:32 PM, Olliver Schinagl
> wrote:
>> From: Olliver Schinagl
>>
>> This patch adds a bit-banging gpio PWM driver. It makes use of
>hrtimers,
>> to allow nano-second resolut
etter here.
>
>Also, get_maintainer.pl is just a hint, and not meant to be used as-is.
>In particular, you are missing the driver's author.
>
>On 26 October 2015 at 18:32, Olliver Schinagl
> wrote:
>> From: Olliver Schinagl
>>
>> The lpc18xx driver curren
From: Olliver Schinagl
Use the result of pwm_is_enabled directly instead of storing it first.
Signed-off-by: Olliver Schinagl
---
drivers/pwm/sysfs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pwm/sysfs.c b/drivers/pwm/sysfs.c
index c472772..ba67845 100644
From: Olliver Schinagl
This patch adds a bit-banging gpio PWM driver. It makes use of hrtimers,
to allow nano-second resolution, though it obviously strongly depends on
the switching speed of the gpio pins, hrtimer and system load.
Each pwm node can have 1 or more "pwm-gpio" entries,
From: Olliver Schinagl
With the newly added pwm_pulse option added to the PWM framework, this
patch adds the pulse functionality to the gpio_pwm driver.
Signed-off-by: Olliver Schinagl
---
drivers/pwm/pwm-gpio.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a
From: Olliver Schinagl
Some hardware PWM's have the possibility to only send out one (or more)
pulses. This can be quite a useful feature in case one wants or needs
only a single pulse, but at the exact width.
Additionally, if multiple pulses are possible, outputting a fixed amount
of p
From: Olliver Schinagl
With the new pulse mode addition to the PWM framework, we can make use
of this for the sunxi PWM.
WARNING: Do not merge yet, currently, we can only pulse once and a
manual disable is required to 'reset' the PWM framework. I haven't
thought through how t
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