On Fri, Apr 02, 2021 at 02:50:49PM +0530, Nava kishore Manne wrote:
> Adds support to handle FPGA/PL power domain. With this patch,
> the PL power domain will be turned on before loading the bitstream
> and turned off while removing/unloading the bitstream using overlays.
> This can be achieved by
On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
&g
Hi Matthew,
On Tue, Apr 06, 2021 at 09:05:35AM -0700, matthew.gerl...@linux.intel.com wrote:
>
> Hi Moritz,
>
> On Mon, 5 Apr 2021, Moritz Fischer wrote:
>
> > Hi Matthew,
> >
> > On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com
>
On Mon, Apr 05, 2021 at 04:52:59PM -0700, matthew.gerl...@linux.intel.com wrote:
> From: Russ Weight
>
> This patch adds the approved PCI Express Device IDs for the
> PF and VF for the card for D5005 PAC cards.
>
> Signed-off-by: Russ Weight
> Signed-off-by: Matthew Gerlach
> ---
> drivers/fp
Hi Matthew,
On Mon, Apr 05, 2021 at 04:53:00PM -0700, matthew.gerl...@linux.intel.com wrote:
> From: Matthew Gerlach
>
> This patch adds DFL bus driver for the Altera SPI Master
> controller. The SPI master is connected to an Intel SPI Slave to
> Avalon Master Bridge, inside an Intel MAX10 BMC
On Fri, Apr 02, 2021 at 02:50:48PM +0530, Nava kishore Manne wrote:
> Add fpga-region property 'power-domains' to allow to handle
> the FPGA/PL power domins.
>
> dt-bindings: fpga: Enable PM generic domain support
>
> Signed-off-by: Nava kishore Manne
> ---
> .../devicetree/bindings/fpga/fpga-r
Hi Geert,
On Fri, Apr 02, 2021 at 01:57:49PM +0200, Geert Uytterhoeven wrote:
> Using overlay sugar syntax makes the DTS files easier to read (and
> write).
>
> While at it, fix two build issues:
> - "/dts-v1/" and "/plugin/" must be separate statements.
> - Add a missing closing curly brace.
Hi Russ,
On Wed, Mar 31, 2021 at 11:47:26AM -0700, Russ Weight wrote:
> Moritz,
>
> On 3/28/21 10:20 AM, Moritz Fischer wrote:
> > Tom,
> >
> > On Sun, Mar 28, 2021 at 08:40:24AM -0700, Tom Rix wrote:
> >> On 3/27/21 11:09 AM, Moritz Fischer wrote:
> >&g
Hi Richard,
On Tue, Mar 30, 2021 at 09:33:05AM -0500, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Extend Intel service layer driver to get the firmware version running at
> FPGA device. Therefore FPGA manager driver, one of Intel service layer
> driver's client, can decide wheth
On Tue, Feb 09, 2021 at 04:20:29PM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Extend Intel service layer driver to get the firmware version running at
> FPGA device. Therefore FPGA manager driver, one of Intel service layer
> driver's client, can decide whether to handle
Tom,
On Sun, Mar 28, 2021 at 08:40:24AM -0700, Tom Rix wrote:
>
> On 3/27/21 11:09 AM, Moritz Fischer wrote:
> > Hi Richard, Russ,
> >
> > On Thu, Feb 25, 2021 at 01:07:14PM +, Gong, Richard wrote:
> >> Hi Moritz,
> >>
> >> Sorry for a
Hi Richard, Russ,
On Thu, Feb 25, 2021 at 01:07:14PM +, Gong, Richard wrote:
> Hi Moritz,
>
> Sorry for asking.
>
> When you have chance, can you help review the version 5 patchset submitted on
> 02/09/21?
>
> Regards,
> Richard
>
> -Original Message-
> From: richard.g...@linux.in
Be more verbose to disambiguate the error case when trying to configure
SRIOV with no driver bound vs. a driver that does not implement the
SRIOV callback.
Reported-by: Brian Foley
Reviewed-by: Krzysztof Wilczyński
Signed-off-by: Moritz Fischer
---
Changes from v1:
- Added Krzysztof's Rev
Hi Xu,
On Wed, Mar 24, 2021 at 04:22:17PM +0800, Xu Yilun wrote:
> Hi Moritz:
>
> Sorry I need to get back to you again, seems no more comments from Greg.
>
> The patchset is stuck here for more than 1 month. Do you have some
> more suggestion that could make it move forward? Do you have some mo
On Tue, Mar 23, 2021 at 03:46:50PM -0700, Russ Weight wrote:
> Port enable is not complete until ACK = 0. Change
> __afu_port_enable() to guarantee that the enable process
> is complete by polling for ACK == 0.
>
> Signed-off-by: Russ Weight
> Reviewed-by: Tom Rix
> Reviewed-by: Matthew Gerlach
On Mon, Feb 15, 2021 at 06:32:16AM -0800, Tom Rix wrote:
>
> On 2/15/21 6:41 AM, Richard Gong wrote:
> > Hi Tom,
> >
> > On 2/13/21 9:44 AM, Tom Rix wrote:
> >>
> >> On 2/9/21 2:20 PM, richard.g...@linux.intel.com wrote:
> >>> From: Richard Gong
> >>>
> >>> Clean up COMMAND_RECONFIG_FLAG_PARTIAL
Hi Krzysztof,
On Thu, Mar 11, 2021 at 04:27:35PM +0100, Krzysztof Kozlowski wrote:
> ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the
> 32-bit ARM drivers to rely on new symbol.
>
> Signed-off-by: Krzysztof Kozlowski
Acked-by: Moritz Fischer
> ---
> driver
Hi Tom,
On Tue, Mar 09, 2021 at 08:03:09AM -0800, Tom Rix wrote:
> Moritz,
>
> This and the next patchset apply to today's char-misc-next.
>
> However they conflicts with other in flight linux-fpga patchsets.
>
> Since I believe these patchsets came first, I think they should have
> preference.
On Mon, Mar 01, 2021 at 06:48:46AM +, Sonal Santan wrote:
> Hello Tom,
>
> > -Original Message-
> > From: Tom Rix
> > Sent: Friday, February 19, 2021 2:26 PM
> > To: Lizhi Hou ; linux-kernel@vger.kernel.org
> > Cc: Lizhi Hou ; linux-f...@vger.kernel.org; Max Zhen
> > ; Sonal Santan ;
On Thu, Feb 04, 2021 at 02:36:11PM +0100, Michal Simek wrote:
> Use already prepared dev_err_probe() introduced by commit a787e5400a1c
> ("driver core: add device probe log helper").
> It simplifies EPROBE_DEFER handling.
>
> Signed-off-by: Michal Simek
> ---
>
> drivers/fpga/xilinx-pr-decouple
On Thu, Feb 04, 2021 at 01:13:13PM +0100, Luca Ceresoli wrote:
> The current code produces an error message on devm_gpiod_get() errors even
> when the error is -EPROBE_DEFER, which should be silent.
>
> This has been observed producing a significant amount of messages like:
>
> xlnx-slave-spi
On Tue, Mar 02, 2021 at 10:49:43PM -0800, Joe Perches wrote:
> On Sun, 2021-02-21 at 12:43 -0800, Moritz Fischer wrote:
> > On Wed, Feb 17, 2021 at 10:40:01PM -0800, Lizhi Hou wrote:
> > > This is V3 of patch series which adds management physical function driver
> > >
Hi Nava,
On Thu, Jan 21, 2021 at 09:17:10PM -0800, Moritz Fischer wrote:
> On Mon, Jan 18, 2021 at 08:20:57AM +0530, Nava kishore Manne wrote:
> > This commit adds secure flags to the framework to support
> > secure BitStream Loading.
> >
> > Signed
On Mon, Mar 01, 2021 at 04:25:37PM -0800, Lizhi Hou wrote:
> Hi Tom，
>
>
> On 02/28/2021 08:54 AM, Tom Rix wrote:
> > CAUTION: This message has originated from an External Source. Please use
> > proper judgment and caution when opening attachments, clicking links, or
> > responding to this emai
Hi Greg,
On Sat, Feb 27, 2021 at 04:42:55PM +0100, Greg KH wrote:
> On Sat, Feb 27, 2021 at 11:27:03PM +0800, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces.
> >
> > The driver now only binds th
On Fri, Feb 26, 2021 at 07:01:05AM -0800, Tom Rix wrote:
> A question i do not know the answer to.
>
> Seems like 'golden' is linked to a manufacturing (diagnostics?) image.
>From my brief history with Xilinx Ultrascale+ PCI cards I recall the golden
image being a sort of known good recovery imag
On Mon, Feb 22, 2021 at 07:05:29AM -0800, Tom Rix wrote:
>
> On 2/17/21 10:40 PM, Lizhi Hou wrote:
> > xrt-lib kernel module infrastructure code to register and manage all
> > leaf driver modules.
> >
> > Signed-off-by: Sonal Santan
> > Signed-off-by: Max Zhen
> > Signed-off-by: Lizhi Hou
> > -
Lizhi,
On Wed, Feb 17, 2021 at 10:40:01PM -0800, Lizhi Hou wrote:
> Hello,
>
> This is V3 of patch series which adds management physical function driver for
> Xilinx
> Alveo PCIe accelerator cards,
> https://www.xilinx.com/products/boards-and-kits/alveo.html
> This driver is part of Xilinx Runt
Lizhi,
On Wed, Feb 17, 2021 at 10:40:05PM -0800, Lizhi Hou wrote:
> xrt-lib kernel module infrastructure code to register and manage all
> leaf driver modules.
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/lib/main.c | 274 ++
On Wed, Feb 17, 2021 at 10:40:18PM -0800, Lizhi Hou wrote:
> Add partition isolation platform driver. partition isolation is
> a hardware function discovered by walking firmware metadata.
> A platform device node will be created for it. Partition isolation
> function isolate the different fpga regi
On Wed, Feb 17, 2021 at 10:40:13PM -0800, Lizhi Hou wrote:
> Add ICAP driver. ICAP is a hardware function discovered by walking
> firmware metadata. A platform device node will be created for it.
> FPGA bitstream is written to hardware through ICAP.
>
> Signed-off-by: Sonal Santan
> Signed-off-by
Lizhi,
On Wed, Feb 17, 2021 at 10:40:17PM -0800, Lizhi Hou wrote:
> Add DDR calibration driver. DDR calibration is a hardware function
> discovered by walking firmware metadata. A platform device node will
> be created for it. Hardware provides DDR calibration status through
> this function.
>
>
On Sun, Feb 21, 2021 at 06:57:31AM -0800, Tom Rix wrote:
> As I am looking through the files, I have this comment.
>
> fpga/ is currently a single directory, while files could be organized in
> subdirectories like
>
> dfl/pci.c
>
> instead have the possible subdir name as a prefix to the filena
On Sun, Feb 21, 2021 at 09:12:37AM -0800, Tom Rix wrote:
>
> On 2/17/21 10:40 PM, Lizhi Hou wrote:
> > Alveo FPGA firmware and partial reconfigure file are in xclbin format.
> This code enumerates and extracts
> > Add
> > code to enumerate and extract sections from xclbin files. xclbin.h is cross
Hi Russ,
On Tue, Feb 16, 2021 at 09:46:53AM -0800, Russ Weight wrote:
> I believe all of the dependencies have been accepted now.
>
> - Russ
Sorry for dropping the ball on this, I'll get to this ASAP after -rc1 is
tagged.
>
> On 2/15/21 6:56 AM, Tom Rix wrote:
> > Russ, Moritz
> >
> > This pat
On Wed, Feb 10, 2021 at 12:15:35PM +0200, Alexandru Ardelean wrote:
> From: Mircea Caprioru
>
> This patch adds support for vco maximum and minimum ranges in accordance
VCO
> with fpga speed grade, voltage, device package, technology and family. This
FPGA
> new information is extracted from two n
the code that uses them.
>
> The register definitions are described at this link:
> https://wiki.analog.com/resources/fpga/docs/hdl/regmap
> (the 'Base (common to all cores)' section).
>
> Acked-by: Moritz Fischer
This patchset is very different from the reviewed one earlier
Russ,
On Fri, Feb 05, 2021 at 10:25:21AM -0800, Russ Weight wrote:
> Port enable is not complete until ACK = 0. Change
> __afu_port_enable() to guarantee that the enable process
> is complete by polling for ACK == 0.
>
> Reviewed-by: Tom Rix
> Reviewed-by: Matthew Gerlach
> Signed-off-by: Russ
On Thu, Feb 04, 2021 at 01:13:13PM +0100, Luca Ceresoli wrote:
> The current code produces an error message on devm_gpiod_get() errors even
> when the error is -EPROBE_DEFER, which should be silent.
>
> This has been observed producing a significant amount of messages like:
>
> xlnx-slave-spi
On Thu, Feb 04, 2021 at 02:36:11PM +0100, Michal Simek wrote:
> Use already prepared dev_err_probe() introduced by commit a787e5400a1c
> ("driver core: add device probe log helper").
> It simplifies EPROBE_DEFER handling.
>
> Signed-off-by: Michal Simek
> ---
>
> drivers/fpga/xilinx-pr-decouple
On Mon, Feb 01, 2021 at 09:21:58AM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add authenticate-fpga-config property for FPGA bitstream authentication,
> which makes sure a signed bitstream has valid signatures.
>
> Signed-off-by: Richard Gong
> ---
> v4: explain authent
> limits and apply them.
>
> Signed-off-by: Dragos Bogdan
> Signed-off-by: Mathias Tausen
> Signed-off-by: Alexandru Ardelean
Acked-by: Moritz Fischer
> ---
> drivers/clk/clk-axi-clkgen.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/d
t; And adds dependencies on the mechanisms required by the driver to work (OF
> and HAS_IOMEM).
>
> Signed-off-by: Dragos Bogdan
> Signed-off-by: Alexandru Ardelean
Reviewed-by: Moritz Fischer
> ---
> drivers/clk/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 del
Hi Catalin,
On Wed, Jan 27, 2021 at 01:09:36PM +, Catalin Marinas wrote:
> On Thu, 21 Jan 2021 17:24:19 -0800, Moritz Fischer wrote:
> > Address issue observed on real world system with suboptimal IORT table
> > where DMA masks of PCI devices would get set
On Wed, Jan 27, 2021 at 10:16:32AM +0100, Michal Simek wrote:
> Hi
>
> On 1/27/21 9:57 AM, Nava kishore Manne wrote:
> > Hi Moritz,
> >
> > Please find my response inline.
> >
> >> -----Original Message-
> >> From: Moritz Fischer
On Wed, Jan 27, 2021 at 07:05:41AM -0600, Richard Gong wrote:
>
> Hi Greg,
>
> Thanks for review!
>
> On 1/27/21 6:04 AM, Greg KH wrote:
> > On Mon, Jan 25, 2021 at 02:56:23PM -0600, richard.g...@linux.intel.com
> > wrote:
> > > From: Richard Gong
> > >
> > > Add COMMAND_AUTHENTICATE_BITSTREA
Hi Richard,
On Mon, Jan 25, 2021 at 02:56:24PM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Extend Intel service layer driver to get the firmware version running at
> FPGA device. Therefore FPGA manager driver, one of Intel service layer
> driver's client, can decide wheth
On Mon, Jan 25, 2021 at 02:56:25PM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add FPGA_MGR_BITSTREM_AUTHENTICATION flag for FPGA bitstream
> authentication, which makes sure a signed bitstream has valid signatures.
>
> Except for the actual configuration of the device, t
Alexandru,
On Tue, Jan 26, 2021 at 01:08:24PM +0200, Alexandru Ardelean wrote:
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86
On Mon, Jan 25, 2021 at 02:56:26PM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add authenticate-fpga-config property to support FPGA bitstream
> authentication, which makes sure a signed bitstream has valid signatures.
>
> Signed-off-by: Richard Gong
> ---
> v3: no chang
On Mon, Jan 25, 2021 at 02:56:28PM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Extend FPGA manager driver to support FPGA bitstream authentication on
> Intel SocFPGA platforms.
>
> Signed-off-by: Richard Gong
> ---
> v3: add handle to retriev the firmware version to keep
On Mon, Jan 25, 2021 at 02:56:27PM -0600, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Add authenticate-fpga-config property for FPGA bitstream authentication,
> which makes sure a signed bitstream has valid signatures.
>
> Signed-off-by: Richard Gong
> ---
> v3: no change
> v2:
On Tue, Jan 26, 2021 at 10:40:05AM +0800, Xu Yilun wrote:
> On Mon, Jan 25, 2021 at 06:22:55PM -0800, Moritz Fischer wrote:
> > On Mon, Jan 25, 2021 at 11:00:38AM -0800, Tom Rix wrote:
> > >
> > > On 1/25/21 12:49 AM, Xu Yilun wrote:
> > > > This patch
On Mon, Jan 25, 2021 at 11:00:38AM -0800, Tom Rix wrote:
>
> On 1/25/21 12:49 AM, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces.
> >
> > The driver now only binds the ether group feature, which
TH_LOG("ioctl() failed to get the number irqs");
> + }
> + ASSERT_LT(irq_num, 256) {
> + TH_LOG("unexpeced number of irqs");
> + }
> + close(devfd);
> +}
> +
> +TEST_HARNESS_MAIN
> --
> 2.27.0
>
Looks good to me, from FPGA perspective, needs Acked-by from Shua, though.
Also, this does not apply to linux-next, or for-5.12 or char-misc-next,
so I'm confused :)
Once that's sorted, feel free to add
Acked-by: Moritz Fischer
- Moritz
On Mon, Jan 18, 2021 at 08:13:16AM +0530, Nava kishore Manne wrote:
> This patch adds load pdi api support to enable pdi/partial loading from
> linux. Programmable Device Image (PDI) is combination of headers, images
> and bitstream files to be loaded. Partial PDI is partial set of image/
> images
Hi Nava,
On Fri, Jan 22, 2021 at 10:34:15AM +, Nava kishore Manne wrote:
> Hi Moritz,
>
> Thanks for the review.
> Please find my response inline.
>
> > -Original Message-----
> > From: Moritz Fischer
> > Sent: Tuesday, January 19, 2021 6:03 AM
&
On Fri, Jan 22, 2021 at 11:29:28AM -0800, t...@redhat.com wrote:
> From: Tom Rix
>
> Every FPGA has several subdevices in other subsystems.
> The new FPGA subdevices section is necessary to ensure changes to
> the subdevices files get reviewed within the context of the FPGA
> subsystem.
>
> Sign
On Fri, Jan 22, 2021 at 07:17:59PM +, Robin Murphy wrote:
> On 2021-01-22 17:50, Moritz Fischer wrote:
> > Hi Robin,
> >
> > On Fri, Jan 22, 2021 at 02:42:05PM +, Robin Murphy wrote:
> > > On 2021-01-22 01:24, Moritz Fischer wrote:
> > > > Addres
Hi Robin,
On Fri, Jan 22, 2021 at 02:42:05PM +, Robin Murphy wrote:
> On 2021-01-22 01:24, Moritz Fischer wrote:
> > Address issue observed on real world system with suboptimal IORT table
> > where DMA masks of PCI devices would get set to 0 as result.
> >
> > i
On Mon, Jan 18, 2021 at 08:20:57AM +0530, Nava kishore Manne wrote:
> This commit adds secure flags to the framework to support
> secure BitStream Loading.
>
> Signed-off-by: Nava kishore Manne
> ---
> drivers/fpga/of-fpga-region.c | 10 ++
> include/linux/fpga/fpga-mgr.h | 12 ++
On Tue, Jan 19, 2021 at 06:34:54AM +, Nava kishore Manne wrote:
> Hi Moritz,
>
> Thanks for the review.
> Please find my response inline.
>
> > -Original Message-----
> > From: Moritz Fischer
> > Sent: Saturday, January 16, 2021 8:28 AM
>
rlier.
Ideally we want to use the minimum mask of what the IORT contains for
the root complex and what the device was configured with.
Fixes: 5ac65e8c8941 ("ACPI/IORT: Support address size limit for root complexes")
Signed-off-by: Moritz Fischer
---
Changes from v1:
- Changed warning to FW
Robin,
On Thu, Jan 21, 2021 at 11:15:05PM +, Robin Murphy wrote:
> On 2021-01-21 21:17, Moritz Fischer wrote:
> > Robin,
> >
> > On Thu, Jan 21, 2021 at 08:08:42PM +, Robin Murphy wrote:
> > > On 2021-01-21 19:16, Moritz Fischer wrote:
> > > > A
Robin,
On Thu, Jan 21, 2021 at 08:08:42PM +, Robin Murphy wrote:
> On 2021-01-21 19:16, Moritz Fischer wrote:
> > Address issue observed on real world system with suboptimal IORT table
> > where DMA masks of PCI devices would get set to 0 as result.
> >
> > iort_
Hi Tom,
On Thu, Jan 21, 2021 at 06:30:20AM -0800, Tom Rix wrote:
>
> On 1/17/21 8:22 AM, Moritz Fischer wrote:
> > Greg,
> >
> > On Sun, Jan 17, 2021 at 04:45:04PM +0100, Greg KH wrote:
> >> On Wed, Jan 13, 2021 at 09:54:07AM +0800, Xu Yilun wrote:
> >&g
nt to use the minimum mask of what the IORT contains for
the root complex and what the device was configured with, but never 0.
Fixes: 5ac65e8c8941 ("ACPI/IORT: Support address size limit for root complexes")
Signed-off-by: Moritz Fischer
---
Hi all,
not sure I'm doing this ri
Hi Nava,
On Mon, Jan 18, 2021 at 08:13:18AM +0530, Nava kishore Manne wrote:
> This patch adds driver for versal fpga manager.
Nit: Add support for Xilinx Versal FPGA manager
>
> PDI source type can be DDR, OCM, QSPI flash etc..
No idea what PDI is :)
> But driver allocates memory always from DDR
Greg,
On Sun, Jan 17, 2021 at 04:45:04PM +0100, Greg KH wrote:
> On Wed, Jan 13, 2021 at 09:54:07AM +0800, Xu Yilun wrote:
> > This patch supports the DFL drivers be written in userspace. This is
> > realized by exposing the userspace I/O device interfaces.
> >
> > The driver leverages the uio_pd
Hi Xu,
On Wed, Jan 13, 2021 at 09:54:08AM +0800, Xu Yilun wrote:
> This patch adds description for UIO support for dfl devices on DFL
> bus.
>
> Signed-off-by: Xu Yilun
> ---
> v2: no doc in v1, add it for v2.
> v3: some documentation fixes.
> v4: documentation change since the driver matching i
Hi Xu,
On Wed, Jan 13, 2021 at 09:54:07AM +0800, Xu Yilun wrote:
> This patch supports the DFL drivers be written in userspace. This is
> realized by exposing the userspace I/O device interfaces.
>
> The driver leverages the uio_pdrv_genirq, it adds the uio_pdrv_genirq
> platform device with the
Hi Tom,
On Sat, Jan 16, 2021 at 11:33:21AM -0800, t...@redhat.com wrote:
> From: Tom Rix
>
> Check that the ioctl DFL_FPGA_PORT_ERR_GET_IRQ_NUM returns
> an expected result.
>
> Tested on vf device 0xbcc1
>
> Sample run with
> # make -C tools/testing/selftests TARGETS=drivers/fpga run_tests
>
Hi,
On Fri, Jan 15, 2021 at 07:04:31AM +0530, Nava kishore Manne wrote:
> This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI
> shutdown manager IP. It can be used to safely handling the AXI traffic
> on a Reconfigurable Partition when it is undergoing dynamic reconfiguration
> a
On Mon, Jan 11, 2021 at 02:39:36PM -0800, Tom Rix wrote:
>
> On 1/11/21 12:28 PM, Moritz Fischer wrote:
> > Tom,
> >
> > On Mon, Jan 11, 2021 at 11:46:03AM -0800, Tom Rix wrote:
> >
> > [..]
> >> I have been doing the first review in a couple o
Hi Greg,
On Mon, Jan 11, 2021 at 07:14:22PM +0100, Greg Kroah-Hartman wrote:
> On Mon, Jan 11, 2021 at 05:34:57PM +0100, Lukas Bulwahn wrote:
> > On Mon, Jan 11, 2021 at 4:52 PM Greg Kroah-Hartman
> > wrote:
> > >
> > > On Mon, Jan 11, 2021 at 12:21:13PM +0100, Lukas Bulwahn wrote:
> > > > Commit
Hi Xu,
On Tue, Jan 12, 2021 at 08:16:15AM +0800, Xu Yilun wrote:
> On Mon, Jan 11, 2021 at 06:59:10AM -0800, Tom Rix wrote:
> >
> > On 1/10/21 10:16 PM, Xu Yilun wrote:
> > > On Sun, Jan 10, 2021 at 12:11:17PM -0800, Moritz Fischer wrote:
> > >> On Sat, Jan 02
Tom,
On Mon, Jan 11, 2021 at 11:46:03AM -0800, Tom Rix wrote:
[..]
> I have been doing the first review in a couple of days after every patch
> landing.
I appreciate your help with doing reviews.
> I see some pretty good response from the developers to fix the issues raised.
... yet patches
ends without a blank line; unexpected unindent.
>
> Rectify ReST formatting in ./Documentation/fpga/dfl.rst.
>
> Signed-off-by: Lukas Bulwahn
Acked-by: Moritz Fischer
> ---
> applies cleanly on next-20210111
>
> Moritz, Matthew, please ack.
>
> Greg, please pick
On Sat, Jan 02, 2021 at 11:13:01AM +0800, Xu Yilun wrote:
> This patch supports the DFL drivers be written in userspace. This is
> realized by exposing the userspace I/O device interfaces.
>
> The driver leverages the uio_pdrv_genirq, it adds the uio_pdrv_genirq
> platform device with the DFL devi
Hi Xu,
On Sat, Jan 02, 2021 at 11:13:00AM +0800, Xu Yilun wrote:
> This patchset supports some dfl device drivers written in userspace.
>
> In the patchset v1, the "driver_override" interface should be used to bind
> the DFL UIO driver to DFL devices. But there is concern that the
> "driver_overr
On Sat, Jan 09, 2021 at 02:08:53PM -0800, Tom Rix wrote:
>
> On 12/28/20 5:51 AM, Zheng Yongjun wrote:
> > spinlock can be initialized automatically with DEFINE_SPINLOCK()
> > rather than explicitly calling spin_lock_init().
> >
> > Signed-off-by: Zheng Yongjun
>
> This looks fine.
>
> Reviewed
On Sat, Jan 09, 2021 at 05:40:38PM -0800, Tom Rix wrote:
>
> On 1/9/21 2:52 PM, Rikard Falkeborn wrote:
> > On Sat, Jan 09, 2021 at 01:55:13PM -0800, Tom Rix wrote:
> >> On 1/8/21 3:54 PM, Rikard Falkeborn wrote:
> >>> The only usage of these is to put their addresses in arrays of pointers
> >>> t
Tom,
On Sun, Jan 10, 2021 at 07:46:29AM -0800, Tom Rix wrote:
>
> On 1/7/21 8:09 AM, Tom Rix wrote:
> > On 1/6/21 8:37 PM, Moritz Fischer wrote:
> >> This is a resend of the previous (unfortunately late) patchset of
> >> changes for FPGA DFL.
> > Is there so
Be more verbose to disambiguate the error case when trying to configure
SRIOV with no driver bound vs. a driver that does not implement the
SRIOV callback.
Reported-by: Brian Foley
Signed-off-by: Moritz Fischer
---
drivers/pci/iov.c | 9 -
1 file changed, 8 insertions(+), 1 deletion
From: Xu Yilun
This patch adds support for the Nios handshake private feature on Intel
PAC (Programmable Acceleration Card) N3000.
The Nios is the embedded processor on the FPGA card. This private feature
provides a handshake interface to FPGA Nios firmware, which receives
retimer configuration
header guards to match filename]
Signed-off-by: Xu Yilun
Reviewed-by: Tom Rix
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
---
MAINTAINERS | 1 +
drivers/fpga/dfl.c | 1 +
drivers/fpga/dfl.h | 72 -
include/linux/dfl.h | 86
From: Xu Yilun
This driver is for the EMIF private feature implemented under FPGA
Device Feature List (DFL) framework. It is used to expose memory
interface status information as well as memory clearing control.
The purpose of memory clearing block is to zero out all private memory
when FPGA is
in file2alias.c.
Signed-off-by: Xu Yilun
Signed-off-by: Wu Hao
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
---
scripts/mod/devicetable-offsets.c | 4
scripts/mod/file2alias.c | 13 +
2 files changed, 17
From: Matthew Gerlach
In preparation of looking for dfls based on a vendor specific pci
capability, move the code for the default method of finding the first
dfl at offset 0 of Bar 0 to its own function.
Signed-off-by: Matthew Gerlach
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
Signed-off-by: Matthew Gerlach
Signed-off-by: Russ Weight
Reviewed-by: Tom Rix
Acked-by: Wu Hao
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl.h | 13 +
include/linux/mod_devicetable.h | 24
2 files changed, 25 insertions(+), 12 deletions
From: Matthew Gerlach
A PCIe vendor specific extended capability is introduced by Intel to
specify the start of a number of DFLs.
Signed-off-by: Matthew Gerlach
Signed-off-by: Moritz Fischer
---
Documentation/fpga/dfl.rst | 27
drivers/fpga/dfl-pci.c | 87
This is a resend of the previous (unfortunately late) patchset of
changes for FPGA DFL.
This contains Matthew's changes to allow for more flexible discovery of
DFLs.
Xu's changeset adds support for DFL device drivers. Two of the first
users are part of the patchset: dfl-emif a memory controller,
-off-by: Xu Yilun
Reviewed-by: Tom Rix
Signed-off-by: Moritz Fischer
---
drivers/fpga/dfl.c | 3 +--
drivers/fpga/dfl.h | 14 +++---
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index b450870b75ed..5a6ba3b2fa05 100644
--- a
On Fri, Dec 04, 2020 at 01:17:37AM +, Max Zhen wrote:
> Hi Moritz,
>
> I manually fixed some line breaks. Not sure why outlook is not doing it
> properly.
> Let me know if it still looks bad to you.
That might just be outlook :)
>
> Please see my reply below.
>
> >
> >
> > Max,
> >
> >
Hi Alex,
On Wed, Dec 02, 2020 at 06:10:42PM +0200, Alexandru Ardelean wrote:
> On Mon, Oct 19, 2020 at 2:14 PM Alexandru Ardelean
> wrote:
> >
> > Up until now the these limits were global/hard-coded, since they are
> > typically limits of the fabric.
> >
> > However, since this is an FPGA genera
Max,
On Thu, Dec 03, 2020 at 03:38:26AM +, Max Zhen wrote:
> [...cut...]
>
> > > > > +xclbin over the User partition as part of DFX. When a user
> > > > > +requests loading of a specific xclbin the xmgmt management
> > > > > +driver reads the parent interface UUID specified in the xclbin
>
Hi Sonal,
On Wed, Dec 02, 2020 at 06:57:11PM +, Sonal Santan wrote:
> Hi Moritz,
>
> > -Original Message-
> > From: Moritz Fischer
> > Sent: Monday, November 30, 2020 8:27 PM
> > To: Sonal Santan
> > Cc: linux-kernel@vger.kernel.org; linux-f...@v
Hi Max,
On Wed, Dec 02, 2020 at 09:24:29PM +, Max Zhen wrote:
> Hi Moritz,
>
> Thanks for your feedback. Please see my reply inline.
>
> Thanks,
> -Max
>
> > -Original Message-----
> > From: Moritz Fischer
> > Sent: Monday, November 30, 2020 20
Hi Sonal,
On Sat, Nov 28, 2020 at 04:00:39PM -0800, Sonal Santan wrote:
> From: Sonal Santan
>
> Add management physical function driver core. The driver attaches
> to management physical function of Alveo devices. It instantiates
> the root driver and one or more partition drivers which in turn
Hi Richard,
On Tue, Dec 01, 2020 at 01:30:16PM -0600, Richard Gong wrote:
> > Can U-Boot determine whether it's the new or old flow? Can you set a
> > different compatible value in your device-tree, to disambiguate
> > behaviors?
> >
>
> The boot flow is determined by defconfig during compilati
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