sight device could have an alias_name entry, that
could be interrogated by a script and used as required. This avoids
breaking any existing scripts using the established naming convention.
4) Any devicetree attribute should follow the ,
naming convention. e.g. arm,some_attribute.
I agree with Alex that it may not be normal practice to add in
attributes in these circumstances - this does not appear to relate to
a specific hardware feature or limitation. You may wish to discuss
this with the device tree maintainers.
Thanks and Regards
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
: 88f11864cf1d ("coresight: etm-perf: Support PID tracing for kernel at
EL2")
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers
Adds documentation for the CoreSight System configuration manager.
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../trace/coresight/coresight-config.rst | 244 ++
Documentation/trace/coresight/coresight.rst
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight
currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 98 +
.../hwtracing/coresight/coresight-syscfg.c| 338
Loaded coresight configurations are registered in the cs_etm\events sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers
itional config and features by configfs
c) enhanced resource management for ETMv4 and checking features have sufficient
resources to be enabled.
d) ECT and CTI support for configuration and features.
Mike Leach (10):
coresight: syscfg: Initial coresight system configuration
coresight: syscfg:
configurations and features.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.h| 142 +
drivers/hwtracing/coresight/coresight-core.c | 12 +-
.../hwtracing/coresight/coresight-etm
HI Suzuki
OK - realized that this is an aarch32 kernel thing on closer
inspection of the kernel test robot info. Now have a reproducer so
can fix
Thanks
Mike
On Mon, 12 Apr 2021 at 12:29, Mike Leach wrote:
>
> HI Suzuki,
>
> On Mon, 12 Apr 2021 at 11:28, Suzuki K Poulose wrote
HI Suzuki,
On Mon, 12 Apr 2021 at 11:28, Suzuki K Poulose wrote:
>
> On 09/04/2021 11:37, Mike Leach wrote:
> > Adds in handlers to allow the ETMv4 to use the complex configuration
> > support. Features and configurations can be loaded and selected in the
> > device.
>
Adds documentation for the CoreSight System configuration manager.
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../trace/coresight/coresight-config.rst | 244 ++
Documentation/trace/coresight/coresight.rst
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight
Loaded coresight configurations are registered in the cs_etm\events sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers
currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 98 +
.../hwtracing/coresight/coresight-syscfg.c| 338
configurations and features.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.h| 142 +
drivers/hwtracing/coresight/coresight-core.c | 12 +-
.../hwtracing/coresight/coresight-etm
d checking features have sufficient
resources to be enabled.
d) ECT and CTI support for configuration and features.
Mike Leach (10):
coresight: syscfg: Initial coresight system configuration
coresight: syscfg: Add registration and feature loading for cs devices
coresight: config: Add configura
Hi Mathieu,
On Mon, 5 Apr 2021 at 21:56, Mathieu Poirier wrote:
>
> On Tue, Mar 16, 2021 at 06:03:59PM +, Mike Leach wrote:
> > Adds configfs subsystem and attributes to the configuration manager
> > to enable the listing of loaded configurations and features.
> >
&
Hi Mathieu,
On Wed, 31 Mar 2021 at 21:49, Mathieu Poirier
wrote:
>
> On Tue, Mar 16, 2021 at 06:03:54PM +, Mike Leach wrote:
> > Loaded coresight configurations are registered in the cs_etm\cs_config sub
>
> This changelog is obsolete - cs_config is no longer unde
HI Suzuki,
On Fri, 19 Mar 2021 at 10:30, Suzuki K Poulose wrote:
>
> Hi Mike
>
> > On 8 Mar 2021, at 17:26, Mike Leach wrote:
> >
> > Hi Suzuki,
> >
> > On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose
> > wrote:
> >>
> >>
Hi Suzuki,
Realised I hadn't answered the question below...
On Fri, 5 Mar 2021 at 10:18, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Adds in handlers to allow the ETMv4 to use the complex configuration
> > support. Features and configurations can
Adds documentation for the CoreSight System configuration manager.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../trace/coresight/coresight-config.rst | 244 ++
Documentation/trace/coresight/coresight.rst | 16 ++
2 files changed, 260 insertions
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Mak
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++
2 files
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 2
Loaded coresight configurations are registered in the cs_etm\cs_config sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 2
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-etm4x-cfg.c | 182
currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 98 ++
.../hwtracing/coresight/coresight-syscfg.c| 324 +-
.../hwtracing/coresight/coresight
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile
configurations and features.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.h| 142 +
drivers/hwtracing/coresight/coresight-core.c | 12 +-
.../hwtracing/coresight/coresight-etm-perf.c | 2 +-
.../hwtracing
abled.
d) ECT and CTI support for configuration and features.
Mike Leach (10):
coresight: syscfg: Initial coresight system configuration
coresight: syscfg: Add registration and feature loading for cs devices
coresight: config: Add configuration and feature generic functions
coresight: etm
amed
> as such csdev_*, rather than cscfg_*_csdev. The latter kind of implies
> "cscfg" is the "primary" object, while it is the csdev where we track
> this.
>
> Feel free to ignore.
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > API for individua
gt; (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> private interrupt (PPI) on address translation errors and when the buffer
> is full. Overall implementation here is inspired from the Arm SPE driver.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Cc: Suzu
bindings for Embedded Trace Extensions.
> > ETE can be connected to legacy coresight components and thus
> > could optionally contain a connection graph as described by
> > the CoreSight bindings.
> >
> > Cc: devicet...@vger.kernel.org
> > Cc: Mathieu Poirier
> &g
rce, not the FEAT_ETE type, which is fine as we
then check the cpu and if it has TRBE.
So the simplifications to the code from the first couple of patch sets
make this explanation slightly misleading. Could do to adjust if
re-spinning set.
Reviewed-by: Mike Leach
> This defines a perc
r and matches the same subtype. Please note
> that at anytime there can be only one ETM tracing the event.
>
> Adding support for different types of sinks for a single
> event is complex and is not something that we expect
> on a sane configuration.
>
> Cc: Mathieu Poirier
On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote:
>
> If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF),
> move the ETM to trace prohibited region using TRFCR, while disabling.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Cc: Anshuman Khandual
> Signed-
Hi Suzuki,
On Thu, 4 Mar 2021 at 16:49, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Configurations are first activated, then when any coresight device is
> > enabled, the active configurations are checked and any matching
> > one is enabled.
>
Hi
On Thu, 4 Mar 2021 at 14:25, Suzuki K Poulose wrote:
>
> On 3/4/21 2:19 PM, Mike Leach wrote:
> > Hi Suzuki,
> >
> > On Thu, 4 Mar 2021 at 12:13, Suzuki K Poulose
> > wrote:
> >>
> >> On 1/28/21 5:09 PM, Mike Leach wrote:
> >>>
Hi Suzuki,
On Thu, 4 Mar 2021 at 12:13, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Loaded coresight configurations are registered in the cs_etm\cs_config sub
> > directory. This extends the etm-perf code to handle these registrations,
> > and
Hi Suzuki,
On Thu, 4 Mar 2021 at 10:08, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Creates an system management API to allow complex configurations and
> > features to be programmed into a CoreSight infrastructure.
> >
> > A feature is de
Hi Suzuki,
On Wed, 3 Mar 2021 at 10:09, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Creates an system management API to allow complex configurations and
> > features to be programmed into a CoreSight infrastructure.
> >
> > A feature is de
On Tue, 2 Mar 2021 at 16:42, Mathieu Poirier wrote:
>
> On Tue, Mar 02, 2021 at 01:24:27PM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Tue, Mar 02, 2021 at 02:23:14PM +, Mike Leach escreveu:
> > > On Tue, 2 Mar 2021 at 12:52, Arnaldo Carvalho de Melo
> > >
#x27;ll get back to this after
> processing fixes for v5.12 and what is outstanding for v5.13.
>
> - Arnaldo
I've tried [1] on both Linux-5.12-rc1 and your tmp.perf/core and it
applies cleanly on both.
Let me know if there is anything else I can try.
Thanks
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Hi Mathieu,
On Thu, 25 Feb 2021 at 21:51, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:32PM +, Mike Leach wrote:
> > Add calls to activate the selected configuration as perf starts
> > and stops the tracing session.
> >
> > Signed-off-by: Mi
HI Mathieu,
On Thu, 25 Feb 2021 at 21:20, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:31PM +, Mike Leach wrote:
> > Configurations are first activated, then when any coresight device is
> > enabled, the active configurations are checked and any matching
HI Mathieu.
On Wed, 24 Feb 2021 at 18:33, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:30PM +, Mike Leach wrote:
> > Loaded coresight configurations are registered in the cs_etm\cs_config sub
> > directory. This extends the etm-perf code to handle these registra
Hi Mathieu,
On Mon, 22 Feb 2021 at 17:38, Mathieu Poirier
wrote:
>
> Hi Mike,
>
> On Thu, Jan 28, 2021 at 05:09:28PM +, Mike Leach wrote:
> > API for individual devices to register with the syscfg management
> > system is added.
> >
> > Devices registe
sight_device {
> > struct coresight_platform_data *pdata;
> > @@ -240,6 +242,9 @@ struct coresight_device {
> > int nr_links;
> > bool has_conns_grp;
> > bool ect_enabled; /* true only if associated ect device is enabled */
> > + /* system configuration and feature lists */
> > + struct list_head feature_csdev_list;
> > + struct list_head config_csdev_list;
> > };
> >
> > /*
> > --
> > 2.17.1
> >
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Hi Mathieu,
On Thu, 18 Feb 2021 at 23:52, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:27PM +, Mike Leach wrote:
> > Creates an system management API to allow complex configurations and
> > features to be programmed into a CoreSight infrastructure.
> >
>
Hi Mathieu,
On Mon, 22 Feb 2021 at 18:50, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:27PM +, Mike Leach wrote:
> > Creates an system management API to allow complex configurations and
> > features to be programmed into a CoreSight infrastructure.
> >
>
Hi Suzuki,
On Thu, 18 Feb 2021 at 15:14, Suzuki K Poulose wrote:
>
> On 2/18/21 2:30 PM, Mike Leach wrote:
> > HI Suzuki,
> >
> > On Thu, 18 Feb 2021 at 07:50, Suzuki K Poulose
> > wrote:
> >>
> >> Hi Mike
> >>
> >> On 2/16/
HI Suzuki,
On Thu, 18 Feb 2021 at 07:50, Suzuki K Poulose wrote:
>
> Hi Mike
>
> On 2/16/21 9:00 AM, Mike Leach wrote:
> > Hi Anshuman,
> >
> > There have been plenty of detailed comments so I will restrict mine to
> > a few general issues:-
> >
>
Hi Anshuman,
On Tue, 16 Feb 2021 at 09:44, Anshuman Khandual
wrote:
>
> Hello Mike,
>
> On 2/16/21 2:30 PM, Mike Leach wrote:
> > Hi Anshuman,
> >
> > There have been plenty of detailed comments so I will restrict mine to
> > a few general issues:-
> &g
ine :
> - CORESIGHT format (indicates the Frame format)
> - RAW format (indicates the format of the source)
>
> The default value is CORESIGHT format for all the records
> (i,e == 0). Add the RAW format for the TRBE sink driver.
>
> Cc: Peter Zijlstra
> Cc: Mike Leach
&
/* record was
> truncated to fit */
> +#define PERF_AUX_FLAG_OVERWRITE0x02/* snapshot
> from overwrite mode */
> +#define PERF_AUX_FLAG_PARTIAL 0x04/* record contains
> gaps */
> +#define PERF_AUX_FLAG_COLLISION0x08/* sample
> collided with another */
> +#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace
> format type */
>
> #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
> #define PERF_FLAG_FD_OUTPUT(1UL << 1)
> --
> 2.7.4
>
Reviewed by: Mike Leach
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
level
> >> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> >> private interrupt (PPI) on address translation errors and when the buffer
> >> is full. Overall implementation here is inspired from the Arm SPE driver.
> >>
> &
On Thu, 28 Jan 2021 at 17:18, Catalin Marinas wrote:
>
> On Wed, Jan 27, 2021 at 02:25:33PM +0530, Anshuman Khandual wrote:
> > This adds TRBE related registers and corresponding feature macros.
> >
> > Cc: Mathieu Poirier
> > Cc: Mike Leach
> > Cc: Suzuki K
Hi Mathieu,
On Mon, 15 Feb 2021 at 16:56, Mathieu Poirier
wrote:
>
> On Mon, Feb 15, 2021 at 04:27:26PM +, Mike Leach wrote:
> > HI Anshuman
> >
> > On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
> > wrote:
> > >
> > > Add support for dedicat
d a sink device. But such connections are not present for certain
> percpu source and sink devices which are exclusively linked and dependent.
> Build the path directly and skip connection scanning for such devices.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Cc: Suzuki K Poulos
the event is active and tracing,
> also provides us with access to the critical information
> needed to wind up a session even in the absence of an active
> output_handle.
>
> This is not an issue for the legacy sinks as none of them supports
> an IRQ and is centrally handled by the
Reviewed-by: Mike Leach
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
wrote:
>
> From: Suzuki K Poulose
>
> Add support for handling the system registers for Embedded Trace
> Extensions (ETE). ETE shares most of the registers with ETMv4 except
> for some and also adds some
Reviewed-by: Mike Leach
On Mon, 15 Feb 2021 at 13:21, Mike Leach wrote:
>
> HI,
>
> On Tue, 2 Feb 2021 at 18:56, Mathieu Poirier
> wrote:
> >
> > On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
> > > From: Suzuki K Poulose
> > >
t for handling the
> PE OS lock
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 50
> ++
> drivers/hwtracing/coresigh
med following the
> > existing convention as ete.
> >
> > ETE mandates that the trace resource status register is programmed
> > before the tracing is turned on. For the moment simply write to
> > it indicating TraceActive.
> >
> > Cc: Mathieu Poirier
&g
Reviewed-by: Mike Leach
On Sat, 13 Feb 2021 at 11:28, Sai Prakash Ranjan
wrote:
>
> Add ETM PID for Cortex-A78 to the list of supported ETMs.
>
> Signed-off-by: Sai Prakash Ranjan
> ---
>
> Changes in v2:
> * Rebased on top of coresight/next from kernel.org coresight
b802, uci_id_etm4),/* Qualcomm Kryo 385
> Cortex-A55 */
>
> base-commit: 1efbcec2ef8c037f1e801c76e4b9434ee2400be7
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Hi Suzuki,
On Fri, 12 Feb 2021 at 15:36, Suzuki K Poulose wrote:
>
> Hi Mike
>
> On 2/12/21 10:34 AM, Mike Leach wrote:
> > Hi Mathieu, Suzuki,
> >
> > Sorry for the really late response on this patch, but I noticed a
> > problem while doing a revie
n Zhou
>
> v8.4 tracing extensions added support for trace filtering controlled
> by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and
> EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2
> tracing if we are running the kernel at EL2.
>
> Cc: Catali
I think Suzuki may be on holiday for two weeks. But this does appear
to pick up both mine and his suggestions.
Suzuki gave his conditional reviewed by in the last patch.
Reviewed-by: Mike Leach
On Mon, 8 Feb 2021 at 20:50, Mathieu Poirier wrote:
>
> On Sat, Feb 06, 2021 at 11:08:33PM
t;
> >"contextid2": Only usable when the kernel is running at EL2. When
> > selected, enables PID tracing on EL2 kernel.
> >
> >"contextid": Will be an alias for the option that enables PID
> > tracing. I.e,
>
ed any configs
> from "contextid", "contextid1" or "contextid2"; otherwise, it
> dynamically sets config based on PMU format "contextid".
>
> Cc: Mike Leach
> Cc: Mathieu Poirier
> Cc: Al Grant
> Co-developed-by: Leo Yan
> Signed-off-b
gt; evsel__set_sample_bit(cs_etm_evsel, CPU);
>
> err = cs_etm_set_option(itr, cs_etm_evsel,
> - ETM_OPT_CTXTID | ETM_OPT_TS);
> + ETM_SET_OPT_CTXTID | ETM_SET_OPT_TS);
> if (err)
> goto out;
> }
> --
> 2.25.1
>
Reivewed-by: Mike Leach
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Hi Suzuki,.
On Tue, 2 Feb 2021 at 22:42, Suzuki K Poulose wrote:
>
> On 2/2/21 4:33 PM, Mike Leach wrote:
> > Hi,
> >
> > On Tue, 2 Feb 2021 at 09:42, Suzuki K Poulose
> > wrote:
> >>
> >> On 2/1/21 11:17 PM, Mathieu Poirier wrote:
> >>
Hi,
On Thu, 4 Feb 2021 at 11:08, Suzuki K Poulose wrote:
>
> On 2/4/21 4:09 AM, Leo Yan wrote:
> > Hi Mike,
> >
> > On Wed, Feb 03, 2021 at 05:39:54PM +, Mike Leach wrote:
> >
> > [...]
> >
> >>> +2.2) Tracing PID
> >>> +
guest, the two configs "contextid1" and "contextid2"
> +can be set at the same time:
> +
> + perf record -e cs_etm/contextid1,contextid2/u -- uname
> +
>
Regards
Mike
> Generating coverage files for Feedback Directed Optimization: AutoFDO
> -
> --
> 2.25.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
,
For version 1, the reader will read the number of parameters in the
per CPU block. This allows the reader to process older or newer files
that may have different numbers of parameters than in use at the
time perf was built.
Signed-off-by: Mike Leach
Reviewed-by: Leo Yan
Tested-by: Leo Yan
, Mathieu Poirier wrote:
> > Good morning,
> >
> > On Wed, Jan 27, 2021 at 05:53:50PM +, Mike Leach wrote:
> > > The current fixed metadata version format (version 0), means that adding
> > > metadata parameter items renders files from a previous version of perf
&
ected sink - we need to eliminate any
source that cannot reach it.
If not we need to find the relevant default sink for the source, which
might be a shared ETR, or per CPU TRBE / ETR, and the abstraction
logic ought to handle getting the captured data to the correct place.
If it doesn't then we are
component doesn't have any explicit connections (e.g,
> ETE) we could simply ignore the graph parsing.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> drivers/hwtracing/coresight/coresig
additional config and features by configfs
c) enhanced resource management for ETMv4 and checking features have sufficient
resources to be enabled.
d) ECT and CTI support for configuration and features.
Mike Leach (10):
coresight: syscfg: Initial coresight system configuration
coresight: syscfg: Add
currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 98 +
.../hwtracing/coresight/coresight-syscfg.c| 348 ++
.../hwtracing/coresight/coresight
Loaded coresight configurations are registered in the cs_etm\cs_config sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 5
Adds documentation for the CoreSight System configuration manager.
Signed-off-by: Mike Leach
---
.../trace/coresight/coresight-config.rst | 244 ++
Documentation/trace/coresight/coresight.rst | 16 ++
2 files changed, 260 insertions(+)
create mode 100644 Documentation
generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Mak
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 2
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++
2 files changed, 15 insertions(+), 1
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-etm4x-cfg.c | 184
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile
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