* assume ELK doesn't need this.
Yeah, ELK = Eagle Lake, CTG = Cantiga. Both are old gen5 platforms IIRC.
Matt
>
> Lucas De Marchi
>
> >
> > BR,
> > Jani.
> >
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
/* gen11 */
> >>INTEL_ICELAKE,
> >>INTEL_ELKHARTLAKE,
> >> + INTEL_JASPERLAKE,
> >>/* gen12 */
> >> INTEL_TIGERLAKE,
> >>INTEL_ROCKETLAKE,
> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> >> index 7eeecb07c9a1..1b5e09cfa11e 100644
> >> --- a/include/drm/i915_pciids.h
> >> +++ b/include/drm/i915_pciids.h
> >> @@ -579,15 +579,18 @@
> >>INTEL_VGA_DEVICE(0x8A51, info), \
> >>INTEL_VGA_DEVICE(0x8A5D, info)
> >>
> >> -/* EHL/JSL */
> >> +/* EHL */
> >> #define INTEL_EHL_IDS(info) \
> >>INTEL_VGA_DEVICE(0x4500, info), \
> >>INTEL_VGA_DEVICE(0x4571, info), \
> >>INTEL_VGA_DEVICE(0x4551, info), \
> >>INTEL_VGA_DEVICE(0x4541, info), \
> >> - INTEL_VGA_DEVICE(0x4E71, info), \
> >>INTEL_VGA_DEVICE(0x4557, info), \
> >> - INTEL_VGA_DEVICE(0x4555, info), \
> >> + INTEL_VGA_DEVICE(0x4555, info)
> >> +
> >> +/* JSL */
> >> +#define INTEL_JSL_IDS(info) \
> >> + INTEL_VGA_DEVICE(0x4E71, info), \
> >>INTEL_VGA_DEVICE(0x4E61, info), \
> >>INTEL_VGA_DEVICE(0x4E57, info), \
> >>INTEL_VGA_DEVICE(0x4E55, info), \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
mplement new combo phy
> initialization step")
> Link: https://github.com/ClangBuiltLinux/linux/issues/1094
> Signed-off-by: Nathan Chancellor
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
> 1 file changed, 2 insertions(+),
hey really need guest -> guest exports or
> > guest -> dom0 exports.
> >
> >> Overall I like the idea, but too lazy to review.
> >
> > Cool. General comments on the idea was all I was looking for for the
> > moment. Spare yor review cycles for the next version ;)
> >
> >> Oh, some kselftests for this stuff would be lovely.
> >
> > I'll look into it.
> >
> > thanks,
> > Gerd
> >
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
uthor: Linus Torvalds
> > Date: Sun Dec 3 11:01:47 2017 -0500
> >
> > Linux 4.15-rc2
> >
> > https://github.com/downor/linux_hyper_dmabuf.git hyper_dmabuf_integration_v3
> >
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
On Mon, Jul 31, 2017 at 10:36:05AM +0200, Jean Delvare wrote:
> Hi Matt, Mauro,
>
> On Thu, 17 Mar 2016 15:18:20 +0100, Jean Delvare wrote:
> > On Tue, 8 Mar 2016 10:32:37 -0800, Matt Roper wrote:
> > > A couple of the EDAC drivers have a nice memdev_dmi_entry structur
/i915:
> > Add two-stage ILK-style watermark programming (v11)
>
>
> Nothing from the graphics developers? Come on, here is someone who
> found a specific patch that causes a problem, and no one responds?
>
> Why isn't this fixed by reverting the above mentioned patch
t;
> > Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
> > Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
> > Signed-off-by: Lyude
> > [omitting CC for stable, since this patch will need to be
On Wed, Aug 03, 2016 at 02:14:53PM -0700, Matt Roper wrote:
...
>
> I imagine we'll eventually probably want to create a new display vfunc
> to handle platform-specific pipe-level stuff that needs to happen under
> vblank evasion (like the scalers and linetime WM we have today) t
On Tue, Aug 02, 2016 at 02:20:33PM -0700, Matt Roper wrote:
> On Tue, Aug 02, 2016 at 02:52:51PM -0400, Lyude wrote:
> > Thanks to Ville for suggesting this as a potential solution to pipe
> > underruns on Skylake.
> >
> > On Skylake all of the registers for config
er branch of an
if/else needs braces, you need to put them on both branches).
> + if (result == 1)
As I mentioned before, the 1=off looks confusing if someone isn't
looking at the bspec carefully. Using a #define for the various 0x1's
in this patch might help clarify the cod
;)
> Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
> Signed-off-by: Lyude
> [omitting CC for stable, since this patch will need to be changed for
> such backports first]
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
> Cc: Hans
le, since this patch will need to be changed for
> such backports first]
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
> Cc: Hans de Goede
> Cc: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_di
nce v2:
> - Write PIPE_WM_LINETIME during vblank evasion
>
> Changes since v3:
> - Rebase against new SAGV patch changes
>
> Changes since v4:
> - Add a parameter to choose what skl_wm_values struct to use when
>writing new plane watermarks
>
> Fixes: 2d41c0b59
eady added to the state if we have a change in
active pipes. I think what you meant to write was "...we'll need to
modify the watermarks on all active *planes*. Since those *planes*
won't..."
Aside from the commit message, I believe the logic is correct, so you
can consid
pipe enabled
> - Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
>enabled
> - Call skl_sagv_enable/disable() from pre/post-plane updates
> Changes since v3:
> - Use time_before() to compare timeout to jiffies
> Changes since v2:
> - Really appl
like
> > we've got enough workarounds to make this tolerable. I've shown this to
> > matt roper, but I should probably post what I've been trying to do for
> > you as well.
> >
> > So the approach I came up with is here
> >
> > https://github.com/ly
On Fri, Jul 29, 2016 at 12:39:05PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 28, 2016 at 05:03:52PM -0700, Matt Roper wrote:
> > This is completely untested (and probably horribly broken/buggy), but
> > here's a quick mockup of the general approach I was thinking for
> >
l: Update plane watermarks atomically during plane updates
> drm/i915/skl: Always wait for pipes to update after a flush
>
> Matt Roper (1):
> drm/i915/gen9: Only copy WM results for changed pipes to skl_hw
>
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu
since v2:
> - Write PIPE_WM_LINETIME during vblank evasion
>
> Changes since v3:
> - Rebase against new SAGV patch changes
>
> Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
> Signed-off-by: Lyude
> Cc: sta...@vger.kernel.org
> Cc: Ville Syrjäl
very time we have to update the watermark values because the cursor was
> moving between screens will introduce a rather noticable lag for users.
>
> Signed-off-by: Lyude
> Cc: sta...@vger.kernel.org
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
>
since v2:
> - Really apply minor style nitpicks to patch this time
> Changes since v1:
> - Added comments about this probably being one of the requirements to
>fixing Skylake's watermark issues
> - Minor style nitpicks from Matt Roper
> - Disable these functions on Broxton, s
> Changes since v1:
> - Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
>then just Skylake
> - Update description to make it clear this patch doesn't fix everything
> - Check if pipes were actually changed before writing watermarks
>
> Fixes: 2d
very time we have to update the watermark values because the cursor was
> moving between screens will introduce a rather noticable lag for users.
>
> Signed-off-by: Lyude
> Cc: sta...@vger.kernel.org
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
>
i.h header. (Jean)
Cc: Mauro Carvalho Chehab
Cc: Jean Delvare
Cc: linux-e...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Matt Roper
---
drivers/edac/ghes_edac.c | 28 +--
drivers/edac/i7core_edac.c | 47 +++--
soon as well.
Cc: Mauro Carvalho Chehab
Cc: Jean Delvare
Cc: linux-e...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Matt Roper
---
drivers/edac/ghes_edac.c | 26 --
drivers/edac/i7core_edac.c | 25 -
include/linux/dmi.h
> [] async_run_entry_fn+0x4a/0x140
> > > > [] process_one_work+0x1fd/0x670
> > > > [] ? process_one_work+0x16c/0x670
> > > > [] worker_thread+0x4e/0x450
> > > > [] ? process_one_work+0x670/0x670
> > > > [] kthread+0x101/0x120
&
_irq_handler [i915]]
> *ERROR* CPU pipe A FIFO underrun
>
> Always setting the panes to enabled fixes this error.
>
> Helped-by: Matt Roper
> Signed-off-by: Thomas Gummerer
Seems like a reasonable short-term workaround and returns us to how the
code used to behaves.
Reviewed-b
gt;primary->state->fb->bits_per_pixel / 8;
else
- p->pri.bytes_per_pixel = 0;
+ p->pri.bytes_per_pixel = 4;
p->cur.bytes_per_pixel = 4;
/*
Matt
--
Matt Roper
Graphics Software Engineer
IoTG
= intel_crtc->cursor_width;
> >>intel_crtc->cursor_width = state->base.crtc_w;
> >>intel_crtc->cursor_height = state->base.crtc_h;
> >>
> >> - if (intel_crtc->active)
> >> + if (intel_crtc->active) {
> >> + i
Bug 93711 <https://bugzilla.kernel.org/show_bug.cgi?id=93711>
>
> Is this a problem with drm-intel-nightly? In particular see
>
> commit afd65eb4cc0578a9c07d621acdb8a570e2782bf7
> Author: Matt Roper
> Date: Tue Feb 3 13:10:04 2015 -0800
>
> drm/i915: Ensure plane->state->fb stays i
g for me).
This won't solve the case if userspace uses a different framebuffer for
each update (while trying to update faster than the refresh rate). Is
there any existing userspace that behaves this way that we can test
with?
Matt
--
Matt Roper
Graphics Software Engineer
IoTG Platform E
__
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--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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