[irqchip: irq/irqchip-next] irqchip/mips-cpu: Set IPI domain parent chip

The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: 599b3063adf4bf041a87a69244ee36aded0d878f Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/599b3063adf4bf041a87a69244ee36aded0d878f Author:Mathias Kresin

[PATCH] phy: lantiq: rcu-usb2: wait after clock enable

ing. There isn't any documentation how much time is required, the value was chosen based on tests. Cc: # v5.7+ Signed-off-by: Mathias Kresin --- drivers/phy/lantiq/phy-lantiq-rcu-usb2.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/phy/lantiq/phy-lantiq-rcu-usb

[PATCH] irqchip: mips-cpu: set IPI domain parent chip

but the parent domain has no chip set. Hence the boot ends in a kernel panic. Set the chip for the parent domain as it is done in the mips gic irq driver, to have a valid irq_data chain. Fixes: 3838a547fda2 ("irqchip: mips-cpu: Introduce IPI IRQ domain support") Cc: # v5.10+ Sign

[PATCH] usb: dwc2: use a longer core rest timeout in dwc2_core_reset()

SoCs. At least till kernel 4.14 the hanging reset only caused a warning but the driver was probed successful. With kernel 4.19 errors out with EBUSY. Cc: linux-stable # 4.19+ Signed-off-by: Mathias Kresin --- drivers/usb/dwc2/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH] MIPS: ralink: Fix mt7620 nd_sd pinmux

In case the nd_sd group is set to the sd-card function, Pins 45 + 46 are configured as GPIOs. If they are blocked by the sd function, they can't be used as GPIOs. Signed-off-by: Mathias Kresin Reported-by: Kristian Evensen Fixes: f576fb6a0700 ("MIPS: ralink: cleanup the soc specific p

[PATCH] MIPS: pci-rt2880: set pci controller of_node

From: Tobias Wolf Set the PCI controller of_node such that PCI devices can be instantiated via device tree. Signed-off-by: Tobias Wolf Signed-off-by: Mathias Kresin --- arch/mips/pci/pci-rt2880.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci

[PATCH] MIPS: ralink: Add rt3352 SPI_CS1 pinmux

The rt3352 has a pin that can be used as second spi chip select, watchdog reset or GPIO. The pinmux setup was missing the definition of said pin. The pin is configured via the same bit on rt5350, so reuse the existing macro. Signed-off-by: Mathias Kresin --- arch/mips/ralink/rt305x.c | 5

[PATCH] gpio: stp-xway: Implement get callback

Add an implementation to get the current GPIO state. The callback is used by the leds-gpio driver for example, in case the current LED/GPIO state should be kept during driver load. Signed-off-by: Mathias Kresin --- drivers/gpio/gpio-stp-xway.c | 15 +++ 1 file changed, 15

Re: [PATCH] MIPS: lantiq: gphy: Drop reboot/remove reset asserts

2018-05-24 15:07 GMT+03:00 James Hogan : > On Mon, May 21, 2018 at 05:39:32PM +0100, James Hogan wrote: >> On Sun, Apr 08, 2018 at 10:30:03AM +0200, Mathias Kresin wrote: >> > While doing a global software reset, these bits are not cleared and let >> > some bootloader f

[PATCH] MIPS: lantiq: gphy: Drop reboot/remove reset asserts

cludes the GPHY resets, these resets aren't required any more. Fixes: 126534141b45 ("MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd") Cc: sta...@vger.kernel.org # 4.14+ Signed-off-by: Mathias Kresin --- drivers/soc/lantiq/gphy.c | 34 -

[PATCH 2/2] net: phy: intel-xway: add VR9 v1.1 phy ids

The phys embedded into the v1.1 of the VR9 SoC are using different phy ids. Add the phy ids to use the driver for this VR9 version as well. Signed-off-by: Mathias Kresin --- drivers/net/phy/intel-xway.c | 28 1 file changed, 28 insertions(+) diff --git a/drivers

[PATCH 1/2] net: phy: intel-xway: add VR9 version number

The VR9 phy ids are matching only for the SoC version 1.2. Rename the macros and change the names to take this into account. Signed-off-by: Mathias Kresin --- drivers/net/phy/intel-xway.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/phy/intel

Re: [PATCH 1/1 RFC] net/phy: Add Lantiq PHY driver

2016-05-23 11:49 GMT+02:00 Alexander Stein : >> The registers are set to some reset values after the chip is coming out of >> reset, but we should set them all to the same value, Mathias said that all >> except for one board he knows are using only one LED per port, but they are >> often using di

Re: [PATCH 1/1 RFC] net/phy: Add Lantiq PHY driver

2016-05-19 9:03 GMT+02:00 John Crispin : > On 19/05/2016 08:57, Alexander Stein wrote: >> Thanks for the link, I wasn't aware of that patch. I like it in general, but >> there are some things I'd like to get addressed first: >> * vr9_gphy_of_reg_init() writes uncoditionally to led3h and led3l even