.
Tested-by: Mark Langsdorf
he warning. This patch changes the order so that phys are
unregistered before the bus device is deleted.
Signed-off-by: Mark Salter
---
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On 07/09/2015 11:59 AM, Peter Zijlstra wrote:
On Thu, Jul 09, 2015 at 11:46:04AM -0500, Mark Langsdorf wrote:
I did a git bisect and it looks like the faulty patch is
d72da4a4d973d8a0a0d3c97e7cdebf287fbe3a99, "rbtree: Make lockless
searches non-fatal". I can't see why it caus
On 07/07/2015 07:56 AM, Mark Langsdorf wrote:
On 07/05/2015 03:22 PM, Linus Torvalds wrote:
It's Sunday, two weeks have passed, and the merge window is closed. I
just pushed out the tag to the git trees, and tar-balls and patches
should be mirroring out too.
I'm seeing a build reg
clude
On both versions, arch/arm64/include/generated/asm/preempt.h
exists. I'm guessing something changed in the build system so
that's its not being picked up for 4.2-rc1 but I'm not sure where
to look.
--Mark Langsdorf
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here to get people started. Additional
information can be added in later patches as needed and
as we get more experience with ACPI on ARM64.
Reviewed-by: Mark Langsdorf
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to upstream when
the new version of Parking protocol is ready.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
---
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On 01/14/2015 09:05 AM, Hanjun Guo wrote:
Using the information presented by GTDT to initialize the arch
timer (not memory-mapped).
Originally-by: Amit Daniel Kachhap
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
---
Tested-by: Mark Langsdorf
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Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Al Stone
Signed-off-by: Hanjun Guo
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Likely
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Graeme Gregory
Signed-off-by: Al Stone
Signed-off-by: Hanjun Guo
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umber directly
for the mapping.
Originally-by: Amit Daniel Kachhap
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
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.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
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only PSCI 0.2+ is supported in ACPI.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Graeme Gregory
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
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with version
less that 5.1.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
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Guo
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d, and enable it to pass
"acpi=force" if people want use ACPI on ARM64. This ensures DT be
the prefer one if ACPI table and DT both are provided at this moment.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Al Stone
Signed-off-by: Graeme Gregory
Signed-off-by: Ha
Tested-by: Yijing Wang
Signed-off-by: Graeme Gregory
Signed-off-by: Hanjun Guo
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.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Graeme Gregory
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
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CC: Leif Lindholm
CC: Ard Biesheuvel
[hj: update the change log]
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return;
-
tlb_flush_mmu_tlbonly(tlb);
tlb_flush_mmu_free(tlb);
}
This fixes the originally reported problem. I have no opinion on
moving the tlb->end check back into tlb_flush_mmu_tlbonly.
Tested-by: Mark Langsdorf
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On 01/09/2015 08:19 AM, Steve Capper wrote:
On 9 January 2015 at 12:13, Mark Rutland wrote:
On Thu, Jan 08, 2015 at 12:51:31PM +, Mark Langsdorf wrote:
I'm consistently getting an out of memory killer triggered when
compiling the kernel (make -j 16 -s) on a 16 core ARM64 system
with
On 01/08/2015 11:34 AM, Catalin Marinas wrote:
On Thu, Jan 08, 2015 at 05:29:40PM +, Mark Langsdorf wrote:
On 01/08/2015 07:45 AM, Catalin Marinas wrote:
On Thu, Jan 08, 2015 at 12:51:31PM +, Mark Langsdorf wrote:
On 01/05/2015 07:46 PM, Linus Torvalds wrote:
It's a day delayed
On 01/08/2015 07:45 AM, Catalin Marinas wrote:
On Thu, Jan 08, 2015 at 12:51:31PM +, Mark Langsdorf wrote:
On 01/05/2015 07:46 PM, Linus Torvalds wrote:
It's a day delayed - not because of any particular development issues,
but simply because I was tiling a bathroom yesterday. But r
CMA related.
I get the same failure with CMA turned off entirely. I assume that means
CMA is not the culprit.
--Mark Langsdorf
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nning a 3.18
kernel.
I'm going to start bisecting the failure now, but here's the crash
log in case someone can see something obvious in it.
--Mark Langsdorf
[ 137.440443] random: nonblocking pool is initialized
[ 1053.720094] cc1 invoked oom-killer: gfp_mask=0x200da, order=0,
oom_sco
allowable frequencies.
The core of the policy adjusting code was taken from
drivers/thermal/cpu_cooling.c.
Signed-off-by: Mark Langsdorf
---
drivers/cpufreq/highbank-cpufreq.c | 117 +
1 file changed, 117 insertions(+)
diff --git a/drivers/cpufreq/highbank
Calxeda's new ECX-2000 part uses the same cpufreq interface as highbank,
so add it to the driver's compatibility list.
This is a minor change that can safely be applied to the 3.10 and 3.11
stable trees.
Signed-off-by: Mark Langsdorf
---
drivers/cpufreq/highbank-cpufreq.c | 3 +
The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly. This patch only affects
documentation and has no functional component.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
---
Changes from v3
Added all optional properties to
On 08/14/2013 03:27 PM, Tejun Heo wrote:
> Hello,
>
> On Wed, Aug 14, 2013 at 01:23:30PM -0500, Mark Langsdorf wrote:
>> Documentation/devicetree/bindings/ata/sata_highbank.txt | 6 --
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> Any ideas on how these s
m the DTB and send the extra clock cycles.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
---
Changes from v3
Renumbered the patch series since the first two got accepted.
Changes from v2
None.
Changes from v1
Added an example to the bindings.
Forced the pre-c
The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly. This patch only affects
documentation and has no functional component.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
---
Changes from v3
Added all optional properties to
this patch.
Signed-off-by: Mark Langsdorf
---
Changes from v3
Edited the commit message to describe the hardware impact.
Renumbered the patch series since the first two got accepted.
Changes from v2
None.
Changes from v1
Clarified that the array is a u32 array
On 08/09/2013 11:10 AM, Tejun Heo wrote:
On Wed, Aug 07, 2013 at 10:52:36AM -0500, Mark Langsdorf wrote:
The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
Will wait for the
The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
---
Changes from v2
Fixed some indenting.
Changes from v1
None.
.../devicetree/bindings/ata/ahci-platform.txt
m the DTB and send the extra clock cycles.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
---
Changes from v2
None.
Changes from v1
Added an example to the bindings.
Forced the pre-clocks and post-clocks values to 0 if there is an
error while reading them or the v
, but failing to apply this patch will
not cause any stability issues on the system.
Signed-off-by: Mark Langsdorf
---
Changes from v2
Further rewords of the commit message.
Changes from v1
Expanded commit message explaining the problems with the
unpatched code.
drivers/ata
Some board designs do not drive the SATA transmit lines within the
specification. The ECME can provide override settings, on a per board
basis, to bring the transmit lines within spec. Read those settings
from the DTB and program them in.
Signed-off-by: Mark Langsdorf
---
Changes from v2
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1, v2
None.
drivers/ata/sata_highbank.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index e9a4f46..8b40025 100644
--- a
On 08/02/2013 03:01 PM, Sergei Shtylyov wrote:
> On 08/02/2013 08:28 PM, Mark Langsdorf wrote:
>
>> The Calxeda sata_highbank driver has been adding its descriptions to the
>> ahci driver. Separate them properly.
>
>> Signed-off-by: Mark Langsdorf
>> Acked-by
m the DTB and send the extra clock cycles.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
---
Changes from v1
Added an example to the bindings.
Forced the pre-clocks and post-clocks values to 0 if there is an
error while reading them or the values aren't in the DTB.
Doc
Some board designs do not drive the SATA transmit lines within the
specification. The ECME can provide override settings, on a per board
basis, to bring the transmit lines within spec. Read those settings
from the DTB and program them in.
Signed-off-by: Mark Langsdorf
---
Changes from v1
The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly.
Signed-off-by: Mark Langsdorf
Acked-by: Rob Herring
---
Changes from v1
None.
.../devicetree/bindings/ata/ahci-platform.txt | 14 ++
.../devicetree/bindings/ata
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1
None.
drivers/ata/sata_highbank.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index e9a4f46..8b40025 100644
--- a
the signals to the LED PIC in the
correct order.
Signed-off-by: Mark Langsdorf
---
Changes from v1
Expanded commit message explaining the problems with the
unpatched code.
drivers/ata/sata_highbank.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ata
On 07/30/2013 11:42 AM, Mark Rutland wrote:
> On Fri, Jul 26, 2013 at 07:38:24PM +0100, Rob Herring wrote:
>> On 07/26/2013 11:22 AM, Mark Rutland wrote:
>>> On Fri, Jul 26, 2013 at 04:11:57PM +0100, Mark Langsdorf wrote:
>>>> Some board designs do not drive the
On 07/29/2013 11:55 AM, Tejun Heo wrote:
> On Fri, Jul 26, 2013 at 10:11:54AM -0500, Mark Langsdorf wrote:
>> The ACTIVITY and ERROR signals were reversed in the original commit.
>> Fix that.
>
> And what's the implication of this change? Does this change the
> b
from the DTB and send the extra clock cycles.
Signed-off-by: Mark Langsdorf
---
Documentation/devicetree/bindings/ata/sata_highbank.txt | 4
drivers/ata/sata_highbank.c | 16 +---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --
The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly.
Signed-off-by: Mark Langsdorf
---
.../devicetree/bindings/ata/ahci-platform.txt | 14 ++
.../devicetree/bindings/ata/sata_highbank.txt | 32 ++
2
The ACTIVITY and ERROR signals were reversed in the original commit.
Fix that.
Signed-off-by: Mark Langsdorf
---
drivers/ata/sata_highbank.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index d047d92..e9a4f46
Some board designs do not drive the SATA transmit lines within the
specification. The ECME can provide override settings, on a per board
basis, to bring the transmit lines within spec. Read those settings
from the DTB and program them in.
Signed-off-by: Mark Langsdorf
---
.../devicetree
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
drivers/ata/sata_highbank.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index e9a4f46..8b40025 100644
--- a/drivers/ata/sata_highbank.c
+++ b
On 06/12/2013 03:15 AM, Viresh Kumar wrote:
> Highbank cpufreq driver doesn't use any APIs from freq_table.c and so must not
> select CPU_FREQ_TABLE.
>
> Cc: Mark Langsdorf
> Signed-off-by: Viresh Kumar
Thanks for catching this.
Acked-by: Mark Langsdorf
> ---
> d
Highbank supports SGPIO by bit-banging out the SGPIO signals over
three GPIO pins defined in the DTB. Add support for this SGPIO
functionality.
Signed-off-by: Mark Langsdorf
---
Changes from v3:
Correctly mask the activity bits to clear bits in ecx_parse_sgpio()
Changes from v2
,On 06/05/2013 06:15 PM, Tejun Heo wrote:
> Hello,
>
> On Wed, Jun 05, 2013 at 05:31:48PM -0500, Mark Langsdorf wrote:
>> +static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32
>> state)
>> +{
>> +if (state & ECX_ACTIVITY_BITS)
Highbank supports SGPIO by bit-banging out the SGPIO signals over
three GPIO pins defined in the DTB. Add support for this SGPIO
functionality.
Signed-off-by: Mark Langsdorf
---
Changes from v2:
Added plat_data to ahci_host_priv
Moved driver specific data to plat_data and got rid
On 06/04/2013 03:32 PM, Tejun Heo wrote:
> Hello, Mark.
>
> On Tue, Jun 04, 2013 at 10:09:41AM -0500, Mark Langsdorf wrote:
>>> And tell ahci core sizeof(ecx_host_priv) some way, but really, just
>>> having a plain pointer should be enough, I think.
>>
>> I
ahci_save_initial_config(dev, hpriv, 0, 0);
>> +ahci_save_initial_config(dev, (struct ahci_host_priv *) hpriv, 0, 0);
>
> Ugh... how is this supposed to work? What if ahci_host_priv grows
> larger than ecx one in the future? :(
For functions like ahci_save_initial_config,
Highbank supports SGPIO by bit-banging out the SGPIO signals over
three GPIO pins defined in the DTB. Add support for this SGPIO
functionality.
Signed-off-by: Mark Langsdorf
---
Changes from v1:
Moved all global variables to a private structure
Replaced all magic numbers with
Increase the retry count for the hard reset function to 100 but
shorten the time out period to 500 ms. See the comment for
ahci_highbank_hardreset for the reasons why those vaulues were
chosen.
Signed-off-by: Mark Langsdorf
---
Changes from v3
Move the detail to a comment on the
On 06/02/2013 03:00 AM, Tejun Heo wrote:
> On Fri, May 31, 2013 at 10:27:26AM -0500, Mark Langsdorf wrote:
>
> For the third time, explain the above in the comment; otherwise, it's
> not going in.
Sorry, I completely misread your requirement. I'll move it to the
comment
experiences a time out
issue. Shorten the Linux time-out value for this driver to 500 ms and
keep the other timing constants the same as the stock AHCI driver. This
change was also tested 15000 times on 24 drives and none of them
experienced a time out.
Signed-off-by: Mark Langsdorf
---
Changes
Highbank supports SGPIO by bit-banging out the SGPIO signals over
three GPIO pins defined in the DTB. Add support for this SGPIO
functionality.
Signed-off-by: Mark Langsdorf
---
.../devicetree/bindings/ata/ahci-platform.txt | 9 ++
arch/arm/boot/dts/ecx-common.dtsi | 1
Create a new ata_port_operations function pointer called
transmit_led_message and give it the default value of
ahci_transmit_led_message. This allows AHCI controllers with
non-standard LED interfaces to use the existing em_ interface.
Signed-off-by: Mark Langsdorf
---
drivers/ata/libahci.c
experiences a time out
issue. Shorten the Linux time-out value for this driver to 500 ms and
keep the other timing constants the same as the stock AHCI driver. This
change was also tested 15000 times on 24 drives and none of them
experienced a time out.
Signed-off-by: Mark Langsdorf
---
Changes
On 05/29/2013 03:12 PM, Timur Tabi wrote:
> On Wed, May 29, 2013 at 10:51 AM, Mark Langsdorf
> wrote:
>>
>> {
>> - const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
>> + unsigned long timing[] = { 5, 100, 500};
>
>
>
retry count to guarantee the link is established.
Also, the default 2 second time-out on a failed drive is too long in
this situation. Shorten it to 500 ms. This was also tested 15000 times
on 24 drives and none of them experienced a time out.
Signed-off-by: Mark Langsdorf
---
drivers/ata
retry count to guarantee the link is established.
Also, the default 2 second time-out on a failed drive is too long in
this situation. Shorten it to 500 ms. This was also tested 15000 times
on 24 drives and none of them experienced a time out.
Signed-off-by: Mark Langsdorf
---
drivers/ata
(chan, (void *)msg))
>>> + ret = msg[1]; /* PL320 updates buffer with FIFO after ACK */
>>> +
>>> + ipc_free_channel(chan);
>>
>> I think I understand why you have done this, but do you really want to
>> request and free every time in the h
introduction of the generic mailbox API framework.
>
> Signed-off-by: Suman Anna
> Cc: Mark Langsdorf
> Cc: Rafael J. Wysocki
> ---
> drivers/cpufreq/highbank-cpufreq.c |2 +-
> drivers/mailbox/pl320-ipc.c |2 +-
> include/linux/{mailbox.h =&g
Avoids a section mismatch.
Signed-off-by: Mark Langsdorf
---
drivers/mailbox/pl320-ipc.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mailbox/pl320-ipc.c b/drivers/mailbox/pl320-ipc.c
index c45b3ae..d873cba 100644
--- a/drivers/mailbox/pl320-ipc.c
+++ b
REQ_CHANGE_NOTE, freq / 100};
>
> return pl320_ipc_transmit(msg);
> }
>
Thanks for the improvement.
Acked-By: Mark Langsdorf
--Mark Langsdorf
Calxeda, Inc.
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Please read the FAQ at http://www.tux.org/lkml/
From: Rob Herring
The pl320 IPC allows for interprocessor communication between the
highbank A9 and the EnergyCore Management Engine. The pl320 implements
a straightforward mailbox protocol.
Signed-off-by: Mark Langsdorf
Signed-off-by: Rob Herring
Cc: Omar Ramirez Luna
Cc: Arnd Bergmann
.
Previous versions of this patch set include two other patches. One has
been dropped as unworkable and the other turned out to be unnecessary.
--Mark Langsdorf
Calxeda, Inc.
--
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the body of a message
Highbank processors depend on the external ECME to perform voltage
management based on a requested frequency. Communication between the
A9 cores and the ECME happens over the pl320 IPC channel.
Signed-off-by: Mark Langsdorf
Reviewed-by: Shawn Guo
Reviewed-by: Mike Turquette
---
Changes from
From: Rob Herring
Move clk setup to twd_local_timer_common_register and rely on
twd_timer_rate being 0 to force calibration if there is no clock.
Remove common_setup_called as it is no longer needed.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Acked-by: Russell King
---
Changes
The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.
Signed-off-by: Mark Langsdorf
Signed-off-by: Rob Herring
Acked-by: Mike Turquette
---
Changes from v6, v7, v8, v9, v10, v11
None
> Is it OK to make that change when applying the patch or do you want to send
> a new one?
I probably should resend so I can include the drivers level Kconfig and
Makefile.
I'll get that out this morning.
--Mark Langsdorf
Calxeda, Inc.
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The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.
Signed-off-by: Mark Langsdorf
Signed-off-by: Rob Herring
Acked-by: Mike Turquette
---
Changes from v6, v7, v8, v9, v10
None.
Changes
From: Rob Herring
The pl320 IPC allows for interprocessor communication between the highbank A9
and the EnergyCore Management Engine. The pl320 implements a straightforward
mailbox protocol.
Signed-off-by: Mark Langsdorf
Signed-off-by: Rob Herring
Cc: Omar Ramirez Luna
Cc: Arnd Bergmann
Highbank processors depend on the external ECME to perform voltage
management based on a requested frequency. Communication between the
A9 cores and the ECME happens over the pl320 IPC channel.
Signed-off-by: Mark Langsdorf
Reviewed-by: Shawn Guo
Reviewed-by: Mike Turquette
---
Changes from
.
Previous versions of this patch set include two other patches. One has
been dropped as unworkable and the other turned out to be unnecessary.
--Mark Langsdorf
Calxeda, Inc.
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From: Rob Herring
Move clk setup to twd_local_timer_common_register and rely on
twd_timer_rate being 0 to force calibration if there is no clock.
Remove common_setup_called as it is no longer needed.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v10
The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.
Signed-off-by: Mark Langsdorf
Signed-off-by: Rob Herring
Acked-by: Mike Turquette
---
Changes from v6, v7, v8, v9
None.
Changes from
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v9
Updated to work with 3.8 kernel.
Changes from v4, v5, v6, v7, v8
None.
Changes from v3
No longer setting *clk to NULL in twd_get_clock().
Changes from v2
Turned the
Highbank processors depend on the external ECME to perform voltage
management based on a requested frequency. Communication between the
A9 cores and the ECME happens over the pl320 IPC channel.
Signed-off-by: Mark Langsdorf
Reviewed-by: Shawn Guo
Reviewed-by: Mike Turquette
---
Changes from v9
From: Rob Herring
The pl320 IPC allows for interprocessor communication between the highbank A9
and the EnergyCore Management Engine. The pl320 implements a straightforward
mailbox protocol.
This patch depends on Omar Ramirez Luna's
mailbox driver patch series.
Signed-off-by: Mark Lang
.
Previous versions of this patch set include two other patches. One has
been dropped as unworkable and the other got picked up and included in
3.8.0.
--Mark Langsdorf
Calxeda, Inc.
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n unrelated bug that's
preventing my test box from booting.
--Mark Langsdorf
Calxeda, Inc.
From: Rafael J. Wysocki [r...@sisk.pl]
Sent: Thursday, December 27, 2012 7:12 AM
To: Mark Langsdorf
Cc: linux-kernel@vger.kernel.org; cpuf...@vge
This patch is withdrawn due to a need for severe rework.
Changes from v4
Withdrawn.
Changes from v3, v2
None.
Changes from v1
Implemented a simple round-up algorithm instead of the over/under
method that could cause errors on Intel processors with boost mode.
--
To u
From: Rob Herring
The pl320 IPC allows for interprocessor communication between the highbank A9
and the EnergyCore Management Engine. The pl320 implements a straightforward
mailbox protocol.
This patch depends on Omar Ramirez Luna's
mailbox driver patch series.
Signed-off-by: Mark Lang
These functions are needed to make the cpufreq-core0 and highbank-cpufreq
drivers loadable as modules.
Signed-off-by: Mark Langsdorf
Acked-by: Nishanth Menon
---
Changes from v4, v5, v6, v7, v8
None.
Changes from v3
includes linux/export.h instead of module.h.
Changes from v2
Highbank processors depend on the external ECME to perform voltage
management based on a requested frequency. Communication between the
A9 cores and the ECME happens over the pl320 IPC channel.
Signed-off-by: Mark Langsdorf
Reviewed-by: Shawn Guo
Cc: mturque...@linaro.org
---
Changes from v8
.
--Mark Langsdorf
Calxeda, Inc.
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Please read the FAQ at http://www.tux.org/lkml/
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v4, v5, v6, v7, v8
None.
Changes from v3
No longer setting *clk to NULL in twd_get_clock().
Changes from v2
Turned the check for the node pointer into an if-then-else statement
The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.
Signed-off-by: Mark Langsdorf
Signed-off-by: Rob Herring
Acked-by: Mike Turquette
---
Changes from v6, v7, v8
None.
Changes from v5
On 12/05/2012 12:49 PM, Mike Turquette wrote:
> On Wed, Dec 5, 2012 at 8:48 AM, Mark Langsdorf
> wrote:
>> diff --git a/drivers/cpufreq/highbank-cpufreq.c
>> b/drivers/cpufreq/highbank-cpufreq.c
>> new file mode 100644
>> index 000..1f28fa6
>> --- /dev/nu
This patch is withdrawn due to a need for severe rework.
Changes from v4
Withdrawn.
Changes from v3, v2
None.
Changes from v1
Implemented a simple round-up algorithm instead of the over/under
method that could cause errors on Intel processors with boost mode.
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