The following commit has been merged into the timers/core branch of tip:
Commit-ID: c90d37c9c41a572ea7183299951341b4640d5b4b
Gitweb:
https://git.kernel.org/tip/c90d37c9c41a572ea7183299951341b4640d5b4b
Author:Magnus Damm
AuthorDate:Tue, 20 Aug 2019 21:35:03 +09:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 1be8c9fd2ac9ad730cf537b8909f66c357866c5d
Gitweb:
https://git.kernel.org/tip/1be8c9fd2ac9ad730cf537b8909f66c357866c5d
Author:Magnus Damm
AuthorDate:Tue, 20 Aug 2019 21:35:46 +09:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 649dd060334f13792f624ec3fa8a0024ed1e02bc
Gitweb:
https://git.kernel.org/tip/649dd060334f13792f624ec3fa8a0024ed1e02bc
Author:Magnus Damm
AuthorDate:Tue, 20 Aug 2019 21:35:25 +09:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 53933bc3a69e0f07a1af2fea16fda9c816ffcf87
Gitweb:
https://git.kernel.org/tip/53933bc3a69e0f07a1af2fea16fda9c816ffcf87
Author:Magnus Damm
AuthorDate:Tue, 20 Aug 2019 21:35:36 +09:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 19d608458f4f3bb3a1f89bd7e4814c3fd30dbec7
Gitweb:
https://git.kernel.org/tip/19d608458f4f3bb3a1f89bd7e4814c3fd30dbec7
Author:Magnus Damm
AuthorDate:Tue, 20 Aug 2019 21:36:07 +09:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 8c1afba285a86b9dbb0637f8c70a34fe2d88569e
Gitweb:
https://git.kernel.org/tip/8c1afba285a86b9dbb0637f8c70a34fe2d88569e
Author:Magnus Damm
AuthorDate:Tue, 20 Aug 2019 21:35:56 +09:00
The following commit has been merged into the timers/core branch of tip:
Commit-ID: 81b604c39997de91f4b2912f803074c85045fe36
Gitweb:
https://git.kernel.org/tip/81b604c39997de91f4b2912f803074c85045fe36
Author:Magnus Damm
AuthorDate:Tue, 20 Aug 2019 21:35:14 +09:00
From: Magnus Damm
Update the CMT driver to mark "renesas,cmt-48" as deprecated.
Instead of documenting a theoretical hardware device based on current software
support level, define DT bindings top-down based on available data sheet
information and make use of part numbers in the
From: Magnus Damm
Add SoC-specific matching for CMT1 on r8a7740 and sh73a0.
This allows us to move away from the old DT bindings such as
- "renesas,cmt-48-sh73a0"
- "renesas,cmt-48-r8a7740"
- "renesas,cmt-48"
in favour for the now commonly used format "ren
Hi Simon,
On Wed, Jul 24, 2019 at 8:12 PM Simon Horman wrote:
>
> On Thu, Jul 18, 2019 at 08:45:24PM +0900, Magnus Damm wrote:
> > From: Magnus Damm
> >
> > Add SoC-specific matching for CMT1 on r8a7740 and sh73a0.
> >
> > This allows us to move a
From: Magnus Damm
This patch reworks the DT binding documentation for the 6-channel
48-bit CMTs known as CMT1 on r8a7740 and sh73a0.
After the update the same style of DT binding as the rest of the upstream
SoCs will now also be used by r8a7740 and sh73a0. The DT binding "cmt-48"
From: Magnus Damm
The R-Car Gen3 SoCs so far come with a total for 4 on-chip CMT devices:
- CMT0
- CMT1
- CMT2
- CMT3
CMT0 includes two rather basic 32-bit timer channels. The rest of the on-chip
CMT devices support 48-bit counters and have 8 channels each.
Based on the data sheet
From: Magnus Damm
This patch adds DT binding documentation for the CMT devices on
the R-Car Gen3 D3 (r8a77995) SoC.
Signed-off-by: Magnus Damm
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
Reviewed-by: Simon Horman
---
Documentation/devicetree/bindings/timer/renesas,cmt.txt
From: Magnus Damm
This patch adds DT binding documentation for the CMT devices on
the R-Car Gen2 V2H (r8a7792) SoC.
Signed-off-by: Magnus Damm
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
Reviewed-by: Simon Horman
---
Documentation/devicetree/bindings/timer/renesas,cmt.txt
From: Magnus Damm
Document the on-chip CMT devices included in r8a7740 and sh73a0.
Included in this patch is DT binding documentation for 32-bit CMTs
CMT0, CMT2, CMT3 and CMT4. They all contain a single channel and are
quite similar however some minor differences still exist:
- "Counter
viewed-by from Simon - thanks!
Please see each individual patch for more detailed information.
Signed-off-by: Magnus Damm
Reviewed-by: Geert Uytterhoeven [Patch 3-5]
Reviewed-by: Rob Herring [Patch 1-5]
Reviewed-by: Simon Horman
---
Developed on top of "renesas-drivers-2019-08-13-v5.
From: Magnus Damm
Add SoC-specific matching for CMT1 on r8a7740 and sh73a0.
This allows us to move away from the old DT bindings such as
- "renesas,cmt-48-sh73a0"
- "renesas,cmt-48-r8a7740"
- "renesas,cmt-48"
in favour for the now commonly used format "ren
From: Magnus Damm
Update the CMT driver to mark "renesas,cmt-48" as deprecated.
Instead of documenting a theoretical hardware device based on current software
support level, define DT bindings top-down based on available data sheet
information and make use of part numbers in the
From: Magnus Damm
This patch adds DT binding documentation for the CMT devices on
the R-Car Gen3 D3 (r8a77995) SoC.
Signed-off-by: Magnus Damm
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/timer/renesas,cmt.txt |2 ++
1 file changed, 2
From: Magnus Damm
The R-Car Gen3 SoCs so far come with a total for 4 on-chip CMT devices:
- CMT0
- CMT1
- CMT2
- CMT3
CMT0 includes two rather basic 32-bit timer channels. The rest of the on-chip
CMT devices support 48-bit counters and have 8 channels each.
Based on the data sheet
From: Magnus Damm
This patch reworks the DT binding documentation for the 6-channel
48-bit CMTs known as CMT1 on r8a7740 and sh73a0.
After the update the same style of DT binding as the rest of the upstream
SoCs will now also be used by r8a7740 and sh73a0. The DT binding "cmt-48"
From: Magnus Damm
Document the on-chip CMT devices included in r8a7740 and sh73a0.
Included in this patch is DT binding documentation for 32-bit CMTs
CMT0, CMT2, CMT3 and CMT4. They all contain a single channel and are
quite similar however some minor differences still exist:
- "Counter
From: Magnus Damm
This patch adds DT binding documentation for the CMT devices on
the R-Car Gen2 V2H (r8a7792) SoC.
Signed-off-by: Magnus Damm
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/timer/renesas,cmt.txt |2 ++
1 file changed, 2
(r8a77995).
- Update the R-Car Gen3 DT documentation to reflect current usage.
- Introduce SoC-specific matching in the driver for CMT1 on sh73a0 and sh73a0.
- Document old "cmt-48" binding as deprecated in the driver.
Please see each individual patch for more detailed information.
Signed
Hi Robin,
On Tue, Jun 20, 2017 at 2:19 AM, Robin Murphy wrote:
> On 19/06/17 10:14, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Add root device handling to the IPMMU driver by allowing certain
>> DT compat strings to enable has_cache_leaf_nodes that in turn will
&
From: Magnus Damm
Introduce support for two bit SL0 bitfield in IMTTBCR
by using a separate feature flag.
Signed-off-by: Magnus Damm
---
Changes since V4:
- Use leaf node mmu instead of root
Changes since V3:
- None
Changes since V2:
- None
Changes since V1:
- None
drivers/iommu
From: Magnus Damm
Tie in r8a7795 features and update the IOMMU_OF_DECLARE
compat string to include the updated compat string.
Signed-off-by: Magnus Damm
---
Changes since V4:
- Got rid of root device availability check in ->xlate()
-> deferred probing is used to make sure the r
From: Magnus Damm
Write IMCTR both in the root device and the leaf node.
To allow access of IMCTR introduce the following function:
- ipmmu_ctx_write_all()
While at it also rename context functions:
- ipmmu_ctx_read() -> ipmmu_ctx_read_root()
- ipmmu_ctx_write() -> ipmmu_ctx_writ
From: Magnus Damm
Introduce a feature to allow opt-out of setting up
IMBUSCR. The default case is unchanged.
Signed-off-by: Magnus Damm
---
Changes since V4:
- Use leaf node mmu instead of root
Changes since V3:
- None
Changes since V2:
- None
Changes since V1:
- Updated the commit
From: Magnus Damm
The r8a7795 IPMMU supports 40-bit bus mastering. Both
the coherent DMA mask and the streaming DMA mask are
set to unlock the 40-bit address space for coherent
allocations and streaming operations.
Signed-off-by: Magnus Damm
---
Changes since V4:
- None
Changes since V3
From: Magnus Damm
Hook up IOMMU_OF_DECLARE() support in case CONFIG_IOMMU_DMA
is enabled. The only current supported case for 32-bit ARM
is disabled, however for 64-bit ARM usage of OF is required.
Signed-off-by: Magnus Damm
---
Changes since V4:
- Use ipmmu_is_root() instead of now removed
From: Magnus Damm
Add support for up to 8 contexts. Each context is mapped to one
domain. One domain is assigned one or more slave devices. Contexts
are allocated dynamically and slave devices are grouped together
based on which IPMMU device they are connected to. This makes slave
devices tied
From: Magnus Damm
Add root device handling to the IPMMU driver by allowing certain
DT compat strings to enable has_cache_leaf_nodes that in turn will
support both root devices with interrupts and leaf devices that
face the actual IPMMU consumer devices.
Signed-off-by: Magnus Damm
---
Changes
From: Magnus Damm
Introduce struct ipmmu_features to track various hardware
and software implementation changes inside the driver for
different kinds of IPMMU hardware. Add use_ns_alias_offset
as a first example of a feature to control if the secure
register bank offset should be used or not
-bit ARM update V2
- Reworked root device handling to make use of driver_for_each_device()
- Added deferred probing to make sure root device always is present
Signed-off-by: Magnus Damm
---
Developed on top of next-20171013
Also applies to renesas-drivers-2017-10-03-v4.14-rc3
Tested on top
From: Magnus Damm
Extend the driver to make use of iommu_device_sysfs_add()/remove()
functions to hook up initial sysfs support.
Suggested-by: Joerg Roedel
Signed-off-by: Magnus Damm
---
Applies on top of next-20170817
drivers/iommu/ipmmu-vmsa.c |6 ++
1 file changed, 6 insertions
-by: Magnus Damm
---
Changes since V1:
- Rebased to apply on top of earlier changes in series
drivers/iommu/ipmmu-vmsa.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
--- 0004/drivers/iommu/ipmmu-vmsa.c
+++ work/drivers/iommu/ipmmu-vmsa.c 2017-07-17 21:04
From: Magnus Damm
Now when both 32-bit and 64-bit code inside the driver is using
fwspec it is possible to replace the utlb handling with fwspec ids
that get populated from ->of_xlate().
Suggested-by: Robin Murphy
Signed-off-by: Magnus Damm
---
Changes since V1:
- Rebased to apply on
Signed-off-by: Magnus Damm
---
Change since V1:
- New patch
drivers/iommu/ipmmu-vmsa.c | 12
1 file changed, 12 deletions(-)
--- 0008/drivers/iommu/ipmmu-vmsa.c
+++ work/drivers/iommu/ipmmu-vmsa.c 2017-07-17 21:35:26.690607110 +0900
@@ -37,7 +37,6 @@ struct ipmmu_vmsa_device
From: Magnus Damm
The 32-bit ARM code gets updated to make use of ->of_xlate() and the
code is shared between 64-bit and 32-bit ARM. The of_device_is_available()
check gets dropped since it is included in of_iommu_xlate().
Suggested-by: Robin Murphy
Signed-off-by: Magnus Damm
---
Chan
From: Magnus Damm
Extend the driver to make use of iommu_device_register()/unregister()
functions together with iommu_device_set_ops() and iommu_set_fwnode().
These used to be part of the earlier posted 64-bit ARM (r8a7795) series but
it turns out that these days they are required on 32-bit ARM
ted-by: Robin Murphy (Patch 2 and 4)
Signed-off-by: Robin Murphy (Patch 3 and 5)
Signed-off-by: Magnus Damm
---
Changes since V1:
- Minor changes to patch 1 and 2 - thanks Robin and Geert!
- Added patch 5 to include further clean ups
Developed on top of v4.13-rc1
drivers/iommu/ipmmu-vms
From: Magnus Damm
Update the IPMMU DT binding documentation to include the r8a7796 compat
string for R-Car M3-W.
Signed-off-by: Magnus Damm
Acked-by: Laurent Pinchart
Acked-by: Rob Herring
Acked-by: Simon Horman
Acked-by: Geert Uytterhoeven
---
Changes since V3:
- None
Changes since
From: Magnus Damm
Support the r8a7796 IPMMU by sharing feature flags between
r8a7795 and r8a7796. Also update IOMMU_OF_DECLARE to hook
up the updated compat string.
Signed-off-by: Magnus Damm
Reviewed-by: Geert Uytterhoeven
---
Changes since V3:
- Added Reviewed-by from Geert - thanks
From: Magnus Damm
Bump up the maximum numbers of micro-TLBS to 48.
Each IPMMU device instance get micro-TLB assignment via
the "iommus" property in DT. Older SoCs tend to use a
maximum number of 32 micro-TLBs per IPMMU instance however
newer SoCs such as r8a7796 make use of up to 48
upstream merge and includes the following tags:
Signed-off-by: Magnus Damm
Acked-by: Laurent Pinchart
Acked-by: Rob Herring
Acked-by: Simon Horman
Acked-by: Geert Uytterhoeven
Patch 2/3 and 3/3 are quite trivial but have no acked-by so far.
Signed-off-by: Magnus Damm
---
Developed on top of
From: Magnus Damm
Tie in r8a7795 features and update the IOMMU_OF_DECLARE
compat string to include the updated compat string.
Signed-off-by: Magnus Damm
---
Changes since V3:
- Rebased code on top of
[PATCH 00/04] iommu/ipmmu-vmsa: 32-bit ARM update
This includes support for
From: Magnus Damm
Hook up IOMMU_OF_DECLARE() support in case CONFIG_IOMMU_DMA
is enabled. The only current supported case for 32-bit ARM
is disabled, however for 64-bit ARM usage of OF is required.
Signed-off-by: Magnus Damm
---
Changes since V3:
- Reworked to fit on top of
[PATCH 00/04
From: Magnus Damm
Introduce support for two bit SL0 bitfield in IMTTBCR
by using a separate feature flag.
Signed-off-by: Magnus Damm
---
Changes since V3:
- None
Changes since V2:
- None
Changes since V1:
- None
drivers/iommu/ipmmu-vmsa.c | 14 +-
1 file changed, 13
From: Magnus Damm
Introduce a feature to allow opt-out of setting up
IMBUSCR. The default case is unchanged.
Signed-off-by: Magnus Damm
---
Changes since V3:
- None
Changes since V2:
- None
Changes since V1:
- Updated the commit message
- Reworked patch to coexist with the multi
From: Magnus Damm
The r8a7795 IPMMU supports 40-bit bus mastering. Both
the coherent DMA mask and the streaming DMA mask are
set to unlock the 40-bit address space for coherent
allocations and streaming operations.
Signed-off-by: Magnus Damm
---
Changes since V3:
- None
Changes since V2
From: Magnus Damm
Write IMCTR both in the root device and the leaf node.
To allow access of IMCTR introduce the following function:
- ipmmu_ctx_write_all()
While at it also rename context functions:
- ipmmu_ctx_read() -> ipmmu_ctx_read_root()
- ipmmu_ctx_write() -> ipmmu_ctx_writ
From: Magnus Damm
Add support for up to 8 contexts. Each context is mapped to one
domain. One domain is assigned one or more slave devices. Contexts
are allocated dynamically and slave devices are grouped together
based on which IPMMU device they are connected to. This makes slave
devices tied
kes use of iommu_device_* functions
- Patch 5/9 sets the mask to 40 bits instead of 64 bits
- Patch 9/9 implements white list handling via ->xlate() and fixes a bug
Signed-off-by: Magnus Damm
---
Developed on top of next-20170614 with the following series applied
[PATCH 00/04] iommu/ipmmu-vmsa: 3
From: Magnus Damm
Add root device handling to the IPMMU driver by allowing certain
DT compat strings to enable has_cache_leaf_nodes that in turn will
support both root devices with interrupts and leaf devices that
face the actual IPMMU consumer devices.
Signed-off-by: Magnus Damm
---
Changes
From: Magnus Damm
Introduce struct ipmmu_features to track various hardware
and software implementation changes inside the driver for
different kinds of IPMMU hardware. Add use_ns_alias_offset
as a first example of a feature to control if the secure
register bank offset should be used or not
Hi Geert,
On Fri, Jun 16, 2017 at 4:18 PM, Geert Uytterhoeven
wrote:
> Hi Magnus,
>
> On Thu, Jun 15, 2017 at 12:29 PM, Magnus Damm wrote:
>> Now when both 32-bit and 64-bit code inside the driver is using
>> fwspec it is possible to replace the utlb handling with f
From: Magnus Damm
The 32-bit ARM code gets updated to make use of ->of_xlate() and the
code is shared between 64-bit and 32-bit ARM. The of_device_is_available()
check gets dropped since it is included in of_iommu_xlate().
Suggested-by: Robin Murphy
Signed-off-by: Magnus Damm
---
driv
From: Magnus Damm
Extend the driver to make use of iommu_device_register()/unregister()
functions together with iommu_device_set_ops() and iommu_set_fwnode().
These used to be part of the earlier posted 64-bit ARM (r8a7795) series but
it turns out that these days they are required on 32-bit ARM
-by: Magnus Damm
---
drivers/iommu/ipmmu-vmsa.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
--- 0010/drivers/iommu/ipmmu-vmsa.c
+++ work/drivers/iommu/ipmmu-vmsa.c 2017-06-15 17:29:00.290607110 +0900
@@ -73,22 +73,9 @@ static struct ipmmu_vmsa_domain *to_vmsa
From: Magnus Damm
Now when both 32-bit and 64-bit code inside the driver is using
fwspec it is possible to replace the utlb handling with fwspec ids
that get populated from ->of_xlate().
Suggested-by: Robin Murphy
Signed-off-by: Magnus Damm
---
drivers/iommu/ipmmu-vmsa.c |
h 3)
Signed-off-by: Magnus Damm
---
Developed on renesas-drivers-2017-06-13-v4.12-rc5 and rebased to next-20170614
drivers/iommu/ipmmu-vmsa.c | 186 +++-
1 file changed, 49 insertions(+), 137 deletions(-)
From: Magnus Damm
Update ->ndo_change_mtu() callback comment to remove text
about returning error in case of undefined callback. This
change makes the comment match the existing code behavior.
Signed-off-by: Magnus Damm
---
Applies on top of next-20170613
include/linux/netdevice.h |
On Wed, Jun 14, 2017 at 6:33 AM, David Miller wrote:
> From: Magnus Damm
> Date: Wed, 14 Jun 2017 02:18:27 +0900
>
>> From: Magnus Damm
>>
>> Allow adjusting the MTU for via-rhine devices in case of no TX alignment
>> buffer is used.
>>
>> Lightly
From: Magnus Damm
Allow adjusting the MTU for via-rhine devices in case of no TX alignment
buffer is used.
Lightly tested on ALIX2D13 hardware by making use of VXLAN with MTU set
to 1500 on top of via-rhine devices with 1550 MTU. Without this patch
the VXLAN MTU is limited to less than 1500
Hi Robin,
On Wed, May 17, 2017 at 11:29 PM, Robin Murphy wrote:
> Hi Magnus,
>
> On 17/05/17 11:07, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Convert from archdata to iommu_priv via iommu_fwspec on ARM64 but
>> let 32-bit ARM keep on using archdata for no
From: Magnus Damm
Neither the ARM page table code enabled by IOMMU_IO_PGTABLE_LPAE
nor the IPMMU_VMSA driver actually depends on ARM_LPAE, so get
rid of the dependency.
Tested with ipmmu-vmsa on r8a7794 ALT and a kernel config using:
# CONFIG_ARM_LPAE is not set
Signed-off-by: Magnus Damm
From: Magnus Damm
Fix comma-instead-of-semicolon typo error present
in the latest version of the IPMMU driver.
Signed-off-by: Magnus Damm
---
Earlier posted as:
[PATCH] iommu/ipmmu-vmsa: Fix pgsize_bitmap semicolon typo
drivers/iommu/ipmmu-vmsa.c |2 +-
1 file changed, 1 insertion
From: Magnus Damm
Convert from archdata to iommu_priv via iommu_fwspec on ARM64 but
let 32-bit ARM keep on using archdata for now.
Once the 32-bit ARM code and the IPMMU driver is able to move over
to CONFIG_IOMMU_DMA=y then coverting to fwspec via ->of_xlate() will
be easy.
For now fwspec
From: Magnus Damm
Introduce an alternative set of iommu_ops suitable for 64-bit ARM
as well as 32-bit ARM when CONFIG_IOMMU_DMA=y. Also adjust the
Kconfig to depend on ARM or IOMMU_DMA. Initialize the device
from ->xlate() when CONFIG_IOMMU_DMA=y.
Signed-off-by: Magnus Damm
---
Changes si
From: Magnus Damm
Introduce a bitmap for context handing and convert the
interrupt routine to handle all registered contexts.
At this point the number of contexts are still limited.
Also remove the use of the ARM specific mapping variable
from ipmmu_irq() to allow compile on ARM64.
Signed-off
From: Magnus Damm
The IPMMU driver is using DT these days, and platform data is no longer
used by the driver. Remove unused code.
Signed-off-by: Magnus Damm
Reviewed-by: Laurent Pinchart
Reviewed-by: Joerg Roedel
Reviewed-by: Geert Uytterhoeven
---
Changes since V7:
- Added Reviewed-by
From: Magnus Damm
Break out the domain allocation code into a separate function.
This is preparation for future code sharing.
Signed-off-by: Magnus Damm
Reviewed-by: Joerg Roedel
Reviewed-by: Geert Uytterhoeven
---
Changes since V7:
- Added Reviewed-by from Geert - Thanks!
drivers
ial series
- Updated bitmap code locking and also used lighter bitop functions
- Updated the Kconfig bits to apply on top of ARCH_RENESAS
Signed-off-by: Magnus Damm
---
Developed on top of a95cfad (v4.12-rc1 + fixes):
Compile tested on 32-bit and 64-bit ARM
Run time tested on 64-bit ARM r8a7
From: Magnus Damm
Break out the utlb parsing code and dev_data allocation into a
separate function. This is preparation for future code sharing.
Signed-off-by: Magnus Damm
Reviewed-by: Joerg Roedel
---
Changes since V7:
- Free archdata and utlbs in case of error
drivers/iommu/ipmmu
From: Magnus Damm
Fix comman-instead-of-semicolon typo error present
in the latest version of the IPMMU driver.
Will in the future be rolled into next driver update.
Signed-off-by: Magnus Damm
---
Applies on top of renesas-drivers-2017-04-18-v4.11-rc7 or -next plus:
[PATCH v7 00/07] iommu
patch
These patches probably need a bit more effort to be beaten into shape
for upstream merge. So simply treat these as experimental test code.
Not-Yet-Signed-off-by: Magnus Damm
---
Developed on top of renesas-drivers-2017-02-21-v4.10
arch/arm64/boot/dts/renesas/r8a7795.dtsi |2
drivers
From: Magnus Damm
The priority handling uses MID/RID values to determine if channels
below to RX or TX sides. The case of RX is unchanged and as low channel
number as possible is used to ensure high priority. New with this code
is that TX is allocated with highest channel number first to force
From: Magnus Damm
Experimental code to enable slow mode on r8a7795 for SCIF2 TX.
Not-Yet-Signed-off-by: Magnus Damm
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- 0001/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ work/arch/arm64
From: Magnus Damm
This experimental slow mode support code simply extends the MID/RID value
to allow encoding a 4-bit value in bit 8-11 to specify the SLM bit value.
With this value set the channel associated with the device will be processed
slower by the hardware. The idea is that the slow
From: Magnus Damm
Support the r8a7796 IPMMU by sharing feature flags between
r8a7795 and r8a7796. Also update IOMMU_OF_DECLARE to hook
up the updated compat string.
Signed-off-by: Magnus Damm
---
Changes since V2:
- Updated to include white list suppport
Changes since V1:
- None
From: Magnus Damm
Bump up the maximum numbers of micro-TLBS to 48.
Each IPMMU device instance get micro-TLB assignment via
the "iommus" property in DT. Older SoCs tend to use a
maximum number of 32 micro-TLBs per IPMMU instance however
newer SoCs such as r8a7796 make use of up to 48
Changes since V1:
- Patch 1/3 updated with more Acked-by tags
- Patch 2/3 updated with high I/O register range support
Patch 1/3 is ready for upstream merge and includes the following tags:
Signed-off-by: Magnus Damm
Acked-by: Laurent Pinchart
Acked-by: Rob Herring
Acked-by: Simon Horman
From: Magnus Damm
Update the IPMMU DT binding documentation to include the r8a7796 compat
string for R-Car M3-W.
Signed-off-by: Magnus Damm
Acked-by: Laurent Pinchart
Acked-by: Rob Herring
Acked-by: Simon Horman
Acked-by: Geert Uytterhoeven
---
Changes since V2:
- None
Changes since
Hi Geert,
On Wed, Mar 8, 2017 at 10:47 PM, Geert Uytterhoeven
wrote:
> Hi Magnus,
>
> On Wed, Mar 8, 2017 at 12:01 PM, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Add root device handling to the IPMMU driver by allowing certain
>> DT compat strings to enable
Hi Robin,
On Wed, Mar 8, 2017 at 8:53 PM, Robin Murphy wrote:
> Hi Magnus,
>
> On 08/03/17 11:01, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Introduce struct ipmmu_features to track various hardware
>> and software implementation changes inside the drive
Hi Geert,
On Wed, Mar 8, 2017 at 10:58 PM, Geert Uytterhoeven
wrote:
> Hi Magnus,
>
> On Wed, Mar 8, 2017 at 12:02 PM, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Tie in r8a7795 features and update the IOMMU_OF_DECLARE
>> compat string to include the
Hi Robin,
Thanks for your feedback!
On Wed, Mar 8, 2017 at 9:21 PM, Robin Murphy wrote:
> On 08/03/17 11:01, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Add support for up to 8 contexts. Each context is mapped to one
>> domain. One domain is assigned one or m
Hi Robin,
On Wed, Mar 8, 2017 at 9:34 PM, Robin Murphy wrote:
> On 08/03/17 11:02, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Write IMCTR both in the root device and the leaf node.
>>
>> Signed-off-by: Magnus Damm
>> ---
>>
>> C
Hi Geert,
On Wed, Mar 8, 2017 at 10:52 PM, Geert Uytterhoeven
wrote:
> Hi Magnus,
>
> On Wed, Mar 8, 2017 at 12:02 PM, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Hook up IOMMU_OF_DECLARE() support in case CONFIG_IOMMU_DMA
>> is enabled. The only current su
Hi Robin,
On Wed, Mar 8, 2017 at 9:48 PM, Robin Murphy wrote:
> On 07/03/17 03:17, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Not all architectures have an iommu member in their archdata, so
>> use #ifdefs support build with COMPILE_TEST on any architecture.
>
From: Magnus Damm
The r8a7795 IPMMU supports 40-bit bus mastering. Both
the coherent DMA mask and the streaming DMA mask are
set to unlock the 40-bit address space for coherent
allocations and streaming operations.
Signed-off-by: Magnus Damm
---
Changes since V2:
- Updated the code and
From: Magnus Damm
Hook up IOMMU_OF_DECLARE() support in case CONFIG_IOMMU_DMA
is enabled. The only current supported case for 32-bit ARM
is disabled, however for 64-bit ARM usage of OF is required.
Signed-off-by: Magnus Damm
---
Changes since V2:
- Reworked registration code to make use of
From: Magnus Damm
Write IMCTR both in the root device and the leaf node.
Signed-off-by: Magnus Damm
---
Changes since V2:
- None
Changes since V1:
- None
drivers/iommu/ipmmu-vmsa.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
--- 0018/drivers/iommu/ipmmu
From: Magnus Damm
Add support for up to 8 contexts. Each context is mapped to one
domain. One domain is assigned one or more slave devices. Contexts
are allocated dynamically and slave devices are grouped together
based on which IPMMU device they are connected to. This makes slave
devices tied
From: Magnus Damm
Introduce support for two bit SL0 bitfield in IMTTBCR
by using a separate feature flag.
Signed-off-by: Magnus Damm
---
Changes since V2:
- None
Changes since V1:
- None
drivers/iommu/ipmmu-vmsa.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion
From: Magnus Damm
Tie in r8a7795 features and update the IOMMU_OF_DECLARE
compat string to include the updated compat string.
TODO:
- Consider making use of iommu_fwspec_add_ids() for uTLB handling
Needed to coexist with non-OF R-Car Gen2 somehow...
- Break out stuff useful for R-Car
From: Magnus Damm
Introduce a feature to allow opt-out of setting up
IMBUSCR. The default case is unchanged.
Signed-off-by: Magnus Damm
---
Changes since V2:
- None
Changes since V1:
- Updated the commit message
- Reworked patch to coexist with the multi context feature
drivers/iommu
From: Magnus Damm
Add root device handling to the IPMMU driver by allowing certain
DT compat strings to enable has_cache_leaf_nodes that in turn will
support both root devices with interrupts and leaf devices that
face the actual IPMMU consumer devices.
Signed-off-by: Magnus Damm
---
Changes
From: Magnus Damm
Introduce struct ipmmu_features to track various hardware
and software implementation changes inside the driver for
different kinds of IPMMU hardware. Add use_ns_alias_offset
as a first example of a feature to control if the secure
register bank offset should be used or not
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