f one instruction it picks up
a next candidate. In single pass strategy it does not happen because CPU
doesn't trap on branch-compacts which share opcode space with BLEZL/BGTZL
(but has RT != 0, of course).
Signed-off-by: Leonid Yegoshin
Reported-by: Douglas Leung
---
arch/mips/kernel/mips-r2-to
Paul Burton wrote:
It is, however, used in such a way by others & seems to me like the only
correct way to implement the lazy cache flushing. The alternative would
be to adjust all generic code to ensure flush_icache_page gets called
before set_pte_at
... which is an exact case right now. Both
On 01/27/2016 03:26 AM, Maciej W. Rozycki wrote:
On Fri, 15 Jan 2016, Leonid Yegoshin wrote:
So you need to build a different kernel for some types of MIPS systems?
Or do you do boot-time rewriting, like a number of other arches do?
I don't know. I would like to have responses. Ralf
.
Signed-off-by: Leonid Yegoshin
---
arch/mips/mm/c-r4k.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5d3a25e1cfae..493f5226da10 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1670,7 +1670,7 @@ void
On 10/28/2015 12:55 PM, Alex Smith wrote:
On 28 October 2015 at 19:28, Leonid Yegoshin wrote:
.
Clocksources are not per-CPU. If the CP0 counter is the current
clocksource, then both the kernel and VDSO implementations of
gettimeofday will read out the CP0 counter from whatever CPU they run
On 10/28/2015 12:04 PM, Alex Smith wrote:
On 28 October 2015 at 18:57, Leonid Yegoshin wrote:
As I've explained the VDSO will only use the CP0 counter in the same
situations that the kernel would when it is the active clocksource.
Any issue that makes the counter unreliable affect
On 10/28/2015 11:30 AM, Alex Smith wrote:
On 28 October 2015 at 18:21, Leonid Yegoshin wrote:
1) I don't see that in code - there is no check that kernel uses actually uses
R4K clocksource as primary (A), and if kernel uses R4K count as a clocksource
and later switches to some more pr
On 10/28/2015 03:20 AM, Alex Smith wrote:
On 27 October 2015 at 20:46, Leonid Yegoshin wrote:
I believe, until this issue is fixed the R4K only CPU should be excluded
from VDSO timing acceleration.
The VDSO code will currently use the CP0 count whenever the kernel is
using it as its primary
For example, On OCTEON single-chip systems we synchronize the the
counters and they don't drift. So, we can use CPO.Count. However, on
two-chip NUMA configurations there may be clock drift between the two
chips, so CPO.Count cannot be used as a clocksource. We have a single
kernel image tha
On 10/27/2015 02:02 PM, David Daney wrote:
On 10/27/2015 01:46 PM, Leonid Yegoshin wrote:
[...]
And finally. clock scaling - what we would do if there are two CPUs with
different clock ratios in system? It seems like common kernel timing
subsystem can handle that.
The code that executes in
On 10/27/2015 07:47 AM, Ralf Baechle wrote:
On Thu, Oct 22, 2015 at 06:41:30PM -0700, Leonid Yegoshin wrote:
You can not use R4K CP0_count in SMP (multicore) without core-specific
adjustment.
After first power-saving with core clock off or core down the values in
CP0_count
in different cores
You can not use R4K CP0_count in SMP (multicore) without core-specific
adjustment.
After first power-saving with core clock off or core down the values in
CP0_count
in different cores are absolutely different.
Until you include in system a patch like
http://patchwork.linux-mips.org/patch/10871
On 10/20/2015 01:35 AM, Markos Chandras wrote:
What tree did you use for this patch? It does not seem to apply to
mainline or Ralf's upstream-sfr.
May I ask you to elaborate more and send me a concern details?
I definitely rebased it to mips-for-linux-next of upstream-sfr from LMO.
- Leonid
I mailed it from LMO 'upstream-sfr'.
I pulled it last week.
I will check it again.
- Leonid.
(introduced by v1).
Tested on all 3 ABIs.
--
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/signal.h | 12 +---
arch/mips/kernel/signal.c |2 +-
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm
MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
set to processing aka rt_sigaction() variant only.
Fixed.
--
v2: Taken in account CONFIG vars interdependencies and conditional expression
simplified. As a result, the reverse problem fixed (introduced by v1).
Teste
MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
set to processing aka rt_sigaction() variant only.
Fixed.
--
v2: Taken in account CONFIG vars interdependencies and conditional expression
simplified. As a result, the reverse problem fixed (introduced by v1).
Teste
On 10/16/2015 01:11 AM, Markos Chandras wrote:
On 10/15/2015 07:50 PM, Leonid Yegoshin wrote:
MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
set to processing aka rt_sigaction() variant only.
Fixed.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm
MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
set to processing aka rt_sigaction() variant only.
Fixed.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/signal.h | 15 ---
arch/mips/kernel/signal.c |2 +-
2 files changed, 13
MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
set to processing aka rt_sigaction() variant only.
Fixed.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/signal.h | 15 ---
arch/mips/kernel/signal.c |2 +-
2 files changed, 13
On 08/11/2015 07:41 AM, Markos Chandras wrote:
Hi,
On Wed, Aug 05, 2015 at 04:53:43PM -0700, Leonid Yegoshin wrote:
if (nir) {
err = mipsr6_emul(regs, nir);
if (err >
On 08/10/2015 12:19 PM, gre...@linuxfoundation.org wrote:
On Mon, Aug 10, 2015 at 12:12:05PM -0700, Leonid Yegoshin wrote:
On 08/10/2015 11:49 AM, gre...@linuxfoundation.org wrote:
On Mon, Aug 10, 2015 at 11:36:34AM -0700, Leonid Yegoshin wrote:
So, this is broken in Linus's tree too?
On 08/10/2015 11:49 AM, gre...@linuxfoundation.org wrote:
On Mon, Aug 10, 2015 at 11:36:34AM -0700, Leonid Yegoshin wrote:
So, this is broken in Linus's tree too?
Yes.
Or is it fixed there, and if
so, what is the git commit id?
There is no an accepted fix. My old patch is in
ange size.
Because of that reasons it is a separate patch from EVA support.
Signed-off-by: Leonid Yegoshin
Signed-off-by: Steven J. Hill
(cherry picked from commit 6b05dd71da1136fbad0ce642790c4c99343f05e7)
(history is skipped)
Note: the replacement of
if (config_ena
On 08/05/2015 05:37 PM, David Daney wrote:
This just means that your userspace is broken.
If GLibC cannot do the right thing then it should be fixed.
Let's skip this until you explain how to create a fully
non-executable-stack process. GLIBC people is ready to do something but
after we remov
On 08/05/2015 05:14 PM, David Daney wrote:
On 08/05/2015 05:06 PM, Leonid Yegoshin wrote:
On 08/05/2015 04:55 PM, Paul Burton wrote:
As was pointed out last time you posted this, it breaks backwards
compatibility with userland & thus cannot be applied.
Never observed since first ver
On 08/05/2015 04:55 PM, Paul Burton wrote:
As was pointed out last time you posted this, it breaks backwards
compatibility with userland & thus cannot be applied.
Never observed since first version.
In other side, the problem with apps like ssh_keygen is observed in
absence of executable st
On 08/05/2015 05:00 PM, David Daney wrote:
Does it handle nested emulation?
Yes, it does since v2:
"- Added unwinding of VDSO emulation stack at signal handler
invocation, hiding an emulation page (Andy Lutomirski note in other
patch comments)"
- Leonid.
--
To unsubscribe from this li
filling some emulation block
in stack or special area and jump to it. This is not suitable for PC-relative
instructions.
So, this patch introduces a universal emulation of that instructions directly by
kernel emulator.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/uapi/asm/inst.h | 42
page is flushed by flush_cache_page in ptrace().
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/cacheflush.h |3 +++
arch/mips/mm/c-octeon.c|8 +++
arch/mips/mm/c-r3k.c |8 +++
arch/mips/mm/c-r4k.c | 43
eeps stack non-executable but things fails at FPU emulation
later.
Here are two issues which are bind together and to solve an incorrect
behaviour of GLIBC (ignoring X ssh-keygen intention) the split of both issues
is needed. So, I did a kernel emulation protected and out of stack.
Signed-off-
This is a last step of 3 patches which shift FPU emulation out of
stack into protected area. So, it disables a default executable stack.
Additionally, it sets a default data area non-executable protection.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/page.h |2 +-
1 file
eemption friendly.
V4 changes:
- Fixed bug in supplementary TLB flush (change KVA to user address space)
- Rebased to 4.X kernel
---
Leonid Yegoshin (3):
MIPS: mips_flush_cache_range is added
MIPS: Setup an instruction emulation in VDSO protected page instead of
user stack
MIPS
On 06/10/2015 03:28 AM, Ralf Baechle wrote:
On Thu, May 28, 2015 at 01:37:24PM -0700, Leonid Yegoshin wrote:
...
I was wondering why there was a cache flush at all so I dove into git
history and found:
commit 4676f9359fa5190ee6f42bbf2c27d28beb14d26a
Author: Leonid Yegoshin
Date: Tue Jan
On 06/02/2015 04:56 PM, David Daney wrote:
On 06/02/2015 09:15 AM, Maciej W. Rozycki wrote:
On Tue, 2 Jun 2015, James Hogan wrote:
binutils appears to support the sync_mb, sync_rmb, sync_wmb aliases
since version 2.21. Can we safely use them?
I suggest that we don't -- we still officially
On 06/02/2015 04:39 AM, James Hogan wrote:
Hi Leonid,
On 02/06/15 01:09, Leonid Yegoshin wrote:
CPUs may occasionally have problems in accordance with HW team.
"have problems in accordance with HW team" is a bit confusing. What do
you mean?
I wrote about memory barriers and pr
On 06/02/2015 05:12 AM, Luc Van Oostenryck wrote:
On Tue, Jun 02, 2015 at 11:08:35AM +0100, Paul Burton wrote:
I think this would read better as something like:
If a processor does not implement the lightweight sync operations then
the architecture requires that they interpret the corres
uot; semantics.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/bitops.h |2 +-
arch/mips/include/asm/spinlock.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 0cf29bd5dc5c..ce9666cf1499 1006
only for MIPS R6 and other MIPS32/64 R2/R5 processors
have it configurable.
Signed-off-by: Leonid Yegoshin
---
arch/mips/Kconfig | 22 ++
arch/mips/include/asm/barrier.h |6 ++
2 files changed, 28 insertions(+)
diff --git a/arch/mips/Kconfig b/arch
5KEs has a pretty short pipeline.
Using memory barriers in MIPS R6 is mandatory, all that
processors have a speculative memory read which can inflict a trouble
without a correct use of barriers in LL-SC loop cycles.
The same is actually for MIPS32 R5 I5600 processor.
Signed-off-by: Leonid Yegoshin
wever, it is considered safe do not implement
some or any lightweight SYNC in specific core because Architecture requires
HW map of unimplemented SYNCs to SYNC 0.
---
Leonid Yegoshin (3):
MIPS: R6: Use lightweight SYNC instruction in smp_* memory barriers
MIPS: enforce LL-SC loop encl
This function is used to flush code used in NMI and EJTAG debug exceptions.
However, during that exceptions the Status.ERL bit is set, which means
that code runs as UNCACHABLE. So, flush code down to memory is needed.
Signed-off-by: Leonid Yegoshin
---
arch/mips/mm/c-r4k.c | 10 +-
1
On 05/22/2015 04:20 PM, Ralf Baechle wrote:
On Fri, May 22, 2015 at 11:37:34AM -0700, Leonid Yegoshin wrote:
On 05/22/2015 02:38 AM, Ralf Baechle wrote:
Just move the call to finish_arch_switch().
It might be a problem later, then a correct MSA partiton starts working. It
should be tight to
Ralf,
If there was TIF_USEDMSA in "prev" task then it means that all MSA HW is
in use.
And switch_to() checks this and transfers it to resume() to indicate
that MSA processing should be done.
Macro call "msa_save_alla0" right before disabling MSA in Config5
does a save of MSA registers.
On 05/22/2015 02:38 AM, Ralf Baechle wrote:
Just move the call to finish_arch_switch().
It might be a problem later, then a correct MSA partiton starts working.
It should be tight to saving MSA registers in that case.
Your rewrite also dropped the if (cpu_has_msa) condition from
disable_msa
Yes, I have a program but it is binary only.
If you want to understand why disable_DMA() after resume() doesn't work,
search for restoring RA register in resume() after changing SP.
- Leonid.
Paul Burton wrote:
On Tue, May 19, 2015 at 02:13:51PM -0700, Leonid Yegoshin wrote:
> Durin
Cancel this, please.
Reason - MSA registers are not supposed to be preserved through
caller-called interface, including syscall.
In other side, keeping MSA context is expensive.
- Leonid.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to ma
in team, I guess.
Well, in this case it should prevent clearing TIF_MSA_CTX_LIVE in copy_thread().
Signed-off-by: Leonid Yegoshin
---
arch/mips/kernel/process.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index f2975d4d1e44..a16e62d40
e_msa' after 'resume' in 'switch_to'
macro never called a first time entry into thread.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/switch_to.h |1 -
arch/mips/kernel/r4k_switch.S |6 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --
Two bug fixes of MSA registers set handling during context switch.
This fixes are respones to multithreading MSA application crash.
It was traced to incorrect handling of MSA registers set during
thread cloning. See inside.
---
Leonid Yegoshin (2):
MIPS: MSA: bugfix - disable MSA during
On 05/15/2015 02:53 PM, Ralf Baechle wrote:
On Thu, May 14, 2015 at 06:34:43PM -0700, Leonid Yegoshin wrote:
The order 1 allocation for the PGD are concerning me a little. On a
system under even moderate memory pressure that might become a bit of
a reliability or performance issue.
With 4kB
On 05/15/2015 01:49 PM, David Daney wrote:
On 05/14/2015 06:34 PM, Leonid Yegoshin wrote:
SEGBITS default is 40 bits or less, depending from CPU type.
This patch introduces 48bits of application virtual address (SEGBITS)
support.
It is defined only for 16K and 64K pages and is optional
On 05/15/2015 09:28 AM, David Daney wrote:
On 05/14/2015 06:34 PM, Leonid Yegoshin wrote:
SEGBITS default is 40 bits or less, depending from CPU type.
This patch introduces 48bits of application virtual address (SEGBITS) support.
It is defined only for 16K and 64K pages and is optional
for 64K pages it adds 3rd level of PTE structure, which has a little
impact during software TLB refill.
This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
virtual address in each segment (SEGBITS).
Signed-off-by: Leonid Yegoshin
---
V2: Added correction for defintion of
for 64K pages it adds 3rd level of PTE structure, which has a little
impact during software TLB refill.
This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
virtual address in each segment (SEGBITS).
Signed-off-by: Leonid Yegoshin
---
arch/mips/Kconfig | 10
ned-off-by: Leonid Yegoshin
---
arch/mips/mm/dma-default.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 609d1241b0c4..ccf49ecfbf8c 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
On 05/13/2015 02:47 PM, David Daney wrote:
On 05/13/2015 11:55 AM, Leonid Yegoshin wrote:
Originally, it was set to 40bits only but I6400 has 48bits of physaddr.
Why not go to the architectural limit of 59 bits?
Because any physaddr should fit PTE and EntryLo register and we also
need 5
Originally, it was set to 40bits only but I6400 has 48bits of physaddr.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/addrspace.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index
On 04/29/2015 02:49 AM, Maciej W. Rozycki wrote:
On Wed, 29 Apr 2015, James Hogan wrote:
Error recovery pointers for fixups was improperly set as ".word"
which is unsuitable for MIPS64.
Replaced by __stringify(PTR)
Every other case of this sort of thing uses STR(PTR) (or __UA_ADDR in
uaccess.
Error recovery pointers for fixups was improperly set as ".word"
which is unsuitable for MIPS64.
Replaced by __stringify(PTR)
Signed-off-by: Leonid Yegoshin
---
arch/mips/kernel/mips-r2-to-r6-emul.c | 104 +
1 file changed, 52 insertions(+), 52
You right,
I am debugging new core and got a wrong backtrace.
Please cancel it, sorry for noise.
- Leonid.
Jonas Gorski wrote:
Hi,
On Tue, Apr 28, 2015 at 1:35 AM, Leonid Yegoshin
wrote:
> MIPS R6 version of memcpy has bug - then length to copy is zero
> and addresses are not a
MIPS R6 version of memcpy has bug - then length to copy is zero
and addresses are not aligned then it can overwrite a whole memory.
Signed-off-by: Leonid Yegoshin
---
arch/mips/lib/memcpy.S |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
On 03/19/2015 02:51 AM, James Hogan wrote:
On 18/03/15 23:25, Leonid Yegoshin wrote:
On 03/18/2015 03:12 PM, James Hogan wrote:
Hi Leonid,
On Wed, Mar 18, 2015 at 12:46:51PM -0700, Leonid Yegoshin wrote:
thread_msa_context_live() == check of TIF_MSA_CTX_LIVE == existence of
MSA context for
On 03/18/2015 03:12 PM, James Hogan wrote:
Hi Leonid,
On Wed, Mar 18, 2015 at 12:46:51PM -0700, Leonid Yegoshin wrote:
thread_msa_context_live() == check of TIF_MSA_CTX_LIVE == existence of
MSA context for thread.
It differs from MSA is owned by thread, it just says that thread has
already
Confirmed - your fix solves TX problem in kernel.
- Leonid.
On 03/18/2015 10:34 AM, Leonid Yegoshin wrote:
Thank you, Markos!
It seems like one Samurai problem may be solved by your work -
right now I experience TX problem while I use NFS root.
Will test today.
- Leonid.
Markos Chandras
On 03/18/2015 04:27 AM, James Hogan wrote:
+ .align 4
doesn't this mean the first one & label might not be suitably aligned.
Would it be better to put this before the ld_d (no need for it after
$w31 case) and putting another .align 4 before the Lmsa_to and Lmsa_from
labels (so the label i
ead still owns MSA unit then it
loads and stores directly with MSA unit and only one MSA register. Saving
and restoring the full MSA context (512bytes) on each misalign exception
is expensive! Preemption is disabled, of course.
Signed-off-by: Leonid Yegoshin
---
V2:
- added a missed assignment
ead still ownes MSA unit then it
loads and stores directly with MSA unit and only one MSA register. Saving
and restoring the full MSA context (512bytes) on each misalign exception
is expensive! Preemption is disabled, of course.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/processo
On 02/14/2015 09:26 AM, Paul Bolle wrote:
Your commit 33d73a3d4159 ("MIPS: lib: memset: Add MIPS R6 support") is
included in yesterday's linux next (ie, next-20150213). I noticed
because a script I use to check linux-next spotted a trivial problem
with it.
It added a reference to CONFIG_CPU_MIPS
On 02/14/2015 09:21 AM, Paul Bolle wrote:
Your commits 430857eae56c ("MIPS: mm: Add MIPS R6 instruction
encodings") and 90163242784b ("MIPS: kernel: unaligned: Add support for
the MIPS R6") are included in yesterday's linux-next (ie,
next-20150213). I noticed because a script I use to check linux
On 01/30/2015 09:23 PM, Guenter Roeck wrote:
Commit bcd022801ee5 ("MIPS: Fix COW D-cache aliasing on fork") replaced
the inline function copy_user_page for mips with an external reference,
but neglected to introduce the actual non-inline function. Restore it.
Fixes: bcd022801ee5 ("MIPS: Fix COW
Is it a New Year joke?
Did you try to build vmlinux MIPS binary?
- Leonid
.
- Lars
On Fri, 2014-12-05 at 03:16 +0100, Leonid Yegoshin wrote:
(repeat mesg, first one went to wrong place)
Lars,
Do you have a stack trace or so then you found the second VPE between
set_pte_at and update_mmu_cache?
It would be interesting how it happens - generally, to get a consistent
SIGILL
On 12/05/2014 11:06 AM, David Daney wrote:
On 12/05/2014 10:51 AM, Kees Cook wrote:
On Fri, Dec 5, 2014 at 9:28 AM, David Daney
wrote:
Some programs require an executable stack, this patch will break them.
Have you tested this?
Do you require empirical evidence that the patch is incorrect
bug
in FS is not enough.
Hold on - do you use non-DMA file system?
If so, I advice you to try this simple patch:
Author: Leonid Yegoshin
Date: Tue Apr 2 14:20:37 2013 -0700
MIPS: (opt) Fix of reading I-pages from non-DMA FS devices for ID
cache separation
This optional
On 12/03/2014 04:20 PM, David Daney wrote:
On 12/03/2014 03:55 PM, Leonid Yegoshin wrote:
On 12/03/2014 03:44 PM, David Daney wrote:
(...)
Big work
Not really, although by number of lines of code, it is about 3x the
size of your patch, it only touches the existing code in one place.
It
On 12/03/2014 03:44 PM, David Daney wrote:
(...)
Big work but it doesn't support customized instructions, multiple ASEs,
MIPS R6 etc.
Well, it is still not a replacement of XOL emulation.
Even close.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a
use non-DMA file system?
If so, I advice you to try this simple patch:
Author: Leonid Yegoshin
Date: Tue Apr 2 14:20:37 2013 -0700
MIPS: (opt) Fix of reading I-pages from non-DMA FS devices for ID
cache separation
This optional fix provides a D-cache flush for instruction code
pages
en that problem on 3.10 kernel.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/pgtable.h |8 +---
arch/mips/mm/cache.c| 27 ---
2 files changed, 13 insertions(+), 22 deletions(-)
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/as
page is flushed by flush_cache_page in ptrace().
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/cacheflush.h |3 +++
arch/mips/mm/c-octeon.c|8 +++
arch/mips/mm/c-r3k.c |8 +++
arch/mips/mm/c-r4k.c | 43
eeps stack non-executable but things fails at FPU emulation
later.
Here are two issues which are bind together and to solve an incorrect
behaviour of GLIBC (ignoring X ssh-keygen intention) the splitting both issues
is needed. So, I did a kernel emulation protected and out of stack.
Signed-off-
This is a last step of 3 patches which shift FPU emulation out of
stack into protected area. So, it disables a default executable stack.
Additionally, it sets a default data area non-executable protection.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/page.h |2 +-
1 file
thread is rescheduled and other threads don't intervene (Peter Zijlstra)
- Fixed uMIPS support (Paul Burton)
- Added unwinding of VDSO emulation stack at signal handler invocation,
hiding an emulation page (Andy Lutomirski note in other patch comments)
V3 change: heavy preemption f
On 10/30/2014 03:07 AM, James Hogan wrote:
Hi Leonid,
On 30/10/14 01:48, Leonid Yegoshin wrote:
A default dma_alloc_coherent() fails to alloc a coherent memory on non-coherent
systems in case of device->coherent_dma_mask covering the whole memory space.
In case of non-coherent systems
DMA.
Added __GFP_DMA flag in case of non-coherent systems to enforce an allocation
of coherent memory in ZONE_DMA.
Signed-off-by: Leonid Yegoshin
---
.../include/asm/mach-cavium-octeon/dma-coherence.h |2 +-
arch/mips/include/asm/mach-generic/dma-coherence.h |2 +-
arch/mips/include/asm/m
On 10/10/2014 03:56 PM, David Daney wrote:
> Right, look at uprobes, it does exactly all this with a single page.
> Slot allocation will block waiting for a free slot when all are in
use.
I don't see a reason to change my 300 lines design into much more
lengthy code. That code has more lin
On 10/10/2014 03:03 AM, James Hogan wrote:
I just mean an (illegal/undefined) sequence of FPU branch instructions
in one anothers delay slots shouldn't be able to crash the kernel.
Actually 2 of them would be enough to verify the kernel didn't get too
confused. Maybe the second will be detected
On 10/09/2014 04:40 PM, James Hogan wrote:
It may be a case for mix of FPU and MIPS R6 emulations. I just keep both
emulators separate as much as possible but I assume that without prove
it may be stackable - some rollback is needed to join both and it may
(probably) cause a double emulation se
On 10/09/2014 03:59 PM, David Daney wrote:
Note: actual execute-protection depends from HW capability, of course.
This patch is required for MIPS32/64 R2 emulation on MIPS R6
architecture.
Without it 'ssh-keygen' crashes pretty fast on attempt to execute
instruction
in stack.
There is muc
Small stack of emulation blocks is supported because nested traps are possible
in MIPS32/64 R6 emulation mix with FPU emulation.
Could you please clarify how this nesting of emulation blocks could
happen now that signals are handled more cleanly.
I.e. isn't the emuframe stuff only required for i
On 10/09/2014 02:42 PM, David Daney wrote:
On 10/09/2014 01:00 PM, Leonid Yegoshin wrote:
The following series implements an executable stack protection in MIPS.
It sets up a per-thread 'VDSO' page and appropriate TLB support.
Page is set write-protected from user and is maintained
This is a last step of 3 patches which shift FPU emulation out of
stack into protected area. So, it disables a default executable stack.
Additionally, it sets a default data area non-executable protection.
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/page.h |2 +-
1 files
eeps stack non-executable but things fails at FPU emulation
later.
Here are two issues which are bind together and to solve an incorrect
behaviour of GLIBC (ignoring X ssh-keygen intention) the splitting both issues
is needed. So, I did a kernel emulation protected and out of stack.
Signed-off-
page is flushed by flush_cache_page in ptrace().
Signed-off-by: Leonid Yegoshin
---
arch/mips/include/asm/cacheflush.h |3 +++
arch/mips/mm/c-octeon.c|8 +++
arch/mips/mm/c-r3k.c |8 +++
arch/mips/mm/c-r4k.c | 43
thread is rescheduled and other threads don't intervene (Peter Zijlstra)
- Fixed uMIPS support (Paul Burton)
- Added unwinding of VDSO emulation stack at signal handler invocation,
hiding an emulation page (Andy Lutomirski note in other patch comments)
---
L
On 10/07/2014 12:21 PM, Rich Felker wrote:
The in-stack trampoline support could be left but used only for
emulating instructions the kernel doesn't know. This would make all
normal binaries immediately usable with non-executable stack, and
would avoid the only potential source of regressions.
On 10/07/2014 12:09 PM, Rich Felker wrote:
I agree completely here. We should not break things (or, as it seems,
leave them broken) for common usage cases that affect everyone just to
coddle proprietary vendor-specific instructions. The latter just
should not be used in delay slots unless the c
(repeat it because of some e-mail failure, sorry)
On 10/07/2014 11:43 AM, David Daney wrote:
Five lines per instruction.
But you must be able to emulate them, so you need an emulator, not XOL.
I feel I didn't say clear - emulation of ADDIUPC (after second look it
is the only instruction requ
Well, I am not a subscriber to mail-list, so I read it the first time
and some notes:
1) David's approach would likely work for FPU emulation but unlikely
works for MIPS Rel 2/Rel 1/ MIPS I emulation in MIPS R6 architecture.
The reason is that the first MIPS R2 instruction (removed from MIPS
On 10/06/2014 05:29 AM, Paul Burton wrote:
First some general questions: is there any reason to need the page used
to be at the same virtual address for each thread? I can't think of one,
and if that's the case then why not simply allocate a series of pages
per-thread via mmap_region or similar
1 - 100 of 119 matches
Mail list logo
