to resolve the issue.
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
lpers for creating the IRQ domain, the
gpio_irq_chip structure is now filled by the driver itself and then
gpiochip_add_data() takes care of instantiating the IRQ domain for us.
Suggested-by: Andy Shevchenko
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
noisy warning). Hence let's return the error code directly
instead of overriding it with -ENODEV.
Suggested-by: Andy Shevchenko
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
rrects the parent's device pointer and removes the
unnecessary setting of the of_node.
Suggested-by: Andy Shevchenko
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
: Fix interrupt handling")
Signed-off-by: Dmitry Osipenko
Looks good to me.
Acked-by: Laxman Dewangan
d-by: Andy Shevchenko
Looks good to me.
Acked-by: Laxman Dewangan
Bitan Biswas
Acked By: Laxman Dewangan
Thanks,
Laxman
resend them
anymore, you can focus on the remaining patches now.
Question: The nominal maintainer for this driver is
Laxman Dewangan (supporter:TEGRA I2C DRIVER)
I wonder if he is still around and interested?
That aside, thanks a lot Dmitry for the review of this series!
Most of patches
struct rc5t583_regulator.
Signed-off-by: Axel Lin
Acked-by: Laxman Dewangan
On Wednesday 27 March 2019 06:59 AM, Axel Lin wrote:
Add a local variable *desc to avoid too many change lines due to over 80
characters.
Signed-off-by: Axel Lin
Acked-by: Laxman Dewangan
On Wednesday 27 March 2019 06:59 AM, Axel Lin wrote:
Use regulator_set/get_current_limit_regmap helpers to save some code.
Signed-off-by: Axel Lin
Acked-by: Laxman Dewangan
ete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.
Cc: Lee Jones
Cc: Laxman Dewangan
Signed-off-by: Paul Gortmaker
Acked-by: Linus Walleij
Acked-by: Laxman Dewangan
no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.
Cc: Lee Jones
Cc: Laxman Dewangan
Signed-off-by: Paul Gortmaker
Acked-by: Linus Walleij
Acked-by: Laxman Dewangan
On Monday 19 November 2018 10:44 PM, Tony Lindgren wrote:
Hi,
* Tony Lindgren [181119 16:19]:
* Peter Ujfalusi [181119 10:16]:
On 2018-11-13 20:06, Tony Lindgren wrote:
Looks like the IRQ_TYPE_NONE issue still is there for omap5 and
should be fixed with IRQ_TYPE_HIGH.
No idea about why
cros instead
of enum.
Acked-by: Laxman Dewangan
e reset_control_assert/deassert from the tegra_i2c_init(). So I'd go for
a complete suspend/resume removal for now as it is causes problem.
Laxman, are you convinced or do you have still objections?
Fine with me. Please add my Ack
Acked-by: Laxman Dewangan
On Monday 14 May 2018 05:29 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, May 14, 2018 at 12:13:47AM +0300, Dmitry Osipenko wrote:
Nothing prevents I2C clients to access I2C while Tegra's driver is being
suspended, this results in -EBUSY error returned to the clients and th
On Thursday 08 March 2018 08:01 PM, Guenter Roeck wrote:
On 03/07/2018 10:06 PM, Laxman Dewangan wrote:
The RPM is measured speed via PWM signal capture which is output
from fan.
So should we have the fan[1..n]_output_rpm?
No. I hear you clearly that you for some reason dislike fan[1
On Wednesday 07 March 2018 07:50 PM, Guenter Roeck wrote:
On 03/07/2018 01:47 AM, Rajkumar Rampelli wrote:
While I am not opposed to ABI changes, the merits of those would
need to be
discussed on the mailing list. But replacing "fan1_input" with "rpm" is
not an acceptable ABI change, even
On Tuesday 06 March 2018 05:23 AM, Gustavo A. R. Silva wrote:
Assign true or false to boolean variables instead of an integer value.
This issue was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva
Acked-by: Laxman Dewangan
On Wednesday 07 February 2018 09:07 PM, Mark Brown wrote:
On Wed, Feb 07, 2018 at 05:20:45PM +0200, Peter De Schrijver wrote:
On Wed, Feb 07, 2018 at 03:01:55PM +, Mark Brown wrote:
I can't really tell what you're saying here. If the driver needs to
know if it can set the a given voltage
On Friday 08 December 2017 01:49 AM, SF Markus Elfring wrote:
From: Markus Elfring
Date: Thu, 7 Dec 2017 21:00:05 +0100
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Acked-by: Laxman Dewangan
On Friday 08 December 2017 01:51 AM, SF Markus Elfring wrote:
From: Markus Elfring
Date: Thu, 7 Dec 2017 21:06:25 +0100
Delete a duplicate character in a word of this description.
Acked-by: Laxman Dewangan
-devm version of thermal_zone_of_sensor_register().
Now the devm_iio_channel_get() is available, do the corresponding change in
this driver and remove gadc_thermal_remove().
Acked-by: Laxman Dewangan
Thanks,
Laxman
On Wednesday 19 July 2017 06:55 PM, Johan Hovold wrote:
On Fri, Apr 07, 2017 at 12:25:49PM +0200, Linus Walleij wrote:
On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as
On Tuesday 02 May 2017 11:13 PM, Laxman Dewangan wrote:
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
On 02/05/17 15:05, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 38.4MHz.
In
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
On 02/05/17 15:05, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 38.4MHz.
In Tegra186, it is 102MHz.
Add support to limit the
SoC chipdata.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Set the 48MHz maximum frequency for Tegra210 and earlier.
- Set the maximum frequency unconditionally as per V1 review comment.
---
drivers/pwm/pwm-tegra.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
d
On Tuesday 02 May 2017 12:07 AM, Matthias Kaehlcke wrote:
Some regulators have different settling times for voltage increases and
decreases. Add DT properties to define separate settling times for up-
and downward voltage changes.
Signed-off-by: Matthias Kaehlcke
---
Acked-by: Laxman
---
Acked-by: Laxman Dewangan
On Saturday 29 April 2017 05:36 AM, Matthias Kaehlcke wrote:
Some regulators have different settling times for voltage increases and
decreases. To avoid a time penalty on the faster transition extend the
settling time property to allow for different settings for upward and
downward transitions.
: Venkat Reddy Talla
Signed-off-by: Fengguang Wu
---
LGTM,
Acked-by: Laxman Dewangan
On Thursday 13 April 2017 08:57 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 13, 2017 at 07:40:28PM +0530, Laxman Dewangan wrote:
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
For Tegra210, it is 38.4MHz
SoC chipdata.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 8c6ed55..7016c08 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -4
avoiding the clock call for getting clock rate
in the pwm_config() each time.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index c040f87..8c6ed55 100644
--- a
On Friday 07 April 2017 03:55 PM, Linus Walleij wrote:
On Thu, Apr 6, 2017 at 3:35 PM, Laxman Dewangan wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active HIGH
lator devices
require the PWM output to be tristated.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use standard pinctrl names for sleep and active state.
- Use API pinctrl_pm_se
lator devices
require the PWM output to be tristated.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use standard pinctrl names for sleep and active
old formula:
hz = 59, rate = 3390
Based on new formula:
hz = 5951, rate = 3360
The PWM signal rate of 3360 is more near to requested period than .
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- None
Changes from V2:
- Fix the commit
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closest one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- None
Changes from V2:
- Fix typo in commit message.
---
drivers/pwm/pwm-tegra.c | 3 +--
1 file
pinctrl_pm_select_*()
Changes from V2:
- Type fixes, rephrases commit message and use pinctrl_pm_state* return
value.
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
implementation
pwm: tegra: Increase precision in pwm rate calculation
pwm: tegra: Add DT
On Thursday 06 April 2017 09:40 PM, Andy Shevchenko wrote:
On Thu, Apr 6, 2017 at 4:35 PM, Laxman Dewangan wrote:
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active
On Thursday 06 April 2017 08:56 PM, Jon Hunter wrote:
On 06/04/17 15:21, Laxman Dewangan wrote:
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decid
Oops, it was actually v2.
On Thursday 06 April 2017 08:47 PM, Jon Hunter wrote:
On 06/04/17 15:21, Laxman Dewangan wrote:
In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where
pinctrl_pm_select_*()
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
implementation
pwm: tegra: Increase precision in pwm rate calculation
pwm: tegra: Add DT binding details to configure pin in suspends/resume
pwm: tegra: Add support to configure pin state in
formula:
hz = 60, rate =
Based on new formula:
hz = 5951, rate = 3360
The rate of 3360 is more near to requested period then the .
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- None
drivers/pwm/pwm-tegra.c | 8 ++--
1 file
also define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use standard pinctrl names for slee
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
None
drivers/pwm/pwm-tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers
also define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan
---
Changes from v1:
- Use sta
only when Single ended flag is enabled.
Signed-off-by: Laxman Dewangan
---
drivers/gpio/gpiolib-of.c | 2 +-
drivers/gpio/gpiolib.c | 4 +++-
include/dt-bindings/gpio/gpio.h | 12
include/linux/of_gpio.h | 1 +
4 files changed, 13 insertions(+), 6 deletions
On Thursday 06 April 2017 06:33 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Apr 06, 2017 at 09:57:09AM +0100, Jon Hunter wrote:
On 05/04/17 15:13, Laxman Dewangan wrote:
+state of the system. The configuration of pin is provided via the pinctrl
+DT node as detailed in
This patch series have following fixes:
- Add more precession in PWM period register value calculation
for lower pwm frequency.
- Add support to configure PWM pins in different state in the
suspend/resume.
Laxman Dewangan (4):
pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
Use macro DIV_ROUND_CLOSEST_ULL() for 64bit division to closet one
instead of implementing the same locally. This increase readability.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-tegra.c b
formula:
hz = 60, rate =
Based on new formula:
hz = 5951, rate = 3360
The rate of 3360 is more near to requested period then the .
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c | 8 ++--
1 file changed, 6 insertions(+), 2
also define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: Laxman Dewangan
---
drivers/pwm/pwm-tegra.c
also define
one of the state of PWM regulator which needs to be configure in
suspend state of system.
Add DT binding details to provide the pin configuration state
from PWM and pinctrl DT node in suspend and active state of
the system.
Signed-off-by: Laxman Dewangan
---
.../devicetree/binding
settling time.
Signed-off-by: Laxman Dewangan
---
This patch is continuation of discussion on patch
regulator: pwm: Fix regulator ramp delay for continuous mode
https://patchwork.kernel.org/patch/9216857/
where is it discussed to have separate property for PWM which has
exponential voltage
Some regulators (some PWM regulators) have the voltage transition
exponentially. On such cases, the settling time for voltage change
is treated as constant time.
Add DT property for providing the settling time for any level of
voltage change for non-linear voltage change.
signed-off-by: Laxman
igned-off-by: Olliver Schinagl
---
Adding Shardar for verifications.
Acked-by: Laxman Dewangan
On Thursday 12 January 2017 11:05 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Jan 12, 2017 at 10:06:24PM +0530, Laxman Dewangan wrote:
On Thursday 12 January 2017 09:45 PM, Thierry Reding wrote:
+ dev_dbg(&pdev->dev, "event recorder: %
On Thursday 12 January 2017 09:45 PM, Thierry Reding wrote:
From: Thierry Reding
The Maxim MAX77620 PMIC has the ability to power off and restart the
system. Add a driver that supports power off (via pm_power_off()) and
restart (via arm_pm_restart() on 32-bit and 64-bit ARM).
Based on work by
me also review the max77620 on similar cleanups.
Acked-by: Laxman Dewangan
On Monday 28 November 2016 02:56 PM, Jon Hunter wrote:
On 25/11/16 17:49, Laxman Dewangan wrote:
In the above dpaux driver, you used the pinctrl framework and its core
functionality for the device tree interfacing and client interfacing.
The same thing I am saying here, we should not avoid
On Friday 25 November 2016 10:59 PM, Jon Hunter wrote:
On 25/11/16 12:04, Laxman Dewangan wrote:
Thanks Thierry for review.
On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote
On Friday 25 November 2016 10:56 PM, Jon Hunter wrote:
On 25/11/16 09:57, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
...
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c
b/drivers/pinctrl/tegra/pinctrl
On Thursday 24 November 2016 08:38 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 08:14:31PM +0530, Laxman Dewangan wrote:
This has nothing to do with the device tree binding. What the device
tree binding defines is the indices to use to obtain a given GPIO
Thanks Thierry for review.
On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
+ NVIDIA Tegra124/210 SoC has IO pads which supports multi-voltage
+ level of interfacing and
On Friday 25 November 2016 02:43 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:53PM +0530, Laxman Dewangan wrote:
+
+The DT property of the IO pads must be under the node of pmc i.e.
+pmc@7000e400 for Tegra124 onwards.
The PMC is at a different
On Thursday 24 November 2016 08:14 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 12:23:56PM +0530, Laxman Dewangan wrote:
On Tuesday 22 November 2016 11:25 PM, Thierry Reding wrote:
+static inline struct tegra_gpio *to_tegra_gpio(struct gpio_chip *chip
On Thursday 24 November 2016 07:41 PM, Linus Walleij wrote:
On Wed, Nov 23, 2016 at 12:42 PM, Laxman Dewangan wrote:
Here, we need the regulator handle which can support the other regulator
APIs.
In some of platforms, we do not use some of the io-pins and on this case, we
do not connect the
can be static and dynamic.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Dropped the custom properties to set pad voltage and use regulator.
- Added support for regulator to get vottage in boot and configure IO
pad voltage.
- Add support for callback to handle regulator notification
on as per review comment from
V2.
Changes from V3:
Use devm_regulator_get() instead of devm_regulator_get_optional().
Laxman Dewangan (2):
pinctrl: tegra: Add DT binding for io pads control
pinctrl: tegra: Add driver to configure voltage and power of io pads
.../bindings/pinctrl/nvidia,
from SoC and hence SW need to configure the PMC
register explicitly to set proper voltage in IO pads based on
IO rail power source voltage.
Add DT binding document for detailing the DT properties for
configuring IO pads voltage levels and its power state.
Signed-off-by: Laxman Dewangan
On Tuesday 22 November 2016 11:25 PM, Thierry Reding wrote:
+static inline struct tegra_gpio *to_tegra_gpio(struct gpio_chip *chip)
+{
+ return container_of(chip, struct tegra_gpio, gpio);
+}
You dont need this as gpiochip_get_data(chip); can provide the required
driver specific data.
On Thursday 24 November 2016 01:10 AM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Nov 23, 2016 at 02:25:51PM +0100, Linus Walleij wrote:
This is already possible and several drivers are doing this.
Everything, all kernel users and all character device users, end up
calling
On Tuesday 22 November 2016 06:28 PM, Linus Walleij wrote:
On Tue, Nov 22, 2016 at 11:20 AM, Laxman Dewangan wrote:
+ rinfo->regulator = devm_regulator_get_optional(dev,
+ soc_data->cfg[i].vsupply);
Please ju
settling time.
Signed-off-by: Laxman Dewangan
CC: Douglas Anderson
CC: Aleksandr Frid
---
This patch is continuation of discussion on patch
regulator: pwm: Fix regulator ramp delay for continuous mode
https://patchwork.kernel.org/patch/9216857/
where is it discussed to have separate property for
Some regulators (some PWM regulators) have the voltage transition
exponentially. On such cases, the settling time for voltage change
is treated as constant time.
Add DT property for providing the settling time for any level of
voltage change for non-linear voltage change.
Signed-off-by: Laxman
Thierry,
On Wednesday 09 November 2016 06:39 PM, Laxman Dewangan wrote:
Tegra SoC support the configutaion of IO pads to multi-level voltage
and low power state. The conifguration is done via pictrl framework
and the io pad driver in pinctrl frameowrk uses the APIs from pmc to
access PMC
from SoC and hence SW need to configure the PMC
register explicitly to set proper voltage in IO pads based on
IO rail power source voltage.
Add DT binding document for detailing the DT properties for
configuring IO pads voltage levels and its power state.
Signed-off-by: Laxman Dewangan
can be static and dynamic.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
- Dropped the custom properties to set pad voltage and use regulator.
- Added support for regulator to get vottage in boot and configure IO
pad voltage.
- Add support for callback to handle regulator notification
on as per review comment from
V2.
Laxman Dewangan (2):
pinctrl: tegra: Add DT binding for io pads control
pinctrl: tegra: Add driver to configure voltage and power of io pads
.../bindings/pinctrl/nvidia,tegra-io-pad.txt | 126 +
drivers/pinctrl/tegra/Kconfig
On Tuesday 22 November 2016 03:15 PM, Joe Perches wrote:
On Tue, 2016-11-22 at 13:45 +0530, Laxman Dewangan wrote:
On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote:
On 09/11/16 13:06, Laxman Dewangan wrote:
+ _entry_(32, "uart", UART, true, &
On Monday 21 November 2016 09:47 PM, Rob Herring wrote:
On Fri, Nov 18, 2016 at 08:05:55PM +0530, Laxman Dewangan wrote:
Some PWM regulator has the exponential transition in voltage change as
opposite to fixed slew-rate linear transition on other regulators.
For such PWM regulators, add the
On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote:
On 09/11/16 13:06, Laxman Dewangan wrote:
+ _entry_(32, "uart", UART, true, "vddio-uart"), \
+ _entry_(33, "usb0", USB0, true, NULL),\
+ _entry
On Tuesday 22 November 2016 02:07 AM, Jon Hunter wrote:
On 21/11/16 12:49, Laxman Dewangan wrote:
On Monday 21 November 2016 04:38 PM, Jon Hunter wrote:
I had a discussion with the ASIC on this and as per them
1.8 V nominal is (1.62V, 1.98V)
3.3 V nominal is (2.97V,3.63V)
I am
On Monday 21 November 2016 04:38 PM, Jon Hunter wrote:
I had a discussion with the ASIC on this and as per them
1.8 V nominal is (1.62V, 1.98V)
3.3 V nominal is (2.97V,3.63V)
I am working with them to update the TRM document but we can assume that
this information will be there in TR
Hi Jon,
I will update the patch per your comment.
Here is answer for some of the query.
Thanks,
Laxman
On Tuesday 15 November 2016 08:37 PM, Jon Hunter wrote:
On 09/11/16 13:06, Laxman Dewangan wrote:
+/**
+ * Macro for 1.8V, keep 200mV as tolerance for deciding that
+ * IO pads should be
On Wednesday 16 November 2016 12:18 AM, Jon Hunter wrote:
On 09/11/16 13:06, Laxman Dewangan wrote:
+NVIDIA Tegra124 and later SoCs support the multi-voltage level and
+low power state of some of its IO pads. When IO interface are not
+used then IO pads can be configure in low power state to
Some PWM regulator has the exponential transition in voltage change as
opposite to fixed slew-rate linear transition on other regulators.
For such PWM regulators, add the property to tell that voltage change
is exponential and having fixed delay for any level of change.
Signed-off-by: Laxman
Some PWM regulator has the exponential transition in voltage change
as opposite to fixed slew-rate linear transition on other regulators.
For such PWM regulators, add support for handling the exponential
voltage ramp delay.
Signed-off-by: Laxman Dewangan
CC: Douglas Anderson
CC: Aleksandr Frid
On Tuesday 15 November 2016 07:57 PM, Rob Herring wrote:
On Tue, Nov 15, 2016 at 5:42 AM, Laxman Dewangan wrote:
On Monday 14 November 2016 09:18 PM, Rob Herring wrote:
On Fri, Nov 04, 2016 at 11:07:54PM +0530, Laxman Dewangan wrote:
regulator
+- pwm-regulator-voltage-ramp-time-us
On Tuesday 15 November 2016 01:04 AM, Rob Herring wrote:
On Wed, Nov 09, 2016 at 06:36:21PM +0530, Laxman Dewangan wrote:
+
+ audio {
+ pins = "audio", "dmic", "sdmmc3";
What's the purpose of grouping the
On Monday 14 November 2016 09:18 PM, Rob Herring wrote:
On Fri, Nov 04, 2016 at 11:07:54PM +0530, Laxman Dewangan wrote:
Some PWM regulator has the exponential transition in voltage change as
opposite to fixed slew-rate linear transition on other regulators.
For such PWM regulators, add the
On Tuesday 15 November 2016 02:33 PM, Linus Walleij wrote:
On Fri, Nov 11, 2016 at 1:17 PM, Laxman Dewangan wrote:
Yeah but since pinctrl and pinmux has its own debugfs files why is this
necessary? I understand it is convenient but only for debugging
right? They the inconvenience of using
On Saturday 05 November 2016 03:50 AM, Linus Walleij wrote:
On Wed, Nov 2, 2016 at 1:17 PM, Laxman Dewangan wrote:
Many of devices/SoCs supports the GPIO and special IO function
from their pins. On such cases, there is always configuration
bits to select the mode of pin as GPIO or as the
Remove tegra_io_rail_power_on() and tegra_io_rail_power_off()
from header as client has been moved to new APIs.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
None
---
include/soc/tegra/pmc.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/soc/tegra/pmc.h b/include
The IO pad voltage configuration can be done in the regulator
notifier callback which is atomic in nature.
Replace the mutex with spin lock for the locking mechanism.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
New in series based on pinctrl driver requirement.
---
drivers/soc/tegra
Add API to get the IO pad power status of the Tegra IO pads.
This will help client driver to get the current power status
of IO pads for handling IO pad power.
Signed-off-by: Laxman Dewangan
---
Changes from V1:
None
---
drivers/soc/tegra/pmc.c | 22 ++
include/soc/tegra
ed in
https://github.com/thierryreding/linux/tree/tegra186
---
Changes from V1:
- make the IO pad votlage configurations to the atomic context as 4th patch of
series.
Laxman Dewangan (4):
soc/tegra: pmc: Remove legacy Tegra I/O rail API
soc/tegra: pmc: Add interface to get IO pad
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