Tested-by: Krishna Reddy
Validated nested translations with NVMe PCI device assigned to Guest VM.
Tested with both v12 and v13 of Jean-Philippe's patches as base.
> This is based on Jean-Philippe's
> [PATCH v12 00/10] iommu: I/O page faults for SMMUv3
> https://lore.kernel.o
Tested-by: Krishna Reddy
Validated Nested SMMUv3 translations for NVMe PCIe device from Guest VM and is
functional.
This patch series resolved the mismatch(seen with v11 patches) for
VFIO_IOMMU_SET_PASID_TABLE and VFIO_IOMMU_CACHE_INVALIDATE Ioctls between linux
and QEMU patch series
> Hi Krishna,
> On 3/15/21 7:04 PM, Krishna Reddy wrote:
> > Tested-by: Krishna Reddy
> >
> >> 1) pass the guest stage 1 configuration
> >
> > Validated Nested SMMUv3 translations for NVMe PCIe device from Guest VM
> along with patch series "v11 SM
Tested-by: Krishna Reddy
> 1) pass the guest stage 1 configuration
> 3) invalidate stage 1 related caches
Validated Nested SMMUv3 translations for NVMe PCIe device from Guest VM along
with patch series "v13 SMMUv3 Nested Stage Setup (IOMMU part)" and QEMU patch
series "vS
Tested-by: Krishna Reddy
> 1) pass the guest stage 1 configuration
Validated Nested SMMUv3 translations for NVMe PCIe device from Guest VM along
with patch series "v11 SMMUv3 Nested Stage Setup (VFIO part)" and QEMU patch
series "vSMMUv3/pSMMUv3 2 stage VFIO integration&q
Move TLB timeout and spin count macros to header file to
allow using the same from vendor specific implementations.
Reviewed-by: Jon Hunter
Reviewed-by: Nicolin Chen
Reviewed-by: Pritesh Raithatha
Reviewed-by: Robin Murphy
Reviewed-by: Thierry Reding
Signed-off-by: Krishna Reddy
.
Reviewed-by: Jon Hunter
Reviewed-by: Nicolin Chen
Reviewed-by: Pritesh Raithatha
Reviewed-by: Robin Murphy
Reviewed-by: Thierry Reding
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 99 +
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu
Add binding for NVIDIA's Tegra194 SoC SMMU.
Reviewed-by: Jon Hunter
Reviewed-by: Rob Herring
Reviewed-by: Robin Murphy
Signed-off-by: Krishna Reddy
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 25 ++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --
/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (5):
iommu/arm-smmu: move TLB timeout and spin count macros
iommu/arm-smmu: ioremap smmu mmio region before implementation init
iommu/arm-smmu: add NVIDIA implementation for ARM MMU-500 usage
dt-bindings: arm-smmu: add
U-500 instance is supported by standard
arm-smmu.c driver itself.
Reviewed-by: Jon Hunter
Reviewed-by: Nicolin Chen
Reviewed-by: Pritesh Raithatha
Reviewed-by: Robin Murphy
Reviewed-by: Thierry Reding
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
Reding
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index cdd15ead9bc4..de520115d3df 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
>On Mon, Jul 13, 2020 at 02:50:20PM +0100, Will Deacon wrote:
>> On Tue, Jul 07, 2020 at 10:00:12PM -0700, Krishna Reddy wrote:
> >> Changes in v10:
>> > Perform SMMU base ioremap before calling implementation init.
>> > Check for Global faults across both
Thanks Rob. One question on setting "minItems: ". Please see below.
>> +allOf:
>> + - if:
>> + properties:
>> +compatible:
>> + contains:
>> +enum:
>> + - nvidia,tegra194-smmu
>> +then:
>> + properties:
>> +reg:
>> + minItem
.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 99 +
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu/arm-smmu.h| 3 +
3 files changed, 117 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu-nvidia.c b/drivers/iommu
Move TLB timeout and spin count macros to header file to
allow using the same from vendor specific implementations.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu.c | 3 ---
drivers/iommu/arm-smmu.h | 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu
U-500 instance is supported by standard
arm-smmu.c driver itself.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Makefile | 2 +-
drivers/iommu/arm-smmu-impl.c | 3 +
drivers/iommu/arm-smmu-nvidia.c | 179
dr
/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (5):
iommu/arm-smmu: move TLB timeout and spin count macros
iommu/arm-smmu: ioremap smmu mmio region before implementation init
iommu/arm-smmu: add NVIDIA implementation for ARM MMU-500
ioremap smmu mmio region before calling into implementation init.
This is necessary to allow mapped address available during vendor
specific implementation init.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a
Add binding for NVIDIA's Tegra194 SoC SMMU.
Signed-off-by: Krishna Reddy
---
.../devicetree/bindings/iommu/arm,smmu.yaml| 18 ++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/
On 01/07/2020 20:00, Krishna Reddy wrote:
>>>>>> +items:
>>>>>> + - enum:
>>>>>> + - nvdia,tegra194-smmu
>>>>>> + - const: arm,mmu-500
>>>>
>>>>> Is the fall
>> With shared irq line, the context fault identification is not optimal
>> already. Reading all the context banks all the time can be additional mmio
>> read overhead. But, it may not hurt the real use cases as these happen only
>> when there are bugs.
>Right, I did ponder the idea of a whole
>Yeah, I realised later last night that this probably originated from forking
>the whole driver downstream. But even then you could have treated the other
>one as a separate nsmmu with a single instance ;)
True, But the initial nvidia implementation had limitation that it can only
handle one in
+items:
+ - enum:
+ - nvdia,tegra194-smmu
+ - const: arm,mmu-500
> >
>>> Is the fallback compatible appropriate here? If software treats this as a
>>> standard MMU-500 it will only program the first instance (because the
>>> second isn't
>>> +for (inst = 0; inst < nvidia_smmu->num_inst; inst++) {
>>> +irq_ret = nvidia_smmu_global_fault_inst(irq, smmu, inst);
>>> +if (irq_ret == IRQ_HANDLED)
>>> +return irq_ret;
>>
>> Any chance there could be more than one SMMU faulting by the time we
>> + - description: NVIDIA SoCs that use more than one "arm,mmu-500"
> Hmm, there must be a better way to word that to express that it only applies
> to the sets of SMMUs that must be programmed identically, and not any other
> independent MMU-500s that might also happen to be in the same So
>> + * When Linux kernel supports multiple SMMU devices, the SMMU device
>> +used for
>> + * isochornous HW devices should be added as a separate ARM MMU-500
>> +device
>> + * in DT and be programmed independently for efficient TLB invalidates.
>I don't understand the "When" there - the driver h
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 98 +
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu/arm-smmu.h| 3 +
3
r
two ARM MMU-500s.
This implementation supports programming two or three ARM MMU-500s
identically as per DT config.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Makefile | 2 +-
drivers/iommu/arm-smmu-impl.c | 3 +
drivers/iommu/arm
Add binding for NVIDIA's Tegra194 SoC SMMU topology that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
.../devicetree/bindings/iommu/arm,smmu.yaml| 18 ++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.ya
Move TLB timeout and spin count macros to header file to
allow using the same values from vendor specific implementations.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu.c | 3 ---
drivers/iommu/arm-smmu.h | 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers
/lkml/2019/10/30/1054
v3 - https://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (4):
iommu/arm-smmu: move TLB timeout and spin count macros
iommu/arm-smmu: add NVIDIA implementation for ARM MMU-500 usage
dt
>> The driver intend to support up to 3 instances. It doesn't really mandate
>> that all three instances be present in same DT node.
>> Each mmio aperture in "reg" property is an instance here. reg =
>> , , ; The reg can have
>> all three or less and driver just configures based on reg and it wo
>OK, well I see what you are saying, but if we intended to support all 3 for
>Tegra194, then we should ensure all 3 are initialised correctly.
The driver intend to support up to 3 instances. It doesn't really mandate that
all three instances be present in same DT node.
Each mmio aperture in "reg
>> NVIDIA's Tegra194 SoC uses two ARM MMU-500s together to interleave
>> IOVA accesses across them.
>> Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
>> string for Tegra194 SoC SMMU topology.
>There is no description here of the 3rd SMMU that you mention below.
>I think t
>> +struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device
>> +*smmu) {
>> +unsigned int i;
>> +for (i = 1; i < MAX_SMMU_INSTANCES; i++) {
>> +struct resource *res;
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, i);
>> +if
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 98 +
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu/arm-smmu.h| 3 +
3
Add binding for NVIDIA's Tegra194 SoC SMMU topology that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.ya
/5/21/1114
v4 - https://lkml.org/lkml/2019/10/30/1054
v3 - https://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (3):
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add
NVIDIA's Tegra194 SoC uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 SoC SMMU topology.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/
>> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
>> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst,
>> + smmu->numpage + idx);
[...]
>> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
>> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
>It reads FSR
>> + if (!nvidia_smmu->bases[0])
>> + nvidia_smmu->bases[0] = smmu->base;
>> +
>> + return nvidia_smmu->bases[inst] + (page << smmu->pgshift); }
>Not critical -- just a nit: why not put the bases[0] in init()?
smmu->base is not available during nvidia_smmu_impl_init() call. It
NVIDIA's Tegra194 SoC uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 SoC SMMU topology.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 101 +++-
drivers/iommu/arm-smmu.c| 17 +-
drivers/iommu/arm-smmu.h| 3
- https://lkml.org/lkml/2019/10/30/1054
v3 - https://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (3):
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add binding for
Add binding for NVIDIA's Tegra194 SoC SMMU topology that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.ya
>Should NVIDIA_TEGRA194_SMMU be a separate value for smmu->model, perhaps? That
>way we avoid this somewhat odd check here.
NVIDIA haven't made any changes to arm,mmu-500. It is only used in different
topology. New model would be mis-leading here.
As suggested by Robin, It can just be moved to
>> + - nvdia,tegra194-smmu-500
>The -500 suffix here seems a bit redundant since there's no other type of SMMU
>in Tegra194, correct?
Yeah, there is only one type of SMMU supported in T194. It was added to be
synonymous with mmu-500. Can be removed.
-KR
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 100
drivers/iommu/arm-smmu.c| 11 +++-
drivers/iommu/arm-smmu.h| 3 +
3
>> drivers/iommu/arm-smmu-nvidia.c:151:33: sparse: sparse: cast removes
>> address space '' of expression
Reported-by: kbuild test robot
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Document
NVIDIA's Tegra194 soc uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 soc.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (4):
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add binding for Tegra194 SMMU
iommu/arm-smmu: Add global/context fault
>For the record: I don't think we should apply these because we don't have a
>good way of testing them. We currently have three problems that prevent us
>from enabling SMMU on Tegra194:
Out of three issues pointed here, I see that only issue 2) is a real blocker
for enabling SMMU HW by default
NVIDIA's Tegra194 soc uses two ARM MMU-500s together to interleave
IOVA accesses across them.
Add NVIDIA implementation for dual ARM MMU-500s and add new compatible
string for Tegra194 soc.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Mak
Add DT node for T194 SMMU to enable SMMU support.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 77
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index
Add global/context fault hooks to allow NVIDIA SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 100
drivers/iommu/arm-smmu.c| 11 +++-
drivers/iommu/arm-smmu.h| 3 +
3
Enable SMMU translations for SDHCI and EQOS transactions on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Document
Changes in v5:
Rebased on top of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
next
v4 - https://lkml.org/lkml/2019/10/30/1054
v3 - https://lkml.org/lkml/2019/10/18/1601
v2 - https://lkml.org/lkml/2019/9/2/980
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (5):
iommu
>>https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/updates
Thanks Will! Let me rebase my patches on top of this branch and send it out.
-KR
Hi Robin,
>>Apologies for crossed wires, but I had a series getting rid of
>>arm_smmu_flush_ops which was also meant to end up making things a bit easier
>>for you:
I was looking to rebase on top of your changes first. Then I read Will's reply
that said your work is queued for 5.5.
Let me kno
c tlb.
v1 - https://lkml.org/lkml/2019/8/29/1588
Krishna Reddy (7):
iommu/arm-smmu: prepare arm_smmu_flush_ops for override
iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage
dt-bindings: arm-smmu: Add binding for Tegra194 SMMU
iommu/arm-smmu: Add global/context fault implementa
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devic
>>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2);
>> The ARM MMU-500 implementation is unmodified. It is the way the are
>> integrated and used together(for interleaved accesses) is different from
>> regular ARM MMU-500.
>> I have added it to get the model number and to be a
Add global/context fault hooks to allow Nvidia SMMU implementation
handle faults across multiple SMMUs.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-nvidia.c | 127
drivers/iommu/arm-smmu.c| 6 ++
drivers/iommu/arm-smmu.h
Add Memory controller DT node on T194 and enable it.
This patch is a prerequisite for SMMU enable on T194.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 7 +++
2 files changed, 11 insertions
Add Nvidia SMMUv2 implementation and model info.
Signed-off-by: Krishna Reddy
---
MAINTAINERS | 2 +
drivers/iommu/Makefile | 2 +-
drivers/iommu/arm-smmu-impl.c | 2 +
drivers/iommu/arm-smmu-nvidia.c | 97 +
drivers
Enable SMMU translations for SDHCI and EQOS transactions.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index ad509bb..0496a87
Add binding doc for Nvidia's smmu-v2 implementation.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devicetree/bindings/iomm
the following branch as it is dependent on the
Arm SMMU Refactor changes from Robin Murphy that are present in this branch.
https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git
for-joerg/arm-smmu/updates
Krishna Reddy (7):
iommu/arm-smmu: add Nvidia SMMUv2 implementation
dt
Hi Robin,
Thanks for the feedback :)
>The whole point of the library idea was to factor out the code in such a way
>that all the details
>specific to a particular implementation can be kept together. But what this
>patch does is insert
>Tegra194-specific handling all through the 'common' code, w
Rearrange arm-smmu.c code into arm-smmu-common.h, arm-smmu-common.c
and arm-smmu.c.
This patch rearranges the arm-smmu.c code to allow sharing the ARM SMMU
driver code with dual ARM SMMU based Tegra194 SMMU driver.
Signed-off-by: Krishna Reddy
---
drivers/iommu/arm-smmu-common.c | 1922
d transparently
handles programming of two SMMU instances.
The third SMMU instance would use the existing ARM SMMU driver.
Changes in v2:
* Added CONFIG_ARM_SMMU_TEGRA to protect Tegra194 SMMU driver compilation
* Enabled CONFIG_ARM_SMMU_TEGRA in defconfig
* Added SMMU nodes in Tegra194 device tree
Enable IOMMU for all SDHCI controllers in Tegra186.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 230c0c8..996997e
513] iommu: Failed to add device 1520.display to group 0:
-12
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 2f3c8e2..230c0c8 10
[3.379231] [] kernel_init+0x18/0x108
[3.379236] [] ret_from_fork+0x10/0x40
[3.379246] ---[ end trace 578db63bb139b8b8 ]---
Signed-off-by: Krishna Reddy
---
arch/arm64/include/asm/sparsemem.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/sparsemem.h
b/arch
Add the DT node for ARM SMMU on Tegra186.
Signed-off-by: Krishna Reddy
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 73
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index
SDHCI controllers on Tegra186 support 40 bit addressing.
IOVA addresses are 48-bit wide on Tegra186.
SDHCI host common code sets dma mask as either 32-bit or 64-bit.
To avoid access issues when SMMU is enabled, disable 64-bit dma.
Signed-off-by: Krishna Reddy
---
drivers/mmc/host/sdhci-tegra.c
>OK, so that's really just another variant of the existing problem we have with
>certain PCI root complexes with restrictive inbound windows.
>The appropriate way to handle that is to reserve the unusable areas of the
>IOVA space up-front.
> Since the support for the ACPI equivalent of "dma-range
most of IOVA range supported by
HW? Can IOVA code look for dma-ranges on its own and limit the iova top to
lowest of mask and dma-ranges, if it is present? or any other ways you can
think of?
-KR
-Original Message-
From: Robin Murphy [mailto:robin.mur...@arm.com]
Sent: Friday, Septe
Limit the IOVA allocated to dma-ranges specified for the device.
This is necessary to ensure that IOVA allocated is addressable
by device.
Signed-off-by: Krishna Reddy
---
drivers/iommu/dma-iommu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/iommu/dma-iommu.c b/drivers
+/*
+ * struct hmm_mirror_ops - HMM mirror device operations callback
+ *
+ * @update: callback to update range on a device */ struct
+hmm_mirror_ops {
+ /* update() - update virtual address range of memory
+*
+* @mirror: pointer to struct hmm_mirror
+* @update: upda
> > The device(H/W controller) need to access few special memory
> > blocks(IOVA==PA) and DRAM as well.
>
> OK, so only /some/ of the VA space is VA==PA, and some is remapped; that's a
> little different that what you originally implied above.
>
> BTW, which HW module is this; AVP/COP or somethin
> > On Tegra, the following use cases need specific IOVA mapping.
> > 1. Few MMIO blocks need IOVA=PA mapping setup.
>
> In that case, why would we enable the IOMMU for that one device; IOMMU
> disabled means VA==PA, right? Perhaps isolation of the device so it can only
> access certain PA ranges
ux.org.uk;
> minc...@kernel.org; chunsang.je...@linaro.org; linux-
> ker...@vger.kernel.org; subas...@gmail.com; linaro-mm-...@lists.linaro.org;
> linux...@kvack.org; io...@lists.linux-foundation.org; Krishna Reddy; linux-
> te...@vger.kernel.org; kyungmin.p...@samsung.com;
> pullip...
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