Re: [PATCH] implement flush_cache_vmap for RISC-V

On Wednesday, April 14, 2021 7:03:13 AM UTC you wrote: > Hi, > > Le 4/12/21 à 3:08 AM, Jisheng Zhang a écrit : > > Hi Jiuyang, > > > > On Mon, 12 Apr 2021 00:05:30 + Jiuyang Liu wrote: > >> This patch implements flush_cache_vmap for RISC-V, since it m

Re: [PATCH] implement flush_cache_vmap and flush_cache_vunmap for RISC-V

VMA won't be added to related codes, which might introduce a bug > > in some out-of-order micro-architecture implementations. > > > > Signed-off-by: Jiuyang Liu > > --- > > > > arch/riscv/include/asm/cacheflush.h | 8 > > 1 file changed, 8 ins

[PATCH] implement flush_cache_vmap for RISC-V

This patch implements flush_cache_vmap for RISC-V, since it modifies PTE. Without this patch, SFENCE.VMA won't be added to related codes, which might introduce a bug in the out-of-order micro-architecture implementations. Signed-off-by: Jiuyang Liu Reviewed-by: Alexandre Ghiti Review

[PATCH] implement flush_cache_vmap and flush_cache_vunmap for RISC-V

This patch implements flush_cache_vmap and flush_cache_vunmap for RISC-V, since these functions might modify PTE. Without this patch, SFENCE.VMA won't be added to related codes, which might introduce a bug in some out-of-order micro-architecture implementations. Signed-off-by: Jiuyan

Re: [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV

On Tue, Mar 16, 2021 at 5:05 AM Alex Ghiti wrote: > > > > Le 3/16/21 à 4:40 AM, Anup Patel a écrit : > > > On Tue, Mar 16, 2021 at 1:59 PM Andrew Waterman > > > wrote: > > >> > > >> On Tue, Mar 16, 2021 at 12:32 AM Anup Patel wrote: >

Re: [PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV

ote: > > +Alex > > On Tue, Mar 16, 2021 at 9:20 AM Jiuyang Liu wrote: > > > > This patch inserts SFENCE.VMA after modifying PTE based on RISC-V > > specification. > > > > arch/riscv/include/asm/pgtable.h: > > 1. implement pte_user, pte_global and pte_le

[PATCH] Insert SFENCE.VMA in function set_pte_at for RISCV

program asid. 2. implement local_flush_tlb_asid to flush tlb with asid. Signed-off-by: Jiuyang Liu --- arch/riscv/include/asm/pgtable.h | 27 +++ arch/riscv/include/asm/tlbflush.h | 12 2 files changed, 39 insertions(+) diff --git a/arch/riscv/include/asm

[PATCH 2/2] Bug Fix for last patch

Sorry for the noise, Andrew gave me feedbacks, and pointed two bugs in last patch. 1. asid should be thread safe, which is not the intent. 2. asid extracting logic was wrong. This patch fixes these bugs. Signed-off-by: Jiuyang Liu --- arch/riscv/include/asm/tlbflush.h | 8 ++-- 1 file