Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Rob Herring
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 181 ++
1 file changed, 181 insertions(+)
create mode 100644
Documentation
Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..8050c14e6a7a 100644
--- a/MAINTAINERS
the physical layer to provide power-saving.
When the system resumes, the PCIe link should be re-established and the
related control register values should be restored.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 113
1
ors)
| | | || | | || | | |
(MSI SET0) (MSI SET1) ... (MSI SET7)
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Marc Zyng
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
dr
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Marc Zyngier
---
drivers/pci/controller/pcie-mediatek-gen3.c | 172
1 file changed, 172 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.
Signed-off-by: Jianjun Wang
Acked-by: Bjorn Helgaas
---
drivers/pci/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci.c b/drivers/pci
property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs
Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Ji
On Mon, 2021-04-19 at 11:44 +0100, Lorenzo Pieralisi wrote:
> On Fri, Apr 16, 2021 at 02:21:00PM -0500, Bjorn Helgaas wrote:
> > On Wed, Mar 24, 2021 at 11:05:03AM +0800, Jianjun Wang wrote:
> > > These series patches add pcie-mediatek-gen3.c and dt-bindings file to
> >
Hi Bjorn, Lorenzo,
Just gentle ping for this patch set, please kindly let me know your
comments about this patch set.
Thanks.
On Wed, 2021-03-24 at 11:05 +0800, Jianjun Wang wrote:
> MediaTek's PCIe host controller has three generation HWs, the new
> generation HW is an individual
ors)
| | | || | | || | | |
(MSI SET0) (MSI SET1) ... (MSI SET7)
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/control
the physical layer to provide power-saving.
When the system resumes, the PCIe link should be re-established and the
related control register values should be restored.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 113
1
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 172
1 file changed, 172 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
b/drivers/pci/controller
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
dr
Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..8050c14e6a7a 100644
--- a/MAINTAINERS
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Rob Herring
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 181 ++
1 file changed, 181 insertions(+)
create mode 100644
Documentation
This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.
Signed-off-by: Jianjun Wang
---
drivers/pci/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 16a17215f633
v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wang (7):
dt-bindings: PCI: mediatek-gen3: Add YAML schema
PCI: Export pci_pio_to_address() for module use
PCI: mediate
On Fri, 2021-03-19 at 19:53 +0100, Pali Rohár wrote:
> On Thursday 18 March 2021 13:48:07 Jianjun Wang wrote:
> > On Thu, 2021-03-18 at 01:02 +0100, Pali Rohár wrote:
> > > On Saturday 13 March 2021 15:43:14 Jianjun Wang wrote:
> > > > On Thu, 2021-03-11 at
On Thu, 2021-03-18 at 01:02 +0100, Pali Rohár wrote:
> On Saturday 13 March 2021 15:43:14 Jianjun Wang wrote:
> > On Thu, 2021-03-11 at 13:38 +0100, Pali Rohár wrote:
> > > On Wednesday 24 February 2021 14:11:28 Jianjun Wang wrote:
> > > > +static int mtk_pcie_sta
On Thu, 2021-03-11 at 13:38 +0100, Pali Rohár wrote:
> On Wednesday 24 February 2021 14:11:28 Jianjun Wang wrote:
> > +static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
> > +{
> ...
> > +
> > + /* Delay 100ms to wait the reference clocks becom
On Thu, 2021-03-11 at 08:19 +, Marc Zyngier wrote:
> On 2021-03-11 00:05, Pali Rohár wrote:
> > On Wednesday 24 February 2021 14:11:30 Jianjun Wang wrote:
> >> +static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
> >> +
On Wed, 2021-03-10 at 09:41 +, Marc Zyngier wrote:
> On Wed, 10 Mar 2021 06:48:49 +,
> Jianjun Wang wrote:
> > > > +static struct irq_chip mtk_msi_irq_chip = {
> > > > + .name = "MSI",
> > > > + .irq_enable
Hi Marc,
Thanks for your review.
On Tue, 2021-03-09 at 11:23 +, Marc Zyngier wrote:
> On Wed, 24 Feb 2021 06:11:30 +,
> Jianjun Wang wrote:
> >
> > Add MSI support for MediaTek Gen3 PCIe controller.
> >
> > This PCIe controller supports up to 256
On Tue, 2021-03-09 at 11:10 +, Marc Zyngier wrote:
> On Wed, 24 Feb 2021 06:11:29 +,
> Jianjun Wang wrote:
> >
> > Add INTx support for MediaTek Gen3 PCIe controller.
> >
> > Signed-off-by: Jianjun Wang
> > Acked-by: Ryder Lee
> > ---
> &
Hi Krzysztof,
Thanks for your suggestion, I will fix it in the next version.
On Thu, 2021-02-25 at 23:00 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
>
> [...]
> > Thanks for your review,
>
> Thank YOU for all the work here!
>
> [...]
> > > > Add suspend_noirq and resume_noirq callback fu
Hi Krzysztof,
Thanks for your review,
On Wed, 2021-02-24 at 15:10 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
>
> > Add suspend_noirq and resume_noirq callback functions to implement
> > PM system suspend hooks for MediaTek Gen3 PCIe controller.
>
> So, "systems suspend" and "resume" hooks
Hi Krzysztof,
Thanks for your review, I will fix it at next version.
On Wed, 2021-02-24 at 15:24 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
>
> [...]
> > +/**
> > + * mtk_intx_eoi
> > + * @data: pointer to chip specific data
> > + *
> > + * As an emulated level IRQ, its interrupt status wi
Hi Krzysztof,
Thanks for your review, I will fix it at next version.
On Wed, 2021-02-24 at 15:31 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
>
> [...]
> > +static struct irq_chip mtk_msi_irq_chip = {
> > + .name = "MSI",
> > + .irq_enable = mtk_pcie_irq_unmask,
> > + .irq_disable = mt
Hi Krzysztof,
Thanks for your review, I will fix these at next version.
Thanks.
On Wed, 2021-02-24 at 14:36 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
>
> Thank you for all the work here!
>
> [...]
> > + * struct mtk_pcie_port - PCIe port information
> > + * @dev: pointer to PCIe device
Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 546aa66428c9..bef7f4017473 100644
--- a/MAINTAINERS
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
dr
ors)
| | | || | | || | | |
(MSI SET0) (MSI SET1) ... (MSI SET7)
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/control
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 176
1 file changed, 176 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
b/drivers/pci/controller
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 181 ++
1 file changed, 181 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci
This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.
Signed-off-by: Jianjun Wang
---
drivers/pci/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b9fecc25d213
saving.
When system resum, the PCIe link should be re-established and the
related control register values should be restored.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 84 +
1 file changed, 84 insertions(+)
diff --git
rn error number when get_optional* API throws an error
3. Use the bulk clk APIs
Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wang (7):
dt-bindings: PCI: mediatek-gen3: A
On Wed, 2021-01-27 at 13:05 +, Marc Zyngier wrote:
> On 2021-01-27 12:31, Jianjun Wang wrote:
> > On Tue, 2021-01-26 at 13:57 +, Marc Zyngier wrote:
> >> On 2021-01-13 11:39, Jianjun Wang wrote:
> >> > Add MSI support for MediaTek Gen3 PCIe controller.
>
On Tue, 2021-01-26 at 12:25 +, Marc Zyngier wrote:
> On 2021-01-13 11:39, Jianjun Wang wrote:
> > Add INTx support for MediaTek Gen3 PCIe controller.
> >
> > Signed-off-by: Jianjun Wang
> > Acked-by: Ryder Lee
> > ---
> > drivers/pc
On Tue, 2021-01-26 at 13:57 +, Marc Zyngier wrote:
> On 2021-01-13 11:39, Jianjun Wang wrote:
> > Add MSI support for MediaTek Gen3 PCIe controller.
> >
> > This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> >
On Mon, 2021-01-25 at 14:22 -0600, Rob Herring wrote:
> On Wed, Jan 13, 2021 at 07:39:55PM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> >
> > Signed-off-by: Jianjun Wang
> > Acked-by: Ryder L
On Mon, 2021-01-25 at 13:54 -0600, Rob Herring wrote:
> On Wed, Jan 13, 2021 at 07:39:57PM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supports Gen3 speed and
> > compat
g document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs
Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wang (7):
dt-bin
ors)
| | | || | | || | | |
(MSI SET0) (MSI SET1) ... (MSI SET7)
With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/control
Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..1a033812c7f9 100644
--- a/MAINTAINERS
saving.
When system resum, the PCIe link should be re-established and the
related control register values should be restored.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 78 +
1 file changed, 78 insertions(+)
diff --git
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 163
1 file changed, 163 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
b/drivers/pci/controller
This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.
Signed-off-by: Jianjun Wang
---
drivers/pci/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 6d4d5a2f923d
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 172 ++
1 file changed, 172 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
dr
On Mon, 2020-12-28 at 15:12 +, Marc Zyngier wrote:
> On Mon, 28 Dec 2020 12:01:57 +,
> Jianjun Wang wrote:
> >
> > On Fri, 2020-12-25 at 19:22 +, Marc Zyngier wrote:
>
> Dropped , as it
> bounces:
>
> : host
> mailgw01.mediatek.com[216.
On Fri, 2020-12-25 at 19:22 +, Marc Zyngier wrote:
> Hi Jianjun,
>
> On Fri, 25 Dec 2020 10:03:07 +,
> Jianjun Wang wrote:
> >
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it suppor
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Ack
Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..1a033812c7f9 100644
--- a/MAINTAINERS
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Rob Herring
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 135 ++
1 file changed, 135 insertions(+)
create mode 100644
Documentation
g document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs
Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wang (4):
dt-bin
This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.
Signed-off-by: Jianjun Wang
---
drivers/pci/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 6d4d5a2f923d
On Tue, 2020-12-22 at 11:55 +0800, Nicolas Boichat wrote:
> On Tue, Dec 22, 2020 at 11:38 AM Jianjun Wang
> wrote:
> >
> > On Mon, 2020-12-21 at 10:18 +0800, Nicolas Boichat wrote:
> > > On Wed, Dec 2, 2020 at 9:39 PM Jianjun Wang
> > > wrote:
> >
On Mon, 2020-12-21 at 10:18 +0800, Nicolas Boichat wrote:
> On Wed, Dec 2, 2020 at 9:39 PM Jianjun Wang wrote:
> >
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supports Gen3 speed and
> > up
On Fri, 2020-12-04 at 12:30 -0600, Bjorn Helgaas wrote:
> On Fri, Dec 04, 2020 at 08:39:09AM +0100, Lukas Wunner wrote:
> > On Mon, Nov 30, 2020 at 11:30:05AM -0600, Bjorn Helgaas wrote:
> > > On Mon, Nov 23, 2020 at 02:45:13PM +0800, Jianjun Wang wrote:
> > > > On
On Wed, 2020-12-02 at 07:49 -0600, Bjorn Helgaas wrote:
> On Wed, Dec 02, 2020 at 09:12:55PM +0800, Jianjun Wang wrote:
> > This interface will be used by PCI host drivers for PIO translation,
> > export it to support compiling those drivers as kernel modules.
> >
> >
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Ack
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
Reviewed-by: Rob Herring
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 135 ++
1 file changed, 135 insertions(+)
create mode 100644
Documentation
Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs
Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wang (3)
This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.
Signed-off-by: Jianjun Wang
---
drivers/pci/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index a458c46d7e39
On Mon, 2020-11-30 at 11:30 -0600, Bjorn Helgaas wrote:
> [+cc Lukas, pciehp power control question]
>
> On Mon, Nov 23, 2020 at 02:45:13PM +0800, Jianjun Wang wrote:
> > On Thu, 2020-11-19 at 14:28 -0600, Bjorn Helgaas wrote:
> > > "Add new generation" re
e
> subject, e.g.,
>
> PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
>
> On Wed, Nov 18, 2020 at 04:29:34PM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts
On Thu, 2020-11-19 at 09:22 -0600, Rob Herring wrote:
> On Wed, Nov 18, 2020 at 04:29:34PM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Ack
Add maintainer for MediaTek PCIe controller driver.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 135 ++
1 file changed, 135 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci
property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs
Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wan
On Mon, 2020-09-28 at 10:32 +0200, Philipp Zabel wrote:
> Hi Jianjun,
>
> On Sun, 2020-09-27 at 15:45 +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
&
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Ack
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 126 ++
1 file changed, 126 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci
-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wang (3):
dt-bindings: PCI: mediatek: Add YAML schema
PCI: mediatek: Add new generation controller support
MAINTAINERS: update entry for MediaTek
Add maintainer for MediaTek PCIe controller driver.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7
On Mon, 2020-09-14 at 08:32 -0600, Rob Herring wrote:
> On Mon, Sep 14, 2020 at 5:07 AM Jianjun Wang
> wrote:
> >
> > On Fri, 2020-09-11 at 16:44 -0600, Rob Herring wrote:
> > > On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote:
> > > > Me
On Fri, 2020-09-11 at 16:44 -0600, Rob Herring wrote:
> On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256
On Fri, 2020-09-11 at 16:45 -0600, Rob Herring wrote:
> On Thu, Sep 10, 2020 at 11:45:34AM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> >
> > Signed-off-by: Jianjun Wang
> > Acked-by: Ryder L
On Fri, 2020-09-11 at 16:33 +0200, Philipp Zabel wrote:
> Hi Jianjun,
>
> On Thu, 2020-09-10 at 11:45 +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
&
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Ack
Add maintainer for MediaTek PCIe controller driver.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 130 ++
1 file changed, 130 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci
These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.
Change in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown
Jianjun Wang (3
On Tue, 2020-09-08 at 14:21 -0600, Rob Herring wrote:
> On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
>
> dt-bindings: PCI: mediatek: ... for the subject.
>
> >
>
On Tue, 2020-09-08 at 15:04 -0500, Bjorn Helgaas wrote:
> On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
>
> Please mention "mediatek" in the subject line so "
On Tue, 2020-09-08 at 13:50 -0600, Rob Herring wrote:
> On Mon, 07 Sep 2020 20:08:50 +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> >
> > Acked-by: Ryder Lee
> > Signed-off-by: Jianjun Wang
>
These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.
Jianjun Wang (3):
dt-bindings: Add YAML schemas for Gen3 PCIe controller
PCI: mediatek: Add new generation controller support
MAINTAINERS: update entry for MediaTek PCIe controller
ff-by: Jianjun Wang
---
drivers/pci/controller/Kconfig | 14 +
drivers/pci/controller/Makefile |1 +
drivers/pci/controller/pcie-mediatek-gen3.c | 1063 +++
3 files changed, 1078 insertions(+)
create mode 100644 drivers/pci/controller/pcie-mediatek-g
Add maintainer for MediaTek PCIe controller driver.
Acked-by: Ryder Lee
Signed-off-by: Jianjun Wang
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Acked-by: Ryder Lee
Signed-off-by: Jianjun Wang
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++
1 file changed, 158 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pci
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun
Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.
Change-Id: I2a022c7291c7e7e161b3a7e8bce28781e0f09b90
Signed-off-by: Jianjun Wang
---
.../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++
1 file changed, 158 insertions(+)
create mode 100644
Add maintainer for MediaTek PCIe controller driver.
Signed-off-by: Jianjun Wang
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7 @@ F: drivers/pci
On Fri, 2019-06-28 at 15:34 +0800, Jianjun Wang wrote:
> MT7629 is an ARM platform SoC which has the same PCIe IP with MT7622.
>
> The HW default value of its Device ID is invalid, fix its Device ID to
> match the hardware implementation.
>
> Acked-by: Ryder Lee
> Signed
MT7629 is an ARM platform Soc which has the same PCIe IP with MT7622.
Reviewed-by: Rob Herring
Acked-by: Ryder Lee
Signed-off-by: Jianjun Wang
---
Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci
MT7629 is an ARM platform SoC which has the same PCIe IP with MT7622.
The HW default value of its Device ID is invalid, fix its Device ID to
match the hardware implementation.
Acked-by: Ryder Lee
Signed-off-by: Jianjun Wang
---
drivers/pci/controller/pcie-mediatek.c | 18
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