Reviewed-by: Huacai Chen
On Wed, Jun 11, 2025 at 7:28 PM Thomas Weißschuh
wrote:
>
> Not all tasks have an ABI associated or vDSO mapped,
> for example kthreads never do.
> If such a task ever ends up calling stack_top(), it will derefence the
> NULL ABI pointer and crash.
&
; F: arch/loongarch/include/asm/kvm*
> F: arch/loongarch/include/uapi/asm/kvm*
> F: arch/loongarch/kvm/
> +F: tools/testing/selftests/kvm/*/loongarch/
> +F: tools/testing/selftests/kvm/lib/loongarch/
>
> KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
> M:
Hi, Bibo,
On Sun, Apr 27, 2025 at 2:45 PM Bibo Mao wrote:
>
> Add core KVM selftests support for LoongArch, it includes exception
> handler, mmu page table setup and vCPU startup entry support.
>
> Signed-off-by: Bibo Mao
> ---
> .../selftests/kvm/lib/loongarch/exception.S | 59 +++
> .../se
Hi, Bibo,
On Sun, Apr 27, 2025 at 2:45 PM Bibo Mao wrote:
>
> This patchset adds KVM selftests for LoongArch system, currently only
> some common test cases are supported and pass to run. These test cases
> are listed as following:
> coalesced_io_test
> demand_paging_test
> dirty_log_
Hi, Bibo,
On Wed, Apr 16, 2025 at 11:55 AM Bibo Mao wrote:
>
> Add core KVM selftests support for LoongArch, it includes exception
> handler, mmu page table setup and vCPU startup entry support.
>
> Signed-off-by: Bibo Mao
> ---
> .../selftests/kvm/lib/loongarch/exception.S | 59 +++
> .../s
Hi, Bibo,
On Wed, Apr 16, 2025 at 11:55 AM Bibo Mao wrote:
>
> Add KVM selftests header files for LoongArch, including processor.h
> and kvm_util_base.h. It mainly contains LoongArch CSR register
> definition and page table entry definition.
>
> Signed-off-by: Bibo Mao
> ---
> .../testing/selft
Hi, Thomas,
On Tue, Apr 15, 2025 at 3:10 PM Thomas Weißschuh
wrote:
>
> Not all tasks have an ABI associated or vDSO mapped,
> for example kthreads never do.
> If such a task ever ends up calling stack_top(), it will derefence the
> NULL ABI pointer and crash.
>
> This can for example happen when
Hi, Bibo,
On Thu, Apr 10, 2025 at 11:57 AM Bibo Mao wrote:
>
> Add KVM selftests header files for LoongArch, including processor.h
> and kvm_util_base.h. It mainly contains LoongArch CSR register
> definition and page table entry definition.
>
> Signed-off-by: Bibo Mao
> ---
> .../testing/selft
Hi, Thomas,
On Mon, Apr 14, 2025 at 4:29 PM Thomas Weißschuh
wrote:
>
> Not all tasks have an ABI associated or vDSO mapped,
> for example kthreads never do.
> If such a task ever ends up calling stack_top(), it will derefence the
> NULL vdso pointer and crash.
>
> This can for example happen whe
> > On Wed, Sep 11 2024 at 17:11, Huacai Chen wrote:
> >> Hi, Thomas,
> >>
> >> On Fri, Aug 30, 2024 at 5:32 PM Bibo Mao wrote:
> >>>
> >>> Interrupts can be routed to maximal four virtual CPUs with one HW
> >>> EIOINTC interr
On Tue, Oct 15, 2024 at 2:14 PM Thomas Weißschuh
wrote:
>
> Hi Huacai,
>
> On Tue, Oct 15, 2024 at 10:15:39AM +0800, Huacai Chen wrote:
> > I can take this patch to the loongarch tree, but I think others should
> > get upstream via kselftests tree?
>
> Yes, sounds go
Hi, Thomas,
I can take this patch to the loongarch tree, but I think others should
get upstream via kselftests tree?
Huacai
On Mon, Oct 14, 2024 at 7:36 PM Thomas Weißschuh
wrote:
>
> Not all tasks have a vDSO mapped, for example kthreads never do.
> If such a task ever ends up calling stack_to
Hi, Thomas,
On Fri, Aug 30, 2024 at 5:32 PM Bibo Mao wrote:
>
> Interrupts can be routed to maximal four virtual CPUs with one HW
> EIOINTC interrupt controller model, since interrupt routing is encoded with
> CPU bitmap and EIOINTC node combined method. Here add the EIOINTC virt
> extension supp
On Thu, Aug 29, 2024 at 9:46 AM maobibo wrote:
>
> Huacai,
>
> On 2024/8/28 下午10:27, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Fri, Aug 23, 2024 at 2:39 PM Bibo Mao wrote:
> >>
> >> Interrupts can be routed to maximal four virtual CPUs with one H
Hi, Bibo,
On Fri, Aug 23, 2024 at 2:39 PM Bibo Mao wrote:
>
> Interrupts can be routed to maximal four virtual CPUs with one HW
> EIOINTC interrupt controller model, since interrupt routing is encoded with
> CPU bitmap and EIOINTC node combined method. Here add the EIOINTC virt
> extension suppor
On Tue, Aug 20, 2024 at 12:02 PM maobibo wrote:
>
> Huacai,
>
> On 2024/8/19 下午9:34, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
> >>
> >> Interrupts can be routed to maximal four virtual CPUs wit
On Tue, Aug 20, 2024 at 11:21 AM maobibo wrote:
>
> Huacai,
>
> Thanks for reviewing my patch.
> I reply inline.
>
> On 2024/8/19 下午9:32, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
> >>
> >> E
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
>
> Interrupts can be routed to maximal four virtual CPUs with one HW
> EIOINTC interrupt controller model, since interrupt routing is encoded with
> CPU bitmap and EIOINTC node combined method. Here add the EIOINTC virt
> extension suppo
Hi, Bibo,
On Mon, Aug 12, 2024 at 11:02 AM Bibo Mao wrote:
>
> Export kernel paravirt features to user space, so that VMM can control
> the single paravirt feature. By default paravirt features will be the same
> with kvm supported features if VMM does not set it.
>
> Also a new feature KVM_FEATU
On Mon, Jul 8, 2024 at 9:16 AM maobibo wrote:
>
>
>
> On 2024/7/6 下午5:41, Huacai Chen wrote:
> > On Sat, Jul 6, 2024 at 2:59 PM maobibo wrote:
> >>
> >> Huacai,
> >>
> >> On 2024/7/6 上午11:00, Huacai Chen wrote:
> >>> Hi,
On Sat, Jul 6, 2024 at 2:59 PM maobibo wrote:
>
> Huacai,
>
> On 2024/7/6 上午11:00, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Fri, May 24, 2024 at 3:38 PM Bibo Mao wrote:
> >>
> >> Steal time feature is added here in kvm side, VM can search su
Hi, Bibo,
On Fri, May 24, 2024 at 3:38 PM Bibo Mao wrote:
>
> Steal time feature is added here in kvm side, VM can search supported
> features provided by KVM hypervisor, feature KVM_FEATURE_STEAL_TIME
> is added here. Like x86, steal time structure is saved in guest memory,
> one hypercall funct
On Mon, Jul 1, 2024 at 2:22 PM Tiezhu Yang wrote:
>
> On 06/29/2024 11:03 PM, Oleg Nesterov wrote:
> > LoongArch defines UPROBE_SWBP_INSN as a function call and this breaks
> > arch_uprobe_trampoline() which uses it to initialize a static variable.
> >
> > Add the new "__builtin_constant_p" helper
Hi, Oleg,
On Sat, Jun 29, 2024 at 11:05 PM Oleg Nesterov wrote:
>
> LoongArch defines UPROBE_SWBP_INSN as a function call and this breaks
> arch_uprobe_trampoline() which uses it to initialize a static variable.
>
> Add the new "__builtin_constant_p" helper, __emit_break(), and redefine
> the cur
On Sat, Jun 29, 2024 at 9:40 PM Oleg Nesterov wrote:
>
> On 06/29, Tiezhu Yang wrote:
> >
> > On Thu, 27 Jun 2024 19:38:06 +0200
> > Oleg Nesterov wrote:
> >
> > ...
> >
> > > > > +arch_initcall(check_emit_break);
> > > > > +
> > > >
> > > > I wouldn't even bother with this, but whatever.
> > >
>
On Tue, May 7, 2024 at 11:06 AM maobibo wrote:
>
>
>
> On 2024/5/7 上午10:05, Huacai Chen wrote:
> > On Tue, May 7, 2024 at 9:40 AM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午10:17, Huacai Chen wrote:
> >>> On Mon, May 6, 202
On Tue, May 7, 2024 at 9:40 AM maobibo wrote:
>
>
>
> On 2024/5/6 下午10:17, Huacai Chen wrote:
> > On Mon, May 6, 2024 at 6:05 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午5:40, Huacai Chen wrote:
> >>> On Mon, May 6, 2024
On Mon, May 6, 2024 at 6:05 PM maobibo wrote:
>
>
>
> On 2024/5/6 下午5:40, Huacai Chen wrote:
> > On Mon, May 6, 2024 at 5:35 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午4:59, Huacai Chen wrote:
> >>> On Mon, May 6, 2024 at
On Mon, May 6, 2024 at 5:35 PM maobibo wrote:
>
>
>
> On 2024/5/6 下午4:59, Huacai Chen wrote:
> > On Mon, May 6, 2024 at 4:18 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 下午3:06, Huacai Chen wrote:
> >>> H
On Mon, May 6, 2024 at 4:18 PM maobibo wrote:
>
>
>
> On 2024/5/6 下午3:06, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Mon, May 6, 2024 at 2:36 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/5/6 上午9:49, Huacai Chen wrote:
> >
Hi, Bibo,
On Mon, May 6, 2024 at 2:36 PM maobibo wrote:
>
>
>
> On 2024/5/6 上午9:49, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
> >>
> >> Physical cpuid is used for interrupt routing for irqchips such
On Mon, May 6, 2024 at 3:00 PM maobibo wrote:
>
>
>
> On 2024/5/6 上午9:53, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
> >>
> >> PARAVIRT option and pv ipi is added on guest kernel side, function
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
>
> On LoongArch system, there is hypercall instruction special for
> virtualization. When system executes this instruction on host side,
> there is illegal instruction exception reported, however it will
> trap into host when it is execut
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
>
> PARAVIRT option and pv ipi is added on guest kernel side, function
> pv_ipi_init() is to add ipi sending and ipi receiving hooks. This function
> firstly checks whether system runs on VM mode. If kernel runs on VM mode,
> it will call
Hi, Bibo,
On Sun, Apr 28, 2024 at 6:05 PM Bibo Mao wrote:
>
> Physical cpuid is used for interrupt routing for irqchips such as
> ipi/msi/extioi interrupt controller. And physical cpuid is stored
> at CSR register LOONGARCH_CSR_CPUID, it can not be changed once vcpu
> is created and physical cpui
Hi, Bibo,
I have done an off-list discussion with some KVM experts, and they
think user-space have its right to know PV features, so cpucfg
solution is acceptable.
And I applied this series with some modifications at
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git/lo
Hi, Bibo,
On Tue, Apr 30, 2024 at 9:45 AM Bibo Mao wrote:
>
> Percpu struct kvm_steal_time is added here, its size is 64 bytes and
> also defined as 64 bytes, so that the whole structure is in one physical
> page.
>
> When vcpu is onlined, function pv_enable_steal_time() is called. This
> functio
erui wrote:
> >> On 2/27/24 11:14, maobibo wrote:
> >>>
> >>>
> >>> On 2024/2/27 上午4:02, Jiaxun Yang wrote:
> >>>>
> >>>>
> >>>> 在2024年2月26日二月 上午8:04,maobibo写道:
> >>>>> On 20
On Mon, Feb 26, 2024 at 10:04 AM maobibo wrote:
>
>
>
> On 2024/2/24 下午5:13, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
> >>
> >> Instruction cpucfg can be used to get processor features. And there
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> register access on ipi sending, and two iocsr access on ipi receiving
> which is ipi interrupt handler. On VM mode all iocsr accessing will
> cause VM to trap into
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> Paravirt interface pv_ipi_init() is added here for guest kernel, it
> firstly checks whether system runs on VM mode. If kernel runs on VM mode,
> it will call function kvm_para_available() to detect current VMM type.
> Now only KVM VM
Hi, Bibo,
On Thu, Feb 22, 2024 at 11:28 AM Bibo Mao wrote:
>
> Instruction cpucfg can be used to get processor features. And there
> is trap exception when it is executed in VM mode, and also it is
> to provide cpu features to VM. On real hardware cpucfg area 0 - 20
> is used. Here one specified
On Mon, Feb 19, 2024 at 5:21 PM maobibo wrote:
>
>
>
> On 2024/2/19 下午4:48, Huacai Chen wrote:
> > On Mon, Feb 19, 2024 at 12:11 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/2/19 上午10:42, Huacai Chen wrote:
> >>> Hi,
On Mon, Feb 19, 2024 at 3:37 PM maobibo wrote:
>
>
>
> On 2024/2/19 下午3:16, Huacai Chen wrote:
> > On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
> >>
> >>
> >>
> >> On 2024/2/19 上午10:45, Huacai Chen wrote:
> >>> Hi,
On Mon, Feb 19, 2024 at 12:11 PM maobibo wrote:
>
>
>
> On 2024/2/19 上午10:42, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
> >>
> >> The patch adds paravirt interface for guest kernel, function
> >
On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
>
>
>
> On 2024/2/19 上午10:45, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
> >>
> >> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
&g
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
>
> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> register access on ipi sending, and two iocsr access on ipi receiving
> which is ipi interrupt handler. On VM mode all iocsr registers
> accessing will cause VM to
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> The patch adds paravirt interface for guest kernel, function
> pv_guest_initi() firstly checks whether system runs on VM mode. If kernel
> runs on VM mode, it will call function kvm_para_available() to detect
> whether current VMM is K
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> On LoongArch system, hypercall instruction is supported when system
> runs on VM mode. This patch adds dummy function with hypercall
> instruction emulation, rather than inject EXCCODE_INE invalid
> instruction exception.
>
> Signed-of
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> This patch refines ipi handling on LoongArch platform, there are
> three changes with this patch.
> 1. Add generic get_percpu_irq() api, replace some percpu irq functions
> such as get_ipi_irq()/get_pmc_irq()/get_timer_irq() with get_p
Hi, Oreoluwa,
On Thu, Feb 15, 2024 at 5:31 AM Oreoluwa Babatunde
wrote:
>
>
> On 2/14/2024 5:03 AM, Huacai Chen wrote:
> > Hi, Oreoluwa,
> >
> > On Sat, Feb 10, 2024 at 8:29 AM Oreoluwa Babatunde
> > wrote:
> >> The platform_init() function which is c
Hi, Oreoluwa,
On Sat, Feb 10, 2024 at 8:29 AM Oreoluwa Babatunde
wrote:
>
> The platform_init() function which is called during device bootup
> contains a few calls to memblock_alloc().
> This is an issue because these allocations are done before reserved
> memory regions are set aside in arch_me
Hi, Bibo,
Without this patch I can also create a SMP VM, so what problem does
this patch want to solve?
Huacai
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
>
> Physical cpuid is used to irq routing for irqchips such as ipi/msi/
> extioi interrupt controller. And physical cpuid is stored at C
Hi, Bibo,
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
>
> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> register access on ipi sender and two iocsr access on ipi receiver
> which is ipi interrupt handler. On VM mode all iocsr registers
> accessing will trap into hyper
Hi, Bibo,
On Mon, Jan 22, 2024 at 6:03 PM Bibo Mao wrote:
>
> This patch refines ipi handling on LoongArch platform, there are
> three changes with this patch.
> 1. Add generic get_percpu_irq api, replace some percpu irq function
> such as get_ipi_irq/get_pmc_irq/get_timer_irq with get_percpu_irq
Hi, Rui Wang,
On Fri, Feb 12, 2021 at 4:21 PM Rui Wang wrote:
>
> From: wangrui
>
> When user-space program accessing a virtual address and falls into TLB invalid
> exception handling. at almost the same time, if the pmd which that contains
> this
> virtual address is hit by THP scanning, and t
Hi, Paolo,
On Sat, Apr 3, 2021 at 6:43 PM Paolo Bonzini wrote:
>
> On 03/04/21 04:31, Huacai Chen wrote:
> > Hi, Paolo,
> >
> > TE mode has been removed in the MIPS tree, can we also remove it in
> > KVM tree before this rework?
>
> I tried the merge and i
Hi, Paolo,
TE mode has been removed in the MIPS tree, can we also remove it in
KVM tree before this rework?
Huacai
On Fri, Apr 2, 2021 at 11:58 PM Paolo Bonzini wrote:
>
> Both trap-and-emulate and VZ have a single implementation that covers
> both .flush_shadow_all and .flush_shadow_memslot, a
Reviewed-by: Huacai Chen
On Fri, Apr 2, 2021 at 11:58 PM Paolo Bonzini wrote:
>
> memslots are stored in RCU and there should be no need to
> change them.
>
> Signed-off-by: Paolo Bonzini
> ---
> arch/arm64/kvm/arm.c | 2 +-
> arch/mips/kvm/mips.c | 2 +-
&
Hi, Qing,
On Sat, Mar 6, 2021 at 10:36 AM Qing Zhang wrote:
>
> Add IO interrupt controller support for Loongson 2k1000, different
> from the 3a series is that 2K1000 has 64 interrupt sources, 0-31
> correspond to the device tree liointc0 device node, and the other
> correspond to liointc1 node.
Reviewed-by: Huacai Chen
On Tue, Mar 2, 2021 at 10:27 AM Jiaxun Yang wrote:
>
>
>
> 在 2021/3/1 下午11:29, Thomas Bogendoerfer 写道:
> > KVM_GUEST is broken and unmaintained, so let's remove it.
> >
> > Signed-off-by: Thomas Bogendoerfer
>
> Reviewed-by:
Hi, Yury,
On Thu, Feb 25, 2021 at 9:59 PM Yury Norov wrote:
>
> From: Alexander Lobakin
>
> MIPS doesn't have architecture-optimized bitsearching functions,
> like find_{first,next}_bit() etc.
Emm, I think MIPS can use clo/clz to optimize bitsearching functions.
Huacai
> It's absolutely harmle
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> This is a Copyright line, and just a typo slipped through.
>
> Signed-off-by: Lukas Bulwahn
> ---
> arch/mips/sgi-ip27/ip27-timer.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletion
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> The domain lookup for linux-mips.org fails for quite some time now.
> Further, the two links:
>
> http://decstation.unix-ag.org/
> http://www.computer-refuge.org/classiccmp/ftp.digital.
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> The linux-mips mailing list now lives at kernel.org. Update all references
> in the kernel tree.
>
> Signed-off-by: Lukas Bulwahn
> ---
> arch/mips/kernel/r4k-bugs64.c | 2 +-
> a
Reviewed-by: Huacai Chen
On Tue, Feb 23, 2021 at 12:22 AM Lukas Bulwahn wrote:
>
> The domain lookup for linux-mips.org fails for quite some time now. Hence,
> webpages, the patchwork instance and Ralf Baechle's email there is not
> reachable anymore.
>
> Remove all refe
Hi, Chenyang,
On Fri, Feb 19, 2021 at 5:11 PM Chenyang Li wrote:
>
> This patch adds an initial DRM driver for the Loongson LS7A1000
> bridge chip(LS7A). The LS7A bridge chip contains two display
> controllers, support dual display output. The maximum support for
> each channel display is to 1920
Reviewed-by: Huacai Chen
On Wed, Feb 10, 2021 at 6:04 PM Christoph Hellwig wrote:
>
> CONFIG_DMA_MAYBE_COHERENT just guards two early init options now. Just
> enable them unconditionally for CONFIG_DMA_NONCOHERENT.
>
> Signed-off-by: Christoph Hellwig
> ---
> arch/mi
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: c1f664d2400e73d5ca0fcd067fa5847d2c789c11
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/c1f664d2400e73d5ca0fcd067fa5847d2c789c11
Author:Huacai Chen
Reviewed-by: Huacai Chen
On Mon, Feb 8, 2021 at 10:51 PM Christoph Hellwig wrote:
>
> Just select DMA_NONCOHERENT and ARCH_HAS_SETUP_DMA_OPS from the
> MIPS_GENERIC platform instead.
>
> Signed-off-by: Christoph Hellwig
> ---
> arch/mips/Kconfig | 8 ++-
Hi, Chenyang,
On Fri, Feb 5, 2021 at 4:33 PM Chenyang Li wrote:
>
> This patch adds an initial DRM driver for the Loongson LS7A1000
> bridge chip(LS7A). The LS7A bridge chip contains two display
> controllers, support dual display output. The maximum support for
> each channel display is to 1920x
Reviewed-by: Huacai Chen
On Tue, Feb 2, 2021 at 10:15 AM Yang Li wrote:
>
> Eliminate the following coccicheck warning:
> ./arch/mips/kvm/mips.c:151:2-3: Unneeded semicolon
>
> Reported-by: Abaci Robot
> Signed-off-by: Yang Li
> ---
> arch/mips/kvm/mips.c | 2
Reviewed-by: Huacai Chen
On Thu, Jan 21, 2021 at 1:44 PM Jinyang He wrote:
>
> Some headers are not necessary, remove them and sort includes.
>
> Signed-off-by: Jinyang He
> ---
> v2:
> - Remove useless header inclusion.
>
> arch
Reviewed-by: Huacai Chen
On Tue, Jan 12, 2021 at 9:07 PM Jinyang He wrote:
>
> Just reorder the header files.
>
> Signed-off-by: Jinyang He
> ---
> arch/mips/kernel/process.c | 44 ++--
> 1 file changed, 22 insertions(+), 22 deleti
Reviewed-by: Huacai Chen
On Wed, Jan 6, 2021 at 7:01 AM Nathan Chancellor
wrote:
>
> When building with clang, the following section mismatch warning occurs:
>
> WARNING: modpost: vmlinux.o(.text+0x24490): Section mismatch in
> reference from the function r4k_cache_init()
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 4cc99d03757df10a4064ba28bf6021406b04d6a9
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/4cc99d03757df10a4064ba28bf6021406b04d6a9
Author:Huacai Chen
Hi, Jiaxun,
On Wed, Dec 30, 2020 at 11:26 AM Jiaxun Yang wrote:
>
> Loongson64C is known to be vulnerable to meltdown according to
> PoC from Rui Wang .
How about Loongson-3A1000/3B1500, and Loongson-2E/2F?
Huacai
>
> Loongson64G defended these side-channel attack by silicon.
>
> Signed-off-by:
Reviewed-by: Huacai Chen
On Wed, Dec 30, 2020 at 11:25 AM Jiaxun Yang wrote:
>
> Accorading to MIPS's announcement[1], only P5600 and P6600 is
> affected by spectre v1 and v2, other cores are not affected.
>
> So we mark vulnerabilities states for MIPS cores as known and
&
Hi, Jiaxun,
On Wed, Dec 30, 2020 at 11:25 AM Jiaxun Yang wrote:
>
> Add infrastructure to display CPU vulnerabilities.
> As most MIPS CPU vendors are dead today and we can't confirm
> vulnerabilities states with them, we'll display vulnerabilities
> as "Unknown" by default and override them in cp
Reviewed-by: Huacai Chen
On Wed, Dec 30, 2020 at 11:49 AM Jiaxun Yang wrote:
>
> .cprestore is removed as we don't expect Position Independent
> zboot ELF.
>
> .noreorder is also removed and rest instructions are massaged
> to improve readability.
>
> t9 register
Reviewed-by: Huacai Chen
On Wed, Dec 30, 2020 at 11:43 AM Jiaxun Yang wrote:
>
> cluster is required for cacheinfo to set shared_cpu_map correctly.
>
> Signed-off-by: Jiaxun Yang
> Reviewed-by: Tiezhu Yang
> Tested-by: Tiezhu Yang
> ---
> arch/mips/loongson64/smp.c
Hi, Jiaxun,
On Wed, Dec 30, 2020 at 11:41 AM Jiaxun Yang wrote:
>
> Victim Cache is defined by Loongson as per-core unified
> private Cache.
> Add this into cacheinfo and make cache levels selfincrement
> instead of hardcode levels.
>
> Signed-off-by: Jiaxun Yang
> Reviewed-by: Tiezhu Yang
> Te
Hi, Qing,
On Sat, Dec 26, 2020 at 5:13 PM Qing Zhang wrote:
>
> The SPI controller has the following characteristics:
>
> - Full-duplex synchronous serial data transmission
> - Support up to 4 variable length byte transmission
> - Main mode support
> - Mode failure generates an error flag and iss
Reviewed-by: Huacai Chen
On Sat, Dec 26, 2020 at 5:16 PM Qing Zhang wrote:
>
> Add spi support.
>
> Signed-off-by: Qing Zhang
> ---
>
> v2:
> - Add spi about pci device DT
>
> v3:
> - Remove spiflash node
>
> v4:
> - Remove useless compatible
>
>
Reviewed-by: Huacai Chen
On Sat, Dec 26, 2020 at 5:13 PM Qing Zhang wrote:
>
> Switch the DT binding to a YAML schema to enable the DT validation.
>
> Signed-off-by: Qing Zhang
> ---
>
> v4:
> - fix warnings/errors about running 'make dt_binding_check'
Reviewed-by: Huacai Chen
On Fri, Dec 25, 2020 at 6:41 PM Qing Zhang wrote:
>
> This is now supported, enable for Loongson systems.
>
> Signed-off-by: Qing Zhang
> ---
>
> v2:
> - Modify CONFIG_SPI_LOONGSON to CONFIG_SPI_LS7A
>
> v3:
> - No changes
>
> v
Hi, Qing
On Fri, Dec 25, 2020 at 6:40 PM Qing Zhang wrote:
>
> The SPI controller has the following characteristics:
>
> - Full-duplex synchronous serial data transmission
> - Support up to 4 variable length byte transmission
> - Main mode support
> - Mode failure generates an error flag and issu
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 3ee36352e26935c7e8145eb4e7ed38b536ca01fc
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/3ee36352e26935c7e8145eb4e7ed38b536ca01fc
Author:Huacai Chen
Hi, Thomas,
On Mon, Nov 16, 2020 at 8:35 PM Thomas Bogendoerfer
wrote:
>
> On Sat, Nov 14, 2020 at 03:34:14PM +0800, Huacai Chen wrote:
> > Hi, Thomas,
> >
> > On Fri, Nov 13, 2020 at 7:13 PM Thomas Bogendoerfer
> > wrote:
> > >
> > > MIPS p
Hi, Roman,
On Sun, Nov 15, 2020 at 6:02 AM Roman Kiryanov wrote:
>
> Hi Hancai,
>
> do you know if CONFIG_GOLDFISH_AUDIO is required for MIPS? I sent a
> patch to retire it.
Not required for MIPS.
Huacai
>
> Regards,
> Roman.
>
> On Sat, Nov 14, 2020 at 12:06 AM 陈华才 wrote:
> >
> > Hi, All,
> >
Hi, Greg,
On Sat, Nov 14, 2020 at 4:16 PM Greg KH wrote:
>
> On Sat, Nov 14, 2020 at 04:06:24PM +0800, 陈华才 wrote:
> > Hi, All,
> >
> > Goldfish RTC works well on MIPS, and QEMU RISC-V emulator use Goldfish
> > as well, so I think we should keep it in kernel.
>
> And more importantly, if you rely
Hi, Thomas,
On Fri, Nov 13, 2020 at 7:13 PM Thomas Bogendoerfer
wrote:
>
> MIPS protection bits are setup during runtime so using defines like
> PAGE_SHARED ignores this runtime changes. Using vm_get_page_prot
> to get correct page protection fixes this.
Is there some visible bugs if without this
Hi, Tiezhu,
On Wed, Nov 4, 2020 at 11:51 AM Tiezhu Yang wrote:
>
> On 11/04/2020 10:00 AM, Huacai Chen wrote:
> > Hi, Tiezhu,
> >
> > On Tue, Nov 3, 2020 at 3:13 PM Tiezhu Yang wrote:
> >> The field LPA of CP0_CONFIG3 register is read only for Loongson64,
Hi, Tiezhu,
On Tue, Nov 3, 2020 at 3:13 PM Tiezhu Yang wrote:
>
> The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
> write operations are meaningless, remove them.
>
> Signed-off-by: Tiezhu Yang
> ---
>
> v2: No changes
> v3: No changes
>
> arch/mips/include/asm/mach-lo
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 1d1e5630de78f7253ac24b92cee6427c3ff04d56
Gitweb:
https://git.kernel.org/tip/1d1e5630de78f7253ac24b92cee6427c3ff04d56
Author:Huacai Chen
AuthorDate:Fri, 11 Sep 2020 18:26:18 +08:00
Committer
s/used/unused/g, but it is too late, I'm sorry.
Huacai
On Tue, Oct 6, 2020 at 7:31 PM Thomas Bogendoerfer
wrote:
>
> On Mon, Oct 05, 2020 at 01:28:46PM +0200, Thomas Bogendoerfer wrote:
> > There are no users of PAGE_USERIO.
> >
> > Signed-off-by: Thomas Bogendoerfer
> > ---
> > arch/mips/incl
Hi, Paolo,
On Thu, Sep 24, 2020 at 2:50 PM Paolo Bonzini wrote:
>
> On 24/09/20 08:31, Huacai Chen wrote:
> > Hi, Sean,
> >
> > On Thu, Sep 24, 2020 at 3:00 AM Sean Christopherson
> > wrote:
> >>
> >> Swap the order of hardware_enable_all() an
kvm_arch_init_vm(). (Maybe I am wrong because I'm not familiar with
VMX/TDX).
Huacai
>
> Cc: Marc Zyngier
> Cc: James Morse
> Cc: Julien Thierry
> Cc: Suzuki K Poulose
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: Huacai Chen
> Cc: Aleksandar Markovic
> C
Hi, Jinyang,
On Fri, Sep 18, 2020 at 2:20 PM Jinyang He wrote:
>
> On 09/17/2020 09:52 PM, Zhou Yanjie wrote:
> > Hello,
> >
> > 在 2020/9/17 下午8:41, Jinyang He 写道:
> >> Hi, Huacai,
> >>
> >>
> >> On 09/16/2020 01:39 PM, Huacai Chen wrot
Hi, Bjorn,
On Tue, Sep 15, 2020 at 4:38 PM Bjorn Helgaas wrote:
>
> On Tue, Sep 15, 2020 at 09:36:13AM +0800, Huacai Chen wrote:
> > Hi, Tiezhu,
> >
> > On Mon, Sep 14, 2020 at 7:25 PM Tiezhu Yang wrote:
> > >
> > > On 09/14/2020 05:46
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