The following commit has been merged into the ras/core branch of tip:
Commit-ID: e1c06d2366e743475b91045ef0c2ce1bbd028cb6
Gitweb:
https://git.kernel.org/tip/e1c06d2366e743475b91045ef0c2ce1bbd028cb6
Author:Gabriele Paoloni
AuthorDate:Fri, 27 Nov 2020 16:18:19
Committer
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 3a866b16fd2360a9c4ebf71cfbf7ebfe968c1409
Gitweb:
https://git.kernel.org/tip/3a866b16fd2360a9c4ebf71cfbf7ebfe968c1409
Author:Gabriele Paoloni
AuthorDate:Fri, 27 Nov 2020 16:18:17
Committer
The following commit has been merged into the ras/core branch of tip:
Commit-ID: e273e6e12ab1db3eb57712bd60655744d0091fa3
Gitweb:
https://git.kernel.org/tip/e273e6e12ab1db3eb57712bd60655744d0091fa3
Author:Gabriele Paoloni
AuthorDate:Fri, 27 Nov 2020 16:18:16
Committer
The following commit has been merged into the ras/core branch of tip:
Commit-ID: d5b38e3d0fdb1a16994b449bc338fb8b26816b07
Gitweb:
https://git.kernel.org/tip/d5b38e3d0fdb1a16994b449bc338fb8b26816b07
Author:Gabriele Paoloni
AuthorDate:Fri, 27 Nov 2020 16:18:18
Committer
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 25bc65d8ddfc17cc1d7a45bd48e9bdc0e729ced3
Gitweb:
https://git.kernel.org/tip/25bc65d8ddfc17cc1d7a45bd48e9bdc0e729ced3
Author:Gabriele Paoloni
AuthorDate:Fri, 27 Nov 2020 16:18:15
Committer
Currently if an MCE happens in user-mode or while the kernel
is copying data from user space, 'kill_it' is used to check
if we can recover the execution of the interrupted task or
not; the flag name however is not much meaningful, hence
rename it to match its goal.
Signed-off-by: Gabrie
Right now in do_machine_check() __mc_scan_banks() triggers
the following call tree:
__mc_scan_banks()->mce_log()->irq_work_queue(&mce_irq_work).
Hence the call of irq_work_queue() below after __mc_scan_banks()
seems redundant. Just remove it.
Signed-off-by: Gabriele Paoloni
Reviewe
where mce_end()
fails.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mce/core.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 32b7099e3511..50e9b0893a92
Right now for LMCE if no_way_out is set mce_panic() is called
regardless of mca_cfg.tolerant. This is not correct as, if
mca_cfg.tolerant = 3, the code should never panic.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mce/core.c | 2 +-
1 file changed, 1
all
severities of all CPUs that entered the MCE handler.
If mce_end() fails, check first if no_way_out is already set and,
if so, stick to it, otherwise use the local worst value.
Cc:
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mce/core.c | 6 --
1 fi
named to kill_current_task
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
Gabriele Paoloni (5):
x86/mce: do not overwrite no_way_out if mce_end() fails
x86/mce: move the mce_panic() call and 'kill_it' assignments to the
right places
x86/mce: for LMCE panic only if m
During the safety analysis that was done in the context of the
ELISA project by the safety architecture working group some
incorrectnesses were spotted.
This patchset proposes some fixes.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
Gabriele Paoloni (4):
x86/mce: do not overwrite
mce_end() fails we first check if no_way_out is already set and
if so we stick to it, otherwise we use the local worst value
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mce/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86
Right now in do_machine_check() we have:
__mc_scan_banks()->mce_log()->irq_work_queue(&mce_irq_work)
hence the call of irq_work_queue() below after __mc_scan_banks()
seems redundant. Just remove it.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mce/
statement where mce_end()
fails
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mce/core.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index b990892c6766
Right now for LMCE if no_way_out is set mce_panic() is called
regardless of mca_cfg.tolerant. This is not correct as if
mca_cfg.tolerant = 3 we should never panic.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Tony Luck
---
arch/x86/kernel/cpu/mce/core.c | 2 +-
1 file changed, 1 insertion
Hi Dann
> -Original Message-
> From: dann frazier [mailto:dann.fraz...@canonical.com]
> Sent: 09 November 2017 16:16
> To: Gabriele Paoloni
> Cc: Catalin Marinas; Will Deacon; Rob Herring; Frank Rowand; Bjorn
> Helgaas; raf...@kernel.org; Arnd Bergmann; linux-arm-kernel
Hi Dann
[...]
> > +
> > +#define START_WORK 0x01
>
> Any reason not to put this in the LPC_ namespace as well?
No, not really. We'll make it consistent in the next patchset
>
> > +/* The minimal nanosecond interval for each query on LPC cycle
> status. */
[...]
> > + * hisilpc_tar
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 07 November 2017 00:23
> To: Gabriele Paoloni
> Cc: catalin.mari...@arm.com; will.dea...@arm.com; robh...@kernel.org;
> frowand.l...@gmail.com; bhelg...@google.com; raf...@kernel.org;
>
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 07 November 2017 00:25
> To: Gabriele Paoloni
> Cc: catalin.mari...@arm.com; will.dea...@arm.com; robh...@kernel.org;
> frowand.l...@gmail.com; bhelg...@google.com; raf...@kernel.org;
>
Hi Bjorn
Many Thanks for reviewing
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 07 November 2017 00:21
> To: Gabriele Paoloni
> Cc: catalin.mari...@arm.com; will.dea...@arm.com; robh...@kernel.org;
> frowand.l...@gmail.com; bhelg.
Hi Randy
> -Original Message-
> From: Randy Dunlap [mailto:rdun...@infradead.org]
> Sent: 27 October 2017 17:44
> To: Gabriele Paoloni; catalin.mari...@arm.com; will.dea...@arm.com;
> robh...@kernel.org; frowand.l...@gmail.com; bhelg...@google.com;
> raf...@kernel.
Hi Corey
Many Thanks for your comments
[...]
> > #define IO_SPACE_LIMIT 0x
> > #endif
> >
> > +#include
>
> This whole thing would be a lot simpler if you had:
>
> #ifdef CONFIG_INDIRECT_PIO
> #define inb logic_inb
> #define outb logic outb
> .
> .
> #endif /* CONFIG_INDIRECT_PIO */
>
Hi David
[...]
> FWIW my thoughts on this are WTF!
>
> Looks to me horribly over complicated and over generalised.
>
> Surely is it could be done the same way that x86 does IO cycles?
No
> So you encode the information into the 'address' the driver passes
> to ioread16() (etc) to allow it to
Added maintainer for drivers/bus/hisi_lpc.c
Signed-off-by: Gabriele Paoloni
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f66488d..b49d4c0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6130,6 +6130,13 @@ F: include/uapi/linux
From: gabriele paoloni
In preparation for having the PCI MMIO helpers to use the new generic
I/O space management(LOGIC_PIO) we need to add the fwnode handler as
extra input parameter.
This patch changes the signature of pci_register_io_range() and of
its callers as needed.
Signed-off-by
From: gabriele paoloni
Currently pci_register_io_range() has only one definition;
therefore there is no use of the __weak attribute.
Signed-off-by: Gabriele Paoloni
Acked-by: Bjorn Helgaas
---
drivers/pci/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci
From: "zhichang.yuan"
Based on the provious patches, this patch supports the ACPI LPC host on
Hip06/Hip07.
Signed-off-by: zhichang.yuan
Signed-off-by: John Garry
Signed-off-by: Gabriele Paoloni
Tested-by: dann frazier
---
drivers/acpi/arm64/acpi_indirectio.c | 3 +
drivers/
From: gabriele paoloni
After introducing the new generic I/O space management(LOGIC_PIO), the
original PCI MMIO relevant helpers need to be updated based on the new
interfaces defined in LOGIC_PIO.
This patch adapts the corresponding code to match the changes introduced
by LOGIC_PIO.
Signed-off
on will be done in a different way from that one of PCI
MMIO. In this way, the I/O 'reg' property of the special ISA/LPC devices
will be parsed correctly.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann #earlier draft
Acked-by: Rob
From: gabriele paoloni
On some platforms(such as Hip06/Hip07), the legacy ISA/LPC devices access
I/O with some special host-local I/O ports known on x86. As their I/O space
are not memory mapped like PCI/PCIE MMIO host bridges, this patch is meant
to support a new class of I/O host controllers
ff-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Acked-by: Rob Herring #dts part
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ++
drivers/bus/Kconfig| 9 +
drivers/bus/Makefile | 1 +
dr
From: gabriele paoloni
This patchset supports the IPMI-bt device attached to the Low-Pin-Count
interface implemented on Hisilicon Hip06/Hip07 SoC.
---
| LPC host
s to either PCI MMIO devices or host-local
I/O peripherals can be unified into the existing I/O accessors defined in
asm-generic/io.h and be redirected to the right device-specific hooks
based on the input logical PIO.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
include/asm
[...]
> >
> > Applied to pci/aer for v4.15, thanks!
> >
> > I rewrote some of the changelog to say "non-fatal" instead of
> > "uncorrectable", since "uncorrectable" also includes fatal errors,
> > and you're not changing those. Take a look and let me know if
> > I broke anything.
>
> Here it is
ch fixes a bug (filed as in the link below)
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197055
Fixes: 6c2b374d7485 ("PCI-Express AER implemetation: AER core and aerdriver")
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
Changes from v2:
- no functional changes
-
Hi Bjorn
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 25 September 2017 19:34
> To: Gabriele Paoloni
> Cc: Linuxarm; liudongdong (C); linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v2] PCIe AER:
Hi Ard
Sorry to reply late on this
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 14 September 2017 15:07
> To: Gabriele Paoloni
> Cc: Lorenzo Pieralisi; Hanjun Guo; Marcin Wojtas; Wangyijing; linux-
> p...@vger.kernel.
Hi Bjorn
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 02 September 2017 18:33
> To: Gabriele Paoloni
> Cc: Linuxarm; liudongdong (C); linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v2] PCIe AER:
Hi Bjorn
Many thanks for looking at this
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 01 September 2017 05:43
> To: Gabriele Paoloni
> Cc: Linuxarm; liudongdong (C); linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> S
ping...
> -Original Message-
> From: Gabriele Paoloni
> Sent: 18 August 2017 12:02
> To: helg...@kernel.org
> Cc: Gabriele Paoloni; Linuxarm; liudongdong (C); linux-
> p...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH v2] PCIe AER: report uncorre
r for non fatal errors.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
Changes from v1:
- now errors are reported only to the fucntions that logged the error
instead of all the functions in the same device.
- the patch subject has changed to match the new implementation
---
Hi Andy
[...]
>
> You may do it on stack. Define your cell statically (but not const)
> and apply resources just before mfd_add_devices() call.
Ok thanks got it
> There are examples in the existing drivers. Intel LPC comes to my mind
> and perhaps PMC (Broxton), though latter has too much othe
Hi Andy
[...]
>
> JFYI: Mika on vacation.
Thanks for letting me know
>
> > I had a look into the MFD framework. If my understanding is correct
> the mfd
> > framework create a platform device for each declared mfd_cell that is
> passed
> > to mfd_add_devices().
>
> Right.
>
> > However ther
+CC Lee Jones
> -Original Message-
> From: Gabriele Paoloni
> Sent: 03 July 2017 17:08
> To: Gabriele Paoloni; Mika Westerberg
> Cc: Rafael J. Wysocki; Lorenzo Pieralisi; Rafael J. Wysocki;
> catalin.mari...@arm.com; will.dea...@arm.com; robh...@kernel.org;
> frowand.
Hi Mika
> -Original Message-
> From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
> ow...@vger.kernel.org] On Behalf Of Gabriele Paoloni
> Sent: 19 June 2017 11:05
> To: Mika Westerberg
> Cc: Rafael J. Wysocki; Lorenzo Pieralisi; Rafael J. Wysocki;
> ca
Hi Bjorn
[...]
++--
> --
> > 2 files changed, 50 insertions(+), 21 deletions(-)
>
> Applied to pci/portdrv for v4.13, thanks!
>
> I tweaked the PME/hotplug no-MSI logic in pcie_init_service_irqs()
> because I thought it was getting hard to read with the negations and
> conj
Hi Mika
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: 19 June 2017 11:02
> To: Gabriele Paoloni
> Cc: Rafael J. Wysocki; Lorenzo Pieralisi; Rafael J. Wysocki;
> catalin.mari...@arm.com; will.dea...@arm.com; robh...@kerne
Hi Rafael, Mika, Lorenzo
> -Original Message-
> From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of
> Rafael J. Wysocki
> Sent: 16 June 2017 13:23
> To: Mika Westerberg
> Cc: Rafael J. Wysocki; Gabriele Paoloni; Lorenzo Pieralisi; Rafael J.
>
Hi Mika
> -Original Message-
> From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
> ow...@vger.kernel.org] On Behalf Of Mika Westerberg
> Sent: 13 June 2017 21:04
> To: Gabriele Paoloni
> Cc: Lorenzo Pieralisi; raf...@kernel.org; Rafael J. Wysocki;
> ca
Hi Mika
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: 13 June 2017 16:10
> To: Gabriele Paoloni
> Cc: Lorenzo Pieralisi; raf...@kernel.org; Rafael J. Wysocki;
> catalin.mari...@arm.com; will.dea...@arm.com; robh...@kerne
Hi Mika
> -Original Message-
> From: Mika Westerberg [mailto:mika.westerb...@linux.intel.com]
> Sent: 13 June 2017 09:49
> To: Lorenzo Pieralisi
> Cc: Gabriele Paoloni; raf...@kernel.org; Rafael J. Wysocki;
> catalin.mari...@arm.com; will.dea...@arm.com; robh...@kerne
Hi Lorenzo, Rafael
> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: 12 June 2017 16:57
> To: Gabriele Paoloni; raf...@kernel.org; Rafael J. Wysocki; Mika
> Westerberg
> Cc: catalin.mari...@arm.com; will.dea...@arm.com;
Hi Lorenzo
Many thanks for reviewing
> -Original Message-
> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
> Sent: 30 May 2017 14:24
> To: Gabriele Paoloni
> Cc: catalin.mari...@arm.com; will.dea...@arm.com; robh...@kernel.org;
> frowand.l...@gmail.com; b
Hi Bjorn
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 26 May 2017 21:58
> To: Gabriele Paoloni
> Cc: catalin.mari...@arm.com; will.dea...@arm.com; robh...@kernel.org;
> frowand.l...@gmail.com; bhelg...@google.com; raf...@kernel.org;
>
Hi Bjorn
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: 26 May 2017 22:20
> To: Gabriele Paoloni
> Cc: catalin.mari...@arm.com; will.dea...@arm.com; robh...@kernel.org;
> frowand.l...@gmail.com; bhelg...@google.com; raf...@kernel.org;
>
[...]
> Hi zhichang.yuan,
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.12-rc2 next-20170525]
> [if your patch is applied to the wrong git tree, please drop us a note
> to help improve the system]
>
> url:https://github.com/0day-ci/linux/
Added maintainer for drivers/bus/hisi_lpc.c
Signed-off-by: Gabriele Paoloni
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9e98464..8fb9006 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6061,6 +6061,14 @@ F: include/uapi/linux
ned-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann #earlier draft
---
drivers/acpi/pci_root.c | 8 ++--
drivers/of/address.c | 5 ++-
drivers/pci/pci.c| 101 ++-
include/asm-generic/
From: gabriele paoloni
This patchset supports the IPMI-bt device attached to the Low-Pin-Count
interface implemented on Hisilicon Hip06/Hip07 SoC.
---
| LPC host
on will be done in a different way from that one of PCI MMIO.
In this way, the I/O 'reg' property of the special ISA/LPC devices will be
parsed correctly.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann #earlier draft
Acked-by: Rob
: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
drivers/acpi/arm64/Makefile| 1 +
drivers/acpi/arm64/acpi_indirect_pio.c | 301 +
drivers/acpi/internal.h| 5 +
drivers/acpi/scan.c| 1 +
include/acpi
From: "zhichang.yuan"
Based on the provious patches, this patch supports the ACPI LPC host on
Hip06/Hip07.
Signed-off-by: zhichang.yuan
Signed-off-by: John Garry
Signed-off-by: Gabriele Paoloni
Tested-by: dann frazier
---
drivers/acpi/arm64/acpi_indirect_pio.c | 3 ++
d
/O accesses to either PCI MMIO devices or host-local
I/O peripherals can be unified into the existing I/O accessors defined in
asm-generic/io.h and be redirected to the right device-specific hooks
based on the input logical PIO.
Signed-off-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
---
i
ff-by: zhichang.yuan
Signed-off-by: Gabriele Paoloni
Acked-by: Rob Herring #dts part
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ++
drivers/bus/Kconfig| 9 +
drivers/bus/Makefile | 1 +
dr
Hi Christoph
> -Original Message-
> From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
> ow...@vger.kernel.org] On Behalf Of Christoph Hellwig
> Sent: 22 May 2017 18:44
> To: Gabriele Paoloni
> Cc: Christoph Hellwig; bhelg...@google.com; helg...@kernel.org;
pcie_port_enable_msix() to use MSI in
case MSI-x allocation fails.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Christoph Hellwig
---
drivers/pci/pcie/portdrv.h | 8 +---
drivers/pci/pcie/portdrv_core.c | 38 --
2 files changed, 25 insertions(+), 21 deletions
From: gabriele paoloni
This patchset:
1) adds support for MSI interrupt vectors to be used for Roor Port services
2) adds support for DPC Root Port service interrupt
The patchset has been tested on Hisilicon Hip08 Chipset
Changes from v4:
- removed meaningless comment
Changes from v3
From: gabriele paoloni
Currently the MSI/MSIx vectors for the root port services are
allocated calling pcie_init_service_irqs(). At the moment these
vectors are only allocated for AER, PME, HP.
This patch allocate an MSI/MSIx vector also for DPC.
Signed-off-by: Liudongdong
Signed-off-by
pcie_port_enable_msix() to use MSI in
case MSI-x allocation fails.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Christoph Hellwig
---
drivers/pci/pcie/portdrv.h | 8 +---
drivers/pci/pcie/portdrv_core.c | 41 +++--
2 files changed, 28 insertions(+), 21 deletions
From: gabriele paoloni
This patchset:
1) adds support for MSI interrupt vectors to be used for Roor Port services
2) adds support for DPC Root Port service interrupt
The patchset has been tested on Hisilicon Hip08 Chipset
Changes from v3:
- removed 2 extra lines at the bottom of comments
From: gabriele paoloni
Currently the MSI/MSIx vectors for the root port services are
allocated calling pcie_init_service_irqs(). At the moment these
vectors are only allocated for AER, PME, HP.
This patch allocate an MSI/MSIx vector also for DPC.
Signed-off-by: Liudongdong
Signed-off-by
Hi Christoph
> -Original Message-
> From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
> ow...@vger.kernel.org] On Behalf Of Christoph Hellwig
> Sent: 21 May 2017 09:33
> To: Gabriele Paoloni
> Cc: bhelg...@google.com; helg...@kernel.org; Linuxarm; linux-
> p..
pcie_port_enable_msix() to use MSI in
case MSI-x allocation fails.
Signed-off-by: Gabriele Paoloni
Reviewed-by: Christoph Hellwig
---
drivers/pci/pcie/portdrv.h | 8 +---
drivers/pci/pcie/portdrv_core.c | 43 -
2 files changed, 30 insertions(+), 21 deletions
From: gabriele paoloni
This patchset:
1) adds support for MSI interrupt vectors to be used for Roor Port services
2) adds support for DPC Root Port service interrupt
The patchset has been tested on Hisilicon Hip08 Chipset
Changes from v2:
- Fixed comment mismatch for function
From: gabriele paoloni
Currently the MSI/MSIx vectors for the root port services are
allocated calling pcie_init_service_irqs(). At the moment these
vectors are only allocated for AER, PME, HP.
This patch allocate an MSI/MSIx vector also for DPC.
Signed-off-by: Liudongdong
Signed-off-by
Hi Christoph
> -Original Message-
> From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
> ow...@vger.kernel.org] On Behalf Of Christoph Hellwig
> Sent: 18 May 2017 10:27
> To: Gabriele Paoloni
> Cc: bhelg...@google.com; helg...@kernel.org; Linuxarm; linux-
> p..
From: gabriele paoloni
This patchset:
1) adds support for MSI interrupt vectors to be used for Roor Port services
2) adds support for DPC Root Port service interrupt
The patchset has been tested on Hisilicon Hip08 Chipset
Changes from v1:
According to comments from Christoph Hellwig in
https
pcie_port_enable_msix() to use MSI in
case MSI-x allocation fails.
Signed-off-by: Gabriele Paoloni
---
drivers/pci/pcie/portdrv.h | 8 ---
drivers/pci/pcie/portdrv_core.c | 46 +
2 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/drivers/pci
From: gabriele paoloni
Currently the MSI/MSIx vectors for the root port services are
allocated calling pcie_init_service_irqs(). At the moment these
vectors are only allocated for AER, PME, HP.
This patch allocate an MSI/MSIx vector also for DPC.
Signed-off-by: Liudongdong
Signed-off-by
Hi Christoph
> -Original Message-
> From: Christoph Hellwig [mailto:h...@infradead.org]
> Sent: 16 May 2017 13:11
> To: Gabriele Paoloni
> Cc: bhelg...@google.com; helg...@kernel.org; Linuxarm; linux-
> p...@vger.kernel.org; lu...@wunner.de; linux-kernel@vger.kernel.o
Hi Christoph
Many thanks for your comments
> -Original Message-
> From: Christoph Hellwig [mailto:h...@infradead.org]
> Sent: 16 May 2017 13:07
> To: Gabriele Paoloni
> Cc: bhelg...@google.com; helg...@kernel.org; Linuxarm; linux-
> p...@vger.kernel.org; lu...@wunne
From: gabriele paoloni
This patchset:
1) adds support for MSI interrupt vectors to be used for Roor Port services
2) adds support for DPC Root Port service interrupt
The patchset has been tested on Hisilicon Hip08 Chipset
Gabriele Paoloni (1):
PCI/portdrv: add support for different MSI
From: gabriele paoloni
Currently the MSI/MSIx vectors for the root port services are
allocated calling pcie_init_service_irqs(). At the moment these
vectors are only allocated for AER, PME, HP.
This patch allocate an MSI/MSIx vector also for DPC.
Signed-off-by: Liudongdong
Signed-off-by
pcie_port_enable_msix() to use MSI in
case MSI-x allocation fails.
Signed-off-by: Gabriele Paoloni
---
drivers/pci/pcie/portdrv.h | 5 +
drivers/pci/pcie/portdrv_core.c | 33 +++--
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/pcie/portdrv.h
Hi Robin and all
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
> ow...@vger.kernel.org] On Behalf Of Robin Murphy
> Sent: 20 March 2017 14:00
> To: Dingtianhong; Catalin Marinas; Will Deacon; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger
vger.kernel.org; Linux PCI; Corey Minyard; Zou Rongrong;
> John Garry; Gabriele Paoloni; kant...@163.com; xuwei (O)
> Subject: Re: [PATCH V8 5/6] ACPI: Support the probing on the devices
> which apply indirect-IO
>
> On Sat, Apr 1, 2017 at 4:16 AM, zhichang.yuan
> wrote:
> >
Hi Marc Many thanks for your comments
> -Original Message-
> From: linuxarm-boun...@huawei.com [mailto:linuxarm-boun...@huawei.com]
> On Behalf Of Marc Zyngier
> Sent: 27 March 2017 09:47
> To: John Garry; Lorenzo Pieralisi; Guohanjun (Hanjun Guo)
> Cc: Rafael J. Wysocki; Yimin (Leo); Greg
Hi Arnd
> -Original Message-
> From: linuxarm-boun...@huawei.com [mailto:linuxarm-boun...@huawei.com]
> On Behalf Of Gabriele Paoloni
> Sent: 16 March 2017 16:14
> To: Arnd Bergmann; Yuanzhichang
> Cc: Mark Rutland; Benjamin Herrenschmidt; Rafael Wysocki; linux-
Rafael Wysocki; Mark Rutland; Linux ARM; ACPI
> Devel Maling List; Lorenzo Pieralisi; Benjamin Herrenschmidt; Linux
> Kernel Mailing List; Linuxarm; devicet...@vger.kernel.org; linux-pci;
> linux-ser...@vger.kernel.org; Corey Minyard; liviu.du...@arm.com; Zou
> Rongrong; John Garr
; p...@vger.kernel.org; linux-ser...@vger.kernel.org; miny...@acm.org;
> liviu.du...@arm.com; zourongr...@gmail.com; John Garry; Gabriele
> Paoloni; zhichang.yua...@gmail.com; kant...@163.com; xuwei (O)
> Subject: Re: [PATCH V7 5/7] ACPI: Delay the enumeration on the devices
> whose dependency has not m
Hi Mark
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: 13 March 2017 10:44
> To: Gabriele Paoloni
> Cc: liudongdong (C); Bjorn Helgaas; Wangzhou (B);
> devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> ker...@vger.ker
Hi Geert
[...]
> > {
> > - .compatible = "hisilicon,pcie-almost-ecam",
> > + .compatible = "hisilicon,pcie-almost-ecam-hip06",
>
> Shouldn't that be "hisilicon,hip06-pcie-almost-ecam"?
>
> > + .data = (void *) &hisi_pcie_platform_ops,
> > + },
> > +
Hi Mark
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: 10 March 2017 17:41
> To: liudongdong (C); Bjorn Helgaas
> Cc: Gabriele Paoloni; Wangzhou (B); devicet...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-kernel@vger.kernel.org
[...]
>
> I will fold the changes into v2 (and I hope other host controllers
> maintainers will follow suit - I do not have enough knowledge of
> all host bridges drivers internals to understand what ioremap calls
> need patching).
Ok great, many thanks!
Gab
>
> Thanks !
> Lorenzo
el.org; linux-a...@vger.kernel.org; Lorenzo
> Pieralisi; Bjorn Helgaas; Gabriele Paoloni; Wangzhou (B)
> Subject: [PATCH 14/20] PCI: hisi: update PCI config space remap
> function
>
> PCI configuration space should be mapped with a memory region type that
> generates on the CPU host
Hi Alex
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
[...]
> >>
> >> I like the extio idea. That allows us to handle all PIO requests on
> >> platforms that don't have native PIO support via different routes
> >> depending on the region they're in. Unfortunately we
Hi Alex thanks for reviewing
[...]
> >
> >>> + * The port size of legacy I/O devices is normally less than
> 0x400.
> >>> + * Defining the I/O range size as 0x400 here should be sufficient
> for
> >>> + * all peripherals under one bus.
> >>> + */
> >>
> >> This comment doesn't make a lot of sense
Hi Arnd
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: 25 November 2016 12:04
> To: Gabriele Paoloni
> Cc: linux-arm-ker...@lists.infradead.org; mark.rutl...@arm.com;
> catalin.mari...@arm.com; linux-...@vger.kernel.org;
> liviu.du
Hi Arnd
Many thanks for your contribution, much appreciated
I have some comments...see inline below
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: 23 November 2016 23:23
> To: linux-arm-ker...@lists.infradead.org
> Cc: Gabriele Paoloni; mark.
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