k on the return value.
Thanks, Marc.
Tested-by: Duc Dang
>
> Fixes: 9c248f8896e6 ("PCI/xgene-msi: Convert to hotplug state machine")
> Cc: Sebastian Andrzej Siewior
> Cc: Duc Dang
> Cc: Bjorn Helgaas
> Cc: Thomas Gleixner
> Cc: sta...@vger.kernel.org
> Signe
00 00 00 02 41 48 50 45 4A 43 4D // SPCRPAHPEJCM
> 0010: 50 72 6F 4C 69 61 6E 74 01 00 00 00 49 4E 54 4C // ProLiantINTL
> 0020: 27 05 16 20 0D 00 00 00 00 08 00 00 00 10 02 1C // '..
> 0030: 00 00 00 00 08 00 6D 00 00 00 03 00 01 02 01 00 // ..m.
> 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 //
>
> Jon.
>
> --
> Computer Architect | Sent from my Fedora powered laptop
>
Regards,
Duc Dang.
On Mon, Dec 5, 2016 at 3:52 PM, Duc Dang wrote:
> Hi Jon,
>
> On Mon, Dec 5, 2016 at 3:27 PM, Jon Masters wrote:
>> Duc, Aleksey, all,
>>
>> I have a question about this...
>>
>> On 12/05/2016 01:51 PM, Duc Dang wrote:
>>> On Mon, Dec 5, 2016 at
Hi Jon,
On Mon, Dec 5, 2016 at 3:27 PM, Jon Masters wrote:
> Duc, Aleksey, all,
>
> I have a question about this...
>
> On 12/05/2016 01:51 PM, Duc Dang wrote:
>> On Mon, Dec 5, 2016 at 5:05 AM, Aleksey Makarov
>> wrote:
>>> Check the 'Register Bit
On Mon, Dec 5, 2016 at 1:53 PM, Bjorn Helgaas wrote:
> On Thu, Dec 01, 2016 at 06:52:23PM -0800, Duc Dang wrote:
>> On Thu, Dec 1, 2016 at 10:33 AM, Bjorn Helgaas wrote:
>
>> I made similar changes in v4 patch. The ECAM quirk will be built when
>> ACPI and PCI_QUIRKS
On Mon, Dec 5, 2016 at 1:20 PM, Bjorn Helgaas wrote:
> On Fri, Dec 02, 2016 at 11:06:30PM -0800, Duc Dang wrote:
>> On Fri, Dec 2, 2016 at 3:39 PM, Bjorn Helgaas wrote:
>
>> > diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
>> > index 8a177a1..a16fc8
t;
> If the driver is other than 16550 the access with is defined
> by the Interface Type field of the SPCR table.
>
> For discussion:
>
> https://lkml.kernel.org/r/7fa523de-3fbb-1566-f521-927143f73...@redhat.com
Tested on X-Gene 1 and X-Gene 2 platforms.
Tested-by: Duc Dang
ard back from Microsoft this morning that they're looking.
Yes, thanks, Jon. It will be nice to have a new 16550 UART type for
those requiring 32-bit access.
>
> Jon.
>
> --
> Computer Architect | Sent from my Fedora powered laptop
>
Regards,
Duc Dang.
this...
> >
> > On 12/01/2016 06:22 PM, Duc Dang wrote:
> > > On Thu, Dec 1, 2016 at 3:07 PM, Bjorn Helgaas wrote:
> > >> On Thu, Dec 01, 2016 at 02:10:10PM -0800, Duc Dang wrote:
> >
> > >>>>> The SoC provide some number of RC bridges,
64-bit #ARM Powered phone
>
>> On Dec 2, 2016, at 02:37, Duc Dang wrote:
>>
>>> On Thu, Dec 1, 2016 at 11:12 PM, Jon Masters wrote:
>>>> On 12/01/2016 09:27 PM, Duc Dang wrote:
>>>> PCIe controllers in X-Gene SoCs is not ECAM compliant: software
>&
On Thu, Dec 1, 2016 at 11:12 PM, Jon Masters wrote:
> On 12/01/2016 09:27 PM, Duc Dang wrote:
>> PCIe controllers in X-Gene SoCs is not ECAM compliant: software
>> needs to configure additional controller's register to address
>> device at bus:dev:function.
>
ch does not scale, it can
only applicable for a specific machine (by checking DMI information to
apply the PNP quirk).
>
> That's all very nasty...
>
> Jon.
>
> On 12/01/2016 11:08 PM, Jon Masters wrote:
>> Hi Bjorn, Duc, Mark,
>>
>> I switched my brain to t
K(2, 0UL), /* off-chip devices */
+ THUNDER_PEM_QUIRK(2, 1UL), /* off-chip devices */
+ THUNDER_ECAM_QUIRK(2, 0UL),
+ THUNDER_ECAM_QUIRK(2, 1UL),
+ THUNDER_ECAM_QUIRK(2, 2UL),
+ THUNDER_ECAM_QUIRK(2, 3UL),
+ THUNDER_ECAM_QUIRK(2, 10UL),
+ THUNDER_ECAM_QUIRK(2, 11UL),
+ THUNDER_ECAM_QUIRK(2, 12UL),
+ THUNDER_ECAM_QUIRK(2, 13UL),
#define XGENE_V1_ECAM_MCFG(rev, seg) \
{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
>
> Jon.
>
> --
> Computer Architect | Sent from my Fedora powered laptop
> ___
> Linaro-acpi mailing list
> linaro-a...@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/linaro-acpi
Regards,
Duc Dang.
On Thu, Dec 1, 2016 at 10:33 AM, Bjorn Helgaas wrote:
> Hi Duc,
>
> On Wed, Nov 30, 2016 at 03:42:53PM -0800, Duc Dang wrote:
>> PCIe controllers in X-Gene SoCs is not ECAM compliant: software
>> needs to configure additional controller's register to address
>
evice.
The quirk will only be applied for X-Gene PCIe MCFG table with
OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
Signed-off-by: Duc Dang
---
v4:
- Rebase on top of pci/ecam tree
- Introduce xgene_get_csr_resource to discover MMIO register space
(per Mark's
On Thu, Dec 1, 2016 at 3:07 PM, Bjorn Helgaas wrote:
> On Thu, Dec 01, 2016 at 02:10:10PM -0800, Duc Dang wrote:
>> On Thu, Dec 1, 2016 at 11:41 AM, Bjorn Helgaas wrote:
>> > On Thu, Dec 01, 2016 at 02:20:53PM -0500, Mark Salter wrote:
>> >> On Thu, 2016-12-01 at 12
On Thu, Dec 1, 2016 at 11:41 AM, Bjorn Helgaas wrote:
> On Thu, Dec 01, 2016 at 02:20:53PM -0500, Mark Salter wrote:
>> On Thu, 2016-12-01 at 12:33 -0600, Bjorn Helgaas wrote:
>> > On Wed, Nov 30, 2016 at 03:42:53PM -0800, Duc Dang wrote:
>
>> > > +static
On Thu, Dec 1, 2016 at 11:17 AM, Jon Masters wrote:
> On 12/01/2016 10:08 AM, Mark Salter wrote:
>> On Wed, 2016-11-30 at 15:42 -0800, Duc Dang wrote:
>
>>> +static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
>>> +{
>>> +struct acpi_de
quirk declares the X-Gene PCIe controller register space as 64KB
fixed memory resource with name "PCIe CSR". This name will be showed
next to the resource range in the output of "cat /proc/iomem".
Signed-off-by: Duc Dang
---
v3:
- Rebase on top of pci/ecam-v6 tree.
- Us
use the PNP0A03 _CRS to report the PCI
> ECAM config space quirk region through a consumer resource keeping in
> mind what I say above (actually I think that's what was done on APM
> firmware initially, for the records).
Just to clarify: APM firmware initially has a _CSR region to declare
the controller register region. We don't know that we need to declare
the reserved space for ECAM until Bjorn pointed out recently (with the
usage of PNP0C02).
I really like this idea about declaring ECAM space and any additional
spaces required for ECAM quirk inside PNP0A03 _CRS. For the firmware
that already shipped, the quirk will need to add additional resources
(for ECAM and other needed regions) into the root-bus. If we decided
to go with this, do we still have time to make additional adjustment
for the current ECAM quirk and the foundation patches before
v4.10-rc1?
>
> Lorenzo
> ___
> Linaro-acpi mailing list
> linaro-a...@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/linaro-acpi
Regards,
Duc Dang.
On Wed, Nov 2, 2016 at 9:53 AM, Bjorn Helgaas wrote:
>
> Hi Duc,
>
> On Tue, Oct 25, 2016 at 06:24:32PM -0700, Duc Dang wrote:
> > PCIe controllers in X-Gene SoCs is not ECAM compliant: software
> > needs to configure additional controller's register to address
&
On Wed, Sep 21, 2016 at 2:22 PM, Bjorn Helgaas wrote:
> On Mon, Sep 19, 2016 at 06:07:37PM -0700, Duc Dang wrote:
>> On Mon, Sep 19, 2016 at 1:06 PM, Bjorn Helgaas wrote:
>> > On Sat, Sep 17, 2016 at 07:24:38AM -0700, Duc Dang wrote:
>
>> This patch only adds
tml,
the series was also modified by Bjorn) to address the limitation
above for X-Gene PCIe controller.
The quirk will only be applied for X-Gene PCIe MCFG table with
OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
Signed-off-by: Duc Dang
---
v2 changes:
1. Get rid of p
mpliant or not. Any
> memory-mapped config space should be reported via some device's _CRS.
>
> The existing x86 practice is to use PNP0C02 devices for this purpose,
> and I think we should just follow that practice.
>
>> For FW that is immutable I really do not see what we can do apart
>> from hardcoding the non-config resources (consumed by a bridge),
>> somehow.
>
> Right. Well, I assume you mean we should hard-code "non-window
> resources consumed directly by a bridge". If firmware in the field is
> broken, we should work around it, and that may mean hard-coding some
> resources.
>
> My point is that the hard-coding should not be buried in a driver
> where it's invisible to the rest of the kernel. If we hard-code it in
> a quirk that adds _CRS entries, then the kernel will work just like it
> would if the firmware had been correct in the first place. The
> resource will appear in /sys/devices/pnp*/*/resources and /proc/iomem,
> and if we ever used _SRS to assign or move ACPI devices, we would know
> to avoid the bridge resource.
Hi Bjorn,
Are you suggesting to add code similar to functions in
linux/drivers/pnp/quirks.c to declare/attach the additional resource
that the host need to have when the resource is not in MCFG table?
>
> Bjorn
Regards,
Duc Dang.
Hi Bjorn,
Thanks for reviewing my RFC patch.
On Mon, Sep 19, 2016 at 1:06 PM, Bjorn Helgaas wrote:
> Hi Duc,
>
> On Sat, Sep 17, 2016 at 07:24:38AM -0700, Duc Dang wrote:
>> PCIe controller in X-Gene SoCs is not ECAM compliant: software
>> needs to configure additional conc
to address the limitation above for X-Gene PCIe controller.
The quirk will only be applied for X-Gene PCIe MCFG table with
OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
Signed-off-by: Duc Dang
---
drivers/acpi/pci_mcfg.c | 32 +
drivers/pci/host/Makefile
On Mon, Sep 12, 2016 at 3:24 PM, Duc Dang wrote:
> On Fri, Sep 9, 2016 at 12:24 PM, Tomasz Nowicki wrote:
>>
>> Some platforms may not be fully compliant with generic set of PCI config
>> accessors. For these cases we implement the way to overwrite CFG accessors
>>
we need another quirk in array.
> +*/
> + pci_mcfg_match_quirks(root, &res, &ops);
> + if (!res.start)
> + return -ENXIO;
> +
> *cfgres = res;
> *ecam_ops = ops;
> return 0;
> @@ -101,6 +164,11 @@ static __init int pci_mcfg_parse(struct
> acpi_table_header *header)
> list_add(&e->list, &pci_mcfg_list);
> }
>
> + /* Save MCFG IDs and revision for quirks matching */
> + memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
> + memcpy(mcfg_oem_table_id, header->oem_table_id,
> ACPI_OEM_TABLE_ID_SIZE);
> + mcfg_oem_revision = header->revision;
> +
> pr_info("MCFG table detected, %d entries\n", n);
> return 0;
> }
> --
> 1.9.1
Regards,
Duc Dang.
tions(-)
> create mode 100644 drivers/pci/host/mcfg-quirks.c
> create mode 100644 drivers/pci/host/mcfg-quirks.h
>
> --
> 1.9.1
>
Regards,
Duc Dang.
<0x0 0x2000 0x0 0x2>;
> interrupts = <0 96 4>,
> <0 97 4>;
> dma-coherent;
Regards,
Duc Dang.
On Wed, Jul 20, 2016 at 3:15 AM, Will Deacon wrote:
> On Tue, Jul 19, 2016 at 01:22:09PM -0700, Duc Dang wrote:
>> On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang wrote:
>> > On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen wrote:
>> >> On Thu, Jul 14, 2016 at 6:16 AM,
On Thu, Jul 14, 2016 at 10:37 AM, Duc Dang wrote:
> On Thu, Jul 14, 2016 at 10:28 AM, Tai Tri Nguyen wrote:
>>
>> Hi Will,
>>
>> On Thu, Jul 14, 2016 at 6:16 AM, Will Deacon wrote:
>> > On Mon, Jul 11, 2016 at 12:05:40PM -0700, Tai Nguyen wrote:
>
ages to patches 1,2 and 4, but then you
> > can route this via the arm-soc tree.
> >
> > Will
>
> I will add the commit messages to these patches 1, 2 and 4 and rout
> this via arm-soc tree.
> CC: Duc (dhd...@apm.com)
I will pull patch 1, 2 and 4 into xgene-next tree and send pull
request to Arnd and Olof.
>
> Thanks,
> --
> Tai
Regards,
Duc Dang.
On Sat, Jul 9, 2016 at 16:15 Paul Gortmaker
wrote:
>
> [Re: [PATCH 14/14] PCI: xgene: make it explicitly non-modular] On 07/07/2016
> (Thu 15:42) Duc Dang wrote:
>
> > On Thu, Jul 7, 2016 at 3:35 PM, Tanmay Inamdar wrote:
> > >
> > >
> > > O
not need?
>> #include
>> #include
>> #include
>> @@ -579,8 +579,4 @@ static struct platform_driver xgene_pcie_driver = {
>> },
>> .probe = xgene_pcie_probe_bridge,
>> };
>> -module_platform_driver(xgene_pcie_driver);
>> -
>> -MODULE_AUTHOR("Tanmay Inamdar ");
>> -MODULE_DESCRIPTION("APM X-Gene PCIe driver");
>> -MODULE_LICENSE("GPL v2");
>> +builtin_platform_driver(xgene_pcie_driver);
>
>
> Copying Duc.
>>
>> --
>> 2.8.4
>>
>
Regards,
Duc Dang.
On Mon, Jun 20, 2016 at 10:17 AM, Christopher Covington
wrote:
> Hi Duc,
>
> On 06/20/2016 05:42 AM, Lorenzo Pieralisi wrote:
>> On Fri, Jun 17, 2016 at 02:37:02PM -0700, Duc Dang wrote:
>>> On Thu, Jun 16, 2016 at 10:48 AM, Lorenzo Pieralisi
>>> wrote:
>&g
On Mon, Jun 20, 2016 at 12:12 PM, Duc Dang wrote:
> On Mon, Jun 20, 2016 at 10:17 AM, Christopher Covington
> wrote:
>> Hi Duc,
>>
>> On 06/20/2016 05:42 AM, Lorenzo Pieralisi wrote:
>>> On Fri, Jun 17, 2016 at 02:37:02PM -0700, Duc Dang wrote:
>>>&
>>>
>>> Gab
>>>
>>
>> I had an internal discussion with jeff and cov before posting on the
>> maillist.
>>
>> I think there is missing info in the email.
>>
>> Usage of oem id + table id + revision is ok.
>>
>> Usage o
pcibios_alloc_irq works fine on X-Gene PCIe
I also tried to remove pcibios_alloc_irq and move its code into
pcibios_enable_device
after pci_enable_resource call and legacy IRQ also works.
Can you also point me to the discussion thread or some info. about the
issue on x86 with [1]?
I want to check
oes not give a valid preprocessing token
> __mcfg_fixup_##oem_id##oem_table_id##dom##bus \
I think the problem is gcc is not happy with quoted string when
processing these tokens
(""QCOM"", the extra "" are added by gcc). So should we not concat
string token
On Tue, Jun 14, 2016 at 4:52 AM, Tomasz Nowicki wrote:
> On 14.06.2016 11:45, Dongdong Liu wrote:
>>
>> Hi Duc
>>
>> 在 2016/6/14 17:00, Duc Dang 写道:
>>>
>>> On Mon, Jun 13, 2016 at 10:51 PM, Dongdong Liu
>>> wrote:
>>>>
>>
On Mon, Jun 13, 2016 at 10:51 PM, Dongdong Liu wrote:
> Hi Duc
>
> 在 2016/6/14 4:57, Duc Dang 写道:
>>
>> On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
>> wrote:
>>>
>>> Hi Dongdong,
>>>
>>> On 06/13/2016 09:02 AM, Dongd
something ARM or Linaro should be doing).
> But I particularly care about X-Gene because I want it to be loved as
> shipping silicon in production systems (Moonshot) that are sitting and
> waiting in the Fedora Phoenix datacenter in large quantity to come
> online if only an upstr
dow iteration
> PCI: tegra: Remove top-level resource from hierarchy
> PCI: tegra: Request host bridge window resources with core function
> PCI: versatile: Request host bridge window resources with core function
> PCI: versatile: Simplify host bridge window iteratio
nd we end-up with whatever is the
> default (edge). You can put whatever you want in the DT, it will be
> ignored.
>
> This series in preparation of these fixes landing in 4.8, where we'll
> be able to do the right thing, and will start noticing stupid things
> coming from the DT.
Hi Marc,
I also see the same warning that David saw. Can you please cc me when
the bug fix series
is available? I will test it out for X-Gene 1 and will need to change
the interrupt setting for timer
events on X-Gene 2 as well.
Regards,
Duc Dang.
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny.
;, /* Secure Phys IRQ */
> -<1 13 0xff01>, /* Non-secure Phys IRQ */
> -<1 14 0xff01>, /* Virt IRQ */
> -<1 15 0xff01>; /* Hyp IRQ */
> + interrupts = <1 0 0x
On Tue, Jun 21, 2016 at 2:26 AM, Lorenzo Pieralisi
wrote:
> On Mon, Jun 20, 2016 at 12:12:24PM -0700, Duc Dang wrote:
>> On Mon, Jun 20, 2016 at 10:17 AM, Christopher Covington
>> wrote:
>> > Hi Duc,
>> >
>> > On 06/20/2016 05:42 AM, Lorenzo Pieralisi
table and not worry about the "PLAT" sub-string match causes the quirk
to be applied unintentionally.
>
> (I'm happy to rip it out, test, and communicate the delta however you'd
> prefer--just let me know.)
>
> Regards,
> Cov
>
> --
> Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
Regards,
Duc Dang.
table and not worry about the "PLAT" sub-string match causes the quirk
to be applied unintentionally.
>
> (I'm happy to rip it out, test, and communicate the delta however you'd
> prefer--just let me know.)
>
> Regards,
> Cov
>
> --
> Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
Regards,
Duc Dang.
On Tue, Jun 21, 2016 at 6:25 AM, Andrew Lunn wrote:
> On Tue, Jun 21, 2016 at 02:02:44AM -0700, Duc Dang wrote:
>> Hi Rob,
>>
>> I got warning on unit_address_vs_reg similar to this
>> https://lkml.org/lkml/2016/3/7/43 when using v4.7-rc2 dtc to build dtb
>> for X
On Tue, Jun 21, 2016 at 2:26 AM, Lorenzo Pieralisi
wrote:
> On Mon, Jun 20, 2016 at 12:12:24PM -0700, Duc Dang wrote:
>> On Mon, Jun 20, 2016 at 10:17 AM, Christopher Covington
>> wrote:
>> > Hi Duc,
>> >
>> > On 06/20/2016 05:42 AM, Lorenzo Pieralisi
due to backward
compatible with old firmware reason (/soc/reboot@1714 as an
example). Is there any other way to avoid the warning?
Regards,
Duc Dang.
On Mon, Jun 20, 2016 at 12:12 PM, Duc Dang wrote:
> On Mon, Jun 20, 2016 at 10:17 AM, Christopher Covington
> wrote:
>> Hi Duc,
>>
>> On 06/20/2016 05:42 AM, Lorenzo Pieralisi wrote:
>>> On Fri, Jun 17, 2016 at 02:37:02PM -0700, Duc Dang wrote:
>>>&
On Mon, Jun 20, 2016 at 10:17 AM, Christopher Covington
wrote:
> Hi Duc,
>
> On 06/20/2016 05:42 AM, Lorenzo Pieralisi wrote:
>> On Fri, Jun 17, 2016 at 02:37:02PM -0700, Duc Dang wrote:
>>> On Thu, Jun 16, 2016 at 10:48 AM, Lorenzo Pieralisi
>>> wrote:
>&g
; MCFG at all - possibly through a _CRS method for a vendor specific
> _HID under the PNP0A03 node ?)
Hi Lorenzo,
For X-Gene: the ECAM space is used to access the configuration space of PCIe
devices, with additional help from controller register to specify the
bus, device and
function num
xt |4 +-
>> arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 40
>> ++--
>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 36 +-
>> 3 files changed, 40 insertions(+), 40 deletions(-)
>
> Acked-by: Rob Herring
Thanks, Rob and Bjorn.
I will pull this patch and the other one on the same series into xgene-next.
Regards,
Duc Dang.
something ARM or Linaro should be doing).
> But I particularly care about X-Gene because I want it to be loved as
> shipping silicon in production systems (Moonshot) that are sitting and
> waiting in the Fedora Phoenix datacenter in large quantity to come
> online if only an upstr
On Tue, Jun 14, 2016 at 4:52 AM, Tomasz Nowicki wrote:
> On 14.06.2016 11:45, Dongdong Liu wrote:
>>
>> Hi Duc
>>
>> 在 2016/6/14 17:00, Duc Dang 写道:
>>>
>>> On Mon, Jun 13, 2016 at 10:51 PM, Dongdong Liu
>>> wrote:
>>>>
>>
On Mon, Jun 13, 2016 at 10:51 PM, Dongdong Liu wrote:
> Hi Duc
>
> 在 2016/6/14 4:57, Duc Dang 写道:
>>
>> On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
>> wrote:
>>>
>>> Hi Dongdong,
>>>
>>> On 06/13/2016 09:02 AM, Dongd
Unit addresses should not have '0x' or leading 0s.
>
>> compatible = "arm,gic-v2m-frame";
>> msi-controller;
>> @@ -159,35 +159,35 @@
>> msi-controller;
>> reg = <0x0 0x9 0x0 0x1000>;
>> };
>> - v2m10: v2m@0xA {
>> + v2m10: v2m@0xa {
>
> and here...
Thanks, Bjorn. Will you have time to post another version that
addresses Rob's comment?
Hi Rob,
If you are fine, I will take these changes into my xgene-next tree for
the next DTS pull request for 4.8 (after your comment is addressed)
Regards,
Duc Dang.
>
> Rob
>>>
>>> Gab
>>>
>>
>> I had an internal discussion with jeff and cov before posting on the
>> maillist.
>>
>> I think there is missing info in the email.
>>
>> Usage of oem id + table id + revision is ok.
>>
>> Usage o
oes not give a valid preprocessing token
> __mcfg_fixup_##oem_id##oem_table_id##dom##bus \
I think the problem is gcc is not happy with quoted string when
processing these tokens
(""QCOM"", the extra "" are added by gcc). So should we not concat
string token
pcibios_alloc_irq works fine on X-Gene PCIe
I also tried to remove pcibios_alloc_irq and move its code into
pcibios_enable_device
after pci_enable_resource call and legacy IRQ also works.
Can you also point me to the discussion thread or some info. about the
issue on x86 with [1]?
I want to check
nd we end-up with whatever is the
> default (edge). You can put whatever you want in the DT, it will be
> ignored.
>
> This series in preparation of these fixes landing in 4.8, where we'll
> be able to do the right thing, and will start noticing stupid things
> coming from the DT.
Hi Marc,
I also see the same warning that David saw. Can you please cc me when
the bug fix series
is available? I will test it out for X-Gene 1 and will need to change
the interrupt setting for timer
events on X-Gene 2 as well.
Regards,
Duc Dang.
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny.
;, /* Secure Phys IRQ */
> -<1 13 0xff01>, /* Non-secure Phys IRQ */
> -<1 14 0xff01>, /* Virt IRQ */
> -<1 15 0xff01>; /* Hyp IRQ */
> + interrupts = <1 0 0x
dow iteration
> PCI: tegra: Remove top-level resource from hierarchy
> PCI: tegra: Request host bridge window resources with core function
> PCI: versatile: Request host bridge window resources with core function
> PCI: versatile: Simplify host bridge window iteratio
On Fri, May 27, 2016 at 3:52 AM, Lorenzo Pieralisi
wrote:
>
> [+ Rafael]
>
> On Thu, May 26, 2016 at 01:49:23PM -0700, Duc Dang wrote:
> > Hi Lorenzo,
> >
> > On Thu, May 26, 2016 at 5:34 AM, Lorenzo Pieralisi
> > wrote:
> > > Hi Duc,
> > &g
Hi Lorenzo,
On Thu, May 26, 2016 at 5:34 AM, Lorenzo Pieralisi
wrote:
> Hi Duc,
>
> On Wed, May 25, 2016 at 04:13:35PM -0700, Duc Dang wrote:
>> On Thu, Feb 25, 2016 at 9:38 AM, Lorenzo Pieralisi
>> wrote:
>> > On Wed, Feb 24, 2016 at 02:28:10PM -0800, Duc Dang wro
On Thu, Feb 25, 2016 at 9:38 AM, Lorenzo Pieralisi
wrote:
> On Wed, Feb 24, 2016 at 02:28:10PM -0800, Duc Dang wrote:
>> On Wed, Feb 24, 2016 at 8:16 AM, Marc Zyngier wrote:
>> > On 24/02/16 16:09, Mark Salter wrote:
>> >> On Tue, 2016-02-09 at 17:56 -0800, Duc
een tested on Cavium ThunderX server. Any help in reviewing and
> testing is very appreciated.
I tried this series on APM X-Gene platforms (with ECAM fix-up quirk
added) and PCIe works fine.
Regards,
Duc Dang.
>
> v6 -> v7
> - drop quirks handling
> - changes for ACPI companion an
On Wed, May 11, 2016 at 2:33 AM, Linus Walleij wrote:
> On Tue, May 3, 2016 at 9:53 AM, Duc Dang wrote:
>
>> This patch enables DWAPB GPIO controller support on X-Gene
>> platforms in ACPI boot mode.
>>
>> Signed-off-by: Duc Dang
>> ---
>> This pa
This patch enables DWAPB GPIO controller support on X-Gene
platforms in ACPI boot mode.
Signed-off-by: Duc Dang
---
This patch needs to be applied on top of for-next branch
of linux-gpio tree.
---
drivers/gpio/gpio-dwapb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio
On Sun, May 1, 2016 at 1:25 AM, Linus Walleij wrote:
> On Sat, Apr 30, 2016 at 10:49 PM, Duc Dang wrote:
>
>> This patch enables ACPI support for X-Gene GFC GPIO driver.
>>
>> Signed-off-by: Duc Dang
>
> Patch applied.
Thanks, Linus.
>
> Duc do you have
This patch enables ACPI support for X-Gene GFC GPIO driver.
Signed-off-by: Duc Dang
---
drivers/gpio/gpio-xgene.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpio/gpio-xgene.c b/drivers/gpio/gpio-xgene.c
index 0dc9161..c00c408 100644
--- a/drivers/gpio/gpio-xgene.c
s has been tested on Cavium ThunderX server. Any help in reviewing and
> testing is very appreciated.
Hi Tomasz,
I changed X-Gene ECAM fixup code to follow the new ECAM APIs and my
X-Gene PCIe on Mustang board works fine with this series.
Thanks and regards,
Duc Dang.
>
> v5 -> v6
&
On Wed, Feb 10, 2016 at 6:28 AM, Arnd Bergmann wrote:
> On Tuesday 09 February 2016 17:49:44 Duc Dang wrote:
>> X-Gene PCIe controller does not fully support ECAM.
>> This patch adds required ECAM fixup to allow X-Gene
>> PCIe controller to be functional in ACPI boot mode
On Mon, Feb 22, 2016 at 8:03 AM, Bjorn Helgaas wrote:
>
> On Sat, Feb 20, 2016 at 1:47 PM, Duc Dang wrote:
> > On Tue, Feb 9, 2016 at 5:56 PM, Duc Dang wrote:
> >> This patch makes pci-xgene-msi driver ACPI-aware and provides
> >> MSI capability for X-Gene v1 PCIe
On Fri, Feb 12, 2016 at 7:39 PM, Duc Dang wrote:
>
> Mailbox device tree node for APM X-Gene platform.
Hi Jassi,
Will you take this patch to your mailbox tree or you want me to
include it into my git pull request to Olof/Arnd (arm-soc tree)?
Regards,
Duc Dang.
>
> Signed-off-
On Wed, Feb 24, 2016 at 8:16 AM, Marc Zyngier wrote:
> On 24/02/16 16:09, Mark Salter wrote:
>> On Tue, 2016-02-09 at 17:56 -0800, Duc Dang wrote:
>>> This patch makes pci-xgene-msi driver ACPI-aware and provides
>>> MSI capability for X-Gene v1 PCIe controllers in ACP
On Tue, Feb 9, 2016 at 5:56 PM, Duc Dang wrote:
> This patch makes pci-xgene-msi driver ACPI-aware and provides
> MSI capability for X-Gene v1 PCIe controllers in ACPI boot mode.
Hi Bjorn,
Are you planning to take this patch into your tree?
Regards,
Duc Dang.
>
> Signed-off-
On Fri, Feb 12, 2016 at 7:39 PM, Duc Dang wrote:
> APM X-Gene SoC has a mailbox controller that provides
> communication mechanism for X-Gene Arm64 cores to communicate
> with X-Gene SoC's Cortex M3 (SLIMpro) processor.
>
> X-Gene mailbox controller provides 8 mailbox c
o GIC
EOI feature. We have a new Tianocore firmware that correctly does GIC
fix-up to avoid the hang, but it may take a while before we release
it. In the mean time, you can comment out following likes of code in
function gic_v2_acpi_init of drivers/irqchip/irq-gic.c file to
continue booting in ACPI mode:
/*
* Disable split EOI/Deactivate if HYP is not available. ACPI
* guarantees that we'll always have a GICv2, so the CPU
* interface will always be the right size.
*/
/*
if (!is_hyp_mode_available())
static_key_slow_dec(&supports_deactivate);
*/
Regards,
Duc Dang.
Mailbox device tree node for APM X-Gene platform.
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
---
Changes since v5:
- None
Changes since v4:
- Rebase over v4.5-rc1
- Change node name to mailbox@1054
Changes since v3:
- Rebase over v4.4
arch/arm64/boot
X-Gene mailbox controller provides 8 mailbox channels, with
each channel has a dedicated interrupt line.
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
---
Changes since v5:
- Add description for struct slimpro_mbox_chan
and struct slimpro_mbox
Changes since v4
ction definition
- Use module_platform_driver instead of subsys_initcall
- Minor coding stype clean up
Changes since v1:
- Add ACPI support
- Use defines for reg offset
Duc Dang (3):
mailbox: Add support for APM X-Gene platform mailbox driver
Documentation: mailbox: Add
This adds the APM X-Gene SLIMpro mailbox device tree
node documentation.
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
Acked-by: Rob Herring
---
Changes since v5:
- None
Changes since v4:
- Rebase over v4.5-rc1
- Fix number of total interrupts in
introduction
On Wed, Feb 10, 2016 at 6:41 AM, Mathieu Poirier
wrote:
> On 9 February 2016 at 20:46, Duc Dang wrote:
>> On Tue, Feb 9, 2016 at 8:40 AM, Mathieu Poirier
>> wrote:
>>> On 8 February 2016 at 15:04, Duc Dang wrote:
>>>> X-Gene mailbox controller provide
On Wed, Feb 10, 2016 at 9:08 AM, Marc Zyngier wrote:
> On 10/02/16 01:56, Duc Dang wrote:
>> This patch makes pci-xgene-msi driver ACPI-aware and provides
>> MSI capability for X-Gene v1 PCIe controllers in ACPI boot mode.
>>
>> Signed-off-by: Duc Dang
&
On Tue, Feb 9, 2016 at 8:40 AM, Mathieu Poirier
wrote:
> On 8 February 2016 at 15:04, Duc Dang wrote:
>> X-Gene mailbox controller provides 8 mailbox channels, with
>> each channel has a dedicated interrupt line.
>>
>> Signed-off-by: Feng Kan
>> Signed-off-by:
This patch makes pci-xgene-msi driver ACPI-aware and provides
MSI capability for X-Gene v1 PCIe controllers in ACPI boot mode.
Signed-off-by: Duc Dang
---
drivers/pci/host/pci-xgene-msi.c | 35 ---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a
igned-off-by: Duc Dang
---
drivers/pci/host/pci-xgene.c | 130 ++-
1 file changed, 127 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index ae00ce2..5d3f74e 100644
--- a/drivers/pci/host/pci-xgene.c
ype clean up
Changes since v1:
- Add ACPI support
- Use defines for reg offset
Duc Dang (3):
mailbox: Add support for APM X-Gene platform mailbox driver
Documentation: mailbox: Add APM X-Gene SLIMpro mailbox dts
documentation
arm64: dts: mailbox device tree node for APM X
Mailbox device tree node for APM X-Gene platform.
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
---
Changes since v4:
- Rebase over v4.5-rc1
- Change node name to mailbox@1054
Changes since v3:
- Rebase over v4.4
arch/arm64/boot/dts/apm/apm-storm.dtsi | 14
X-Gene mailbox controller provides 8 mailbox channels, with
each channel has a dedicated interrupt line.
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
---
Changes since v4:
- Rebase over v4.5-rc1
- Fix section mistmatch warning by removing
__init in slimpro_mbox_probe
This adds the APM X-Gene SLIMpro mailbox device tree
node documentation.
Signed-off-by: Feng Kan
Signed-off-by: Duc Dang
Acked-by: Rob Herring
---
Changes since v4:
- Rebase over v4.5-rc1
- Fix number of total interrupts in
introduction text
- Change node name
esting is very appreciated.
Hi Tomasz,
I tested your tree with APM X-Gene v1 and X-Gene v2 platforms and PCIe
came up fine on both platforms (with X-Gene ECAM fixup patch that I
will post separately). Thanks for your work and please feel free to
add my Tested-by.
Regards,
Duc Dang.
>
>
Hi Jassi,
On Fri, Jan 15, 2016 at 6:57 PM, Duc Dang wrote:
> X-Gene mailbox controller provides 8 mailbox channels, with
> each channel has a dedicated interrupt line.
Did you have a chance to look into this version 4 of my mail-box patch?
Regards,
Duc Dang.
>
> Signed-off-
On Wed, Jan 20, 2016 at 1:06 AM, Marc Zyngier wrote:
> Hi Duc,
>
> On Tue, 19 Jan 2016 11:12:15 -0800
> Duc Dang wrote:
>
>> On Sun, Sep 13, 2015 at 4:14 AM, Marc Zyngier wrote:
>> >
>> > The GICv2 architecture mandates that the two 4kB GIC regions a
t;
> url:
> https://github.com/0day-ci/linux/commits/Duc-Dang/mailbox-Add-support-for-APM-X-Gene-platform-mailbox-driver/20160116-110535
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next
> config: arm64-allyesconfig (attached as .config)
> reproduce:
>
; I don't have access to such system. Any helps are appreciated.
Hi Suravee,
I tested your v2m-multiframe-v6 branch with APM X-Gene 2 that has
multiple GICv2m frames and it worked.
Please feel free to add:
Tested-by: Duc Dang
>
> Thanks,
> Suravee
>
> Changes from V5: (https
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