在 2018/10/11 23:57, Keith Busch 写道:
On Thu, Oct 11, 2018 at 08:26:18AM -0700, Bjorn Helgaas wrote:
From: Bjorn Helgaas
Previously we enabled AER error reporting only for Switch Ports that were
enumerated prior to registering the AER service driver. Switch Ports
enumerated after AER driver
Hi Bjorn
commit 15a6711649915ca3e9d1086dc88ff4b616b99aac
Author: Bjorn Helgaas
Date: Tue Oct 9 17:25:25 2018 -0500
PCI/AER: Enable reporting for ports enumerated after AER driver registration
Previously we enabled AER error reporting only for Switch Ports that were
enumerated pr
在 2017/11/9 3:13, Tyler Baicar 写道:
Currently the GHES code only calls into the AER driver for
recoverable type errors. This is incorrect because errors of
other severities do not get logged by the AER driver and do not
get exposed to user space via the AER trace event. So, call
into the AER driv
在 2017/4/27 1:24, Jingoo Han 写道:
On Wednesday, April 26, 2017 6:54 AM, Dongdong Liu wrote;
Tested-by: Dongdong Liu
I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599
netcard.
Thank you for testing these patches. HiSilicon PCIe may use Designware-based
PCIe
Tested-by: Dongdong Liu
I tested the patchset on HiSilicon ARM64 D05 board.It works ok with 82599
netcard.
Thanks,
Dongdong
在 2017/4/25 14:40, Jon Masters 写道:
On 04/19/2017 12:48 PM, Lorenzo Pieralisi wrote:
On some platforms (ie ARM/ARM64) ioremap fails to comply with the PCI
Hi Ming
The latest patchset is [PATCH v11 00/15] PCI: ARM64 ECAM quirks
You can get them from
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git (pci/ecam)
Thanks
Dongdong
在 2016/12/22 16:31, Ming Lei 写道:
Hi Dongdong,
On Tue, Nov 22, 2016 at 8:08 PM, Dongdong Liu wrote:
This
Hi Tomasz
在 2016/11/23 9:44, Dongdong Liu 写道:
Hi Tomasz
在 2016/11/22 20:32, Tomasz Nowicki 写道:
Hi Dongdong,
On 22.11.2016 13:08, Dongdong Liu wrote:
The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID&segment to look
Hi Tomasz
在 2016/11/22 20:32, Tomasz Nowicki 写道:
Hi Dongdong,
On 22.11.2016 13:08, Dongdong Liu wrote:
The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID&segment to look for and returns
the RC address resource. Use PNP
rc base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.
Signed-off-by: Dongdong Liu
Signed-off-by: Gabriele Paoloni
---
MAINTAINERS | 1 +
drivers/acpi/pci_mcfg.c | 13 +
drivers/pci/host/Kconfig
e of PNP0A03 instead of
hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
Arnd comments.
v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.
Dongdong Liu (2):
PC
0C02
resource belong to.
Signed-off-by: Dongdong Liu
Signed-off-by: Tomasz Nowicki
---
drivers/pci/pci-acpi.c | 69 ++
drivers/pci/pci.h | 4 +++
2 files changed, 73 insertions(+)
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
i
Hi Rafael
Many Thanks for your review.
在 2016/11/19 6:00, Rafael J. Wysocki 写道:
On Fri, Nov 18, 2016 at 10:22 AM, Dongdong Liu wrote:
The acpi_get_rc_resources() is used to get the RC register address that can
not be described in MCFG. It takes the _HID&segment to look for and outputs
th
to
Arnd comments.
v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers.
Dongdong Liu (2):
PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers
rc base
addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
2. New entry in common quirk array.
Signed-off-by: Dongdong Liu
Signed-off-by: Gabriele Paoloni
---
MAINTAINERS | 1 +
drivers/acpi/pci_mcfg.c | 13
drivers/pci/host/Kconfig
0C02
resource belong to.
Signed-off-by: Dongdong Liu
Signed-off-by: Tomasz Nowicki
---
drivers/pci/pci-acpi.c | 71 ++
drivers/pci/pci.h | 4 +++
2 files changed, 75 insertions(+)
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
i
turn -ENOMEM;
ret = acpi_get_rc_resources("HISI0081", root->segment, res);
if (ret) {
dev_err(&adev->dev, "can't get rc base address");
return ret;
}
reg_base = devm_ioremap(&adev->dev, res->start, resource_size(res));
Hi Bjorn
在 2016/11/17 7:00, Bjorn Helgaas 写道:
On Mon, Nov 14, 2016 at 05:33:20PM -0600, Bjorn Helgaas wrote:
On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:
PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any
Hi Bjorn
在 2016/11/17 3:31, Bjorn Helgaas 写道:
On Wed, Nov 16, 2016 at 07:59:38PM +0800, Dongdong Liu wrote:
Hi Bjorn
Many Thanks for your review
在 2016/11/15 7:33, Bjorn Helgaas 写道:
On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:
PCIe controller in Hip05/HIP06/HIP07 SoCs is
Hi Bjorn
Many Thanks for your review
在 2016/11/15 7:33, Bjorn Helgaas 写道:
On Wed, Nov 09, 2016 at 05:14:57PM +0800, Dongdong Liu wrote:
PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we
needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
.../devi
resses from PNP0C02 as subdevice of PNP0A03 instead of
hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
Arnd comments.
v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers
Dongdo
rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.
Signed-off-by: Dongdong Liu
Signed-off-by: Gabriele Paoloni
---
MAINTAINERS | 1 +
drivers/acpi/pci_mcfg.c | 13
drivers/pci/host/Kconfig | 8
Hi Bjorn
Thanks for your review.
在 2016/11/3 7:40, Bjorn Helgaas 写道:
On Thu, Oct 20, 2016 at 11:10:34AM +0800, Dongdong Liu wrote:
PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we
Hi Lorenzo
Many thanks for your review.
在 2016/10/22 0:08, Lorenzo Pieralisi 写道:
On Fri, Oct 21, 2016 at 02:12:44PM +0800, Dongdong Liu wrote:
[...]
+static int hisi_pcie_init(struct pci_config_window *cfg)
+{
+ int ret;
+ struct acpi_device *adev = to_acpi_device(cfg->par
Hi Rafael
Thanks for your review.
在 2016/10/20 20:27, Rafael J. Wysocki 写道:
On Thu, Oct 20, 2016 at 5:10 AM, Dongdong Liu wrote:
PCIe controller in Hip05/HIP06/HIP07 SoCs is not ECAM compliant.
It is non ECAM only for the RC bus config space;for any other bus
underneath the root bus we
needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
.../devi
A03 instead of
hardcode the addresses.
- modify hisi_pcie_acpi_rd_conf/hisi_pcie_acpi_wr_conf() according to
Arnd comments.
v1 -> v2:
- rebase against Tomasz RFC V5 quirk mechanism
- add ACPI support for the HiSilicon Hip07 SoC PCIe controllers
Dongdong Liu (2):
PCI: hisi: Add ECAM suppo
rc base
addresses from PNP0C02 as subdevice of PNP0A03.
2. New entry in common quirk array.
Signed-off-by: Dongdong Liu
Signed-off-by: Gabriele Paoloni
---
MAINTAINERS | 1 +
drivers/acpi/pci_mcfg.c | 15
drivers/pci/host/Kconfig | 8
Hi Tomasz
在 2016/9/13 14:32, Tomasz Nowicki 写道:
Hi Liu,
On 13.09.2016 04:36, Dongdong Liu wrote:
Hi Tomasz
在 2016/9/10 3:24, Tomasz Nowicki 写道:
Some platforms may not be fully compliant with generic set of PCI config
accessors. For these cases we implement the way to overwrite CFG
accessors
having it in MCFG.
{ "OEM_ID", "OEM_TABLE_ID", , , , &boo_ops,
DEFINE_RES_MEM(START, SIZE) },
pci_generic_ecam_ops and MCFG entries will be used for platforms
free from quirks.
Signed-off-by: Tomasz Nowicki
Signed-off-by: Dongdong Liu
Signed-off-by: Chri
Hi Rafael
在 2016/9/2 7:38, Rafael J. Wysocki 写道:
On Thursday, September 01, 2016 11:23:42 AM Dongdong Liu wrote:
在 2016/9/1 6:56, Rafael J. Wysocki 写道:
On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote:
Add specific quirks for PCI config space accessors.This involves:
1. New
Hi Arnd
在 2016/9/1 22:02, Arnd Bergmann 写道:
2. We need to backward compatible with the old dt way config access as below
code,
so we have to call hisi_pcie_common_cfg_read() when accessing the RC config
space.
For this, we have to call hisi_pcie_common_cfg_read().
drivers/pci/host/pcie-hisi
Hi Arnd
在 2016/9/1 15:41, Arnd Bergmann 写道:
On Thursday, September 1, 2016 10:05:29 AM CEST Dongdong Liu wrote:
在 2016/8/31 19:45, Arnd Bergmann 写道:
On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote:
+
+/* HipXX PCIe host only supports 32-bit config access */
+int
在 2016/9/1 6:56, Rafael J. Wysocki 写道:
On Wednesday, August 31, 2016 07:48:14 PM Dongdong Liu wrote:
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping
在 2016/8/31 19:48, Arnd Bergmann 写道:
On Wednesday, August 31, 2016 7:48:14 PM CEST Dongdong Liu wrote:
+static struct hisi_rc_res rc_res[] = {
+ {
+ HIP05,
+ {
+ DEFINE_RES_MEM(0xb007, SZ_4K),
+ DEFINE_RES_MEM
在 2016/8/31 19:45, Arnd Bergmann 写道:
On Wednesday, August 31, 2016 7:48:12 PM CEST Dongdong Liu wrote:
+
+/* HipXX PCIe host only supports 32-bit config access */
+int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int size,
+ u32 *val)
+{
+ u32
needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
.../devi
re-architect the Hip05/Hip06 host controllers driver to prepare
for the ACPI based driver.
The common functions used also by the ACPI driver have been grouped
into a new "common" file.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
MAINTAINERS
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.
Signed-off-by: Dongdong Liu
Signed-off-by: Gabriele Paoloni
ers
Dongdong Liu (3):
PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for
ACPI
PCI: hisi: Add ECAM support for devices that are not RC
PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers
.../devicetree/bindings/pci/hisilicon-pcie.txt | 15 +-
MAINTAIN
252 insertions(+), 57 deletions(-)
create mode 100644 drivers/pci/host/mcfg-quirks.c
create mode 100644 drivers/pci/host/mcfg-quirks.h
Based on the patchset, tested on HiSilicon D03 board with intel 82599 net card.
It worked OK.
Tested-by: Dongdong Liu
Thanks
Dongdong
re-architect the Hip05/Hip06 host controllers driver to prepare
for the ACPI based driver.
The common functions used also by the ACPI driver have been grouped
into a new "common" file.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
MAINTAINERS
needed in preparation for the ACPI based driver
to allow both DT and ACPI drivers to use the same BIOS
(that configure the Designware iATUs).
This commit doesn't break backward compatibility with
previous non-ECAM platforms.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Dongdong Liu
---
.../devi
Add specific quirks for PCI config space accessors.This involves:
1. New initialization call hisi_pcie_acpi_init() to get RC config resource
with hardcoded range address and setup ecam mapping.
2. New entry in common quirk array.
Signed-off-by: Dongdong Liu
Signed-off-by: Gabriele Paoloni
platforms(not RC).
- adds the HiSilicon ACPI specific quirks.
This patchset is base on Tomasz RFC V4 quirk mechanism:
https://lkml.org/lkml/2016/6/28/165
Dongdong Liu (3):
PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for
ACPI
PCI: hisi: Add ECAM support
board may be as below comments:
-Original Message-
From: Dongdong Liu [mailto:liudongdo...@huawei.com]
Sent: Monday, July 04, 2016 4:44 PM
To: Po Liu; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
devicet...@vger.kernel.org
Cc
Hi Po
I found a problem with the similar patch. as the below log.
[4.287060] pci :80:00.0: quirk_aer_interrupt dev->irq 416
[4.293778] pcieport :80:00.0: pci_device_probe in
[4.299605] pcieport :80:00.0: of_irq_parse_pci() failed with rc=-22
[4.307209] pcieport :8
在 2016/6/14 16:24, Po Liu 写道:
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer interrupt with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Hi Duc
在 2016/6/14 17:00, Duc Dang 写道:
On Mon, Jun 13, 2016 at 10:51 PM, Dongdong Liu wrote:
Hi Duc
在 2016/6/14 4:57, Duc Dang 写道:
On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
wrote:
Hi Dongdong,
On 06/13/2016 09:02 AM, Dongdong Liu wrote:
diff --git a/drivers/acpi
Hi Duc
在 2016/6/14 4:57, Duc Dang 写道:
On Mon, Jun 13, 2016 at 8:47 AM, Christopher Covington
wrote:
Hi Dongdong,
On 06/13/2016 09:02 AM, Dongdong Liu wrote:
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index d3c3e85..49612b3 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b
= pci_ecam_map_bus,
.read = foo_ecam_config_read,
.write = foo_ecam_config_write,
}
};
DECLARE_ACPI_MCFG_FIXUP(&foo_pci_ops, , ,
, );
Signed-off-by: Tomasz Nowicki
Signed-off-by: Dongdong Liu
---
drivers/acpi/pci_mcfg.c
From: Tomasz Nowicki
pci_generic_ecam_ops is used by default. Since there are platforms
which have non-compliant ECAM space we need to overwrite these
accessors prior to PCI buses enumeration. In order to do that
we call pci_mcfg_get_ops to retrieve pci_ecam_ops structure so that
we can use prope
This series bases on pending ACPI PCI support for ARM64:
https://lkml.org/lkml/2016/6/10/706
Quirk handling relies on an idea of matching MCFG OEM ID and OEM TABLE ID
(the ones from standard header of MCFG table). Linker section is used
so that quirks can be registered using special macro (see pat
the bootup log which contains PCIe host and Intel 82599 networking card
part.
Tested-by: Dongdong Liu
Loading driver at 0x0006D473000 EntryPoint=0x0006DE80100
Loading driver at 0x0006D473000 EntryPoint=0x0006DE80100
EFI stub: Booting Linux Kernel...
EFI stub: Using DTB from configuration tabl
82599 networking card
part.
Tested-by: Dongdong Liu
EFI stub: Booting Linux Kernel...
EFI stub: Using DTB from configuration table
EFI stub: Exiting boot services and installing virtual address map...
GMAC ExitBootServicesEvent
SMMU ExitBootServicesEvent
[0.00] Booting Linux on physical
Hi Tomasz
I used the patchset and added "PATCH V6 11/13 specic quirks", tested on
HiSilicon D02 board but met the below problem.
[2.614115] [] hisi_pcie_init+0x6c/0x1ec
[2.619571] [] pci_ecam_create+0x130/0x1ec
[2.625209] [] pci_acpi_scan_root+0x160/0x218
[2.631096] [] acpi_pci_
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