, and leads to
"unable to handle page fault" BUG.
Closes: https://lore.kernel.org/all/20250516131246.6244-1-00107...@163.com/
Signed-off-by: David Wang <00107...@163.com>
Acked-by: Suren Baghdasaryan
---
kernel/module/main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel
At 2025-05-20 00:03:16, "Suren Baghdasaryan" wrote:
>On Sun, May 18, 2025 at 3:12 AM David Wang <00107...@163.com> wrote:
>>
>> When module load failed after memory for codetag sections ready,
>
>nit: s/ready/is ready
>
>> codetag section memory wa
lead to
"unable to handle page fault" BUG.
Closes: https://lore.kernel.org/all/20250516131246.6244-1-00107...@163.com/
Signed-off-by: David Wang <00107...@163.com>
---
kernel/module/main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/module/main.c b/kernel/mod
@infradead.org;
> sta...@vger.kernel.org; t...@linutronix.de; tony.l...@intel.com;
> torva...@linux-foundation.org; David Wang ; Ashok
> Raj
> Topic: Re: Re: Re: [tip:x86/urgent] x86/mce: Ensure offline CPUs don' t
> participate in rendezvous process
>
> On Thu, May 30, 2019 at
Commit-ID: 987ddbe4870b53623d76ac64044c55a13e368113
Gitweb: https://git.kernel.org/tip/987ddbe4870b53623d76ac64044c55a13e368113
Author: David Wang
AuthorDate: Thu, 27 Dec 2018 16:41:50 +0800
Committer: Ingo Molnar
CommitDate: Fri, 19 Apr 2019 19:28:06 +0200
x86/power: Optimize C3
cores which share some caches with the
idling core.
Signed-off-by: David Wang
Reviewed-by: Thomas Gleixner
Changes from v2 to v3:
*1, Replace "c->x86_mask" with "c->x86_stepping".
Changes from v1 to v2:
* 1, Add some Family/Model/Stepping contrains to let this
> -Original Mail-
> Sender: Borislav Petkov [mailto:b...@alien8.de]
> Time: 2018年6月26日 22:30
> Receiver: David Wang
> CC: tony.l...@intel.com; mi...@redhat.com; t...@linutronix.de;
> h...@zytor.com; x...@kernel.org; linux-kernel@vger.kernel.org;
> linux-e...@vg
New Centaur CPU support CMCI mechanism, which is compatible with INTEL CMCI.
Signed-off-by: David Wang
Changes from v1 to v2:
*1, add vendor check for Centaur CPU in cmci_supported.
*2, Only call intel_init_cmci for Centaur CPU in mce_intel_feature_init
function.
---
arch/x86/Kconfig
> -Original Mail-
> Sender: Borislav Petkov [mailto:b...@alien8.de]
> Time: 2018年6月1日 17:38
> Receiver: David Wang
> CC: tony.l...@intel.com; mi...@redhat.com; t...@linutronix.de;
> h...@zytor.com; gre...@linuxfoudation.org; x...@kernel.org;
> linux-kernel@vge
Newer Centaur support CMCI mechanism, which is compatible with INTEL CMCI.
Signed-off-by: David Wang
---
arch/x86/Kconfig | 12
arch/x86/kernel/cpu/mcheck/mce.c | 6 ++
2 files changed, 18 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index
For new Centaur CPUs the ucode will take care of the preservation of cache
coherence
between CPU cores in C-states regardless of how deep the C-states are. So, it
is not
necessary to flush the caches in software befor entering C3.
Signed-off-by: David Wang
Changes from v2 to v3:
*1, Replace
Commit-ID: 807e9bc8e2fe6b4907f9f77fd073f7ef5073af29
Gitweb: https://git.kernel.org/tip/807e9bc8e2fe6b4907f9f77fd073f7ef5073af29
Author: David Wang
AuthorDate: Thu, 3 May 2018 10:32:45 +0800
Committer: Thomas Gleixner
CommitDate: Sun, 13 May 2018 16:14:24 +0200
x86/CPU: Move
Commit-ID: a2aa578fec8c29436bce5e6c15e1e31729d539a3
Gitweb: https://git.kernel.org/tip/a2aa578fec8c29436bce5e6c15e1e31729d539a3
Author: David Wang
AuthorDate: Thu, 3 May 2018 10:32:46 +0800
Committer: Thomas Gleixner
CommitDate: Sun, 13 May 2018 16:14:24 +0200
x86/Centaur: Report
Commit-ID: 606e20959ef49f22cddb611f2cefef8e6501e3dd
Gitweb: https://git.kernel.org/tip/606e20959ef49f22cddb611f2cefef8e6501e3dd
Author: David Wang
AuthorDate: Thu, 3 May 2018 10:32:45 +0800
Committer: Thomas Gleixner
CommitDate: Sun, 13 May 2018 12:06:12 +0200
x86/CPU: Move
Commit-ID: 5a19009043fcffd1591b04a588d53336a66855d5
Gitweb: https://git.kernel.org/tip/5a19009043fcffd1591b04a588d53336a66855d5
Author: David Wang
AuthorDate: Thu, 3 May 2018 10:32:46 +0800
Committer: Thomas Gleixner
CommitDate: Sun, 13 May 2018 12:06:13 +0200
x86/Centaur: Report
Commit-ID: 2cc61be60e37b1856a97ccbdcca3e86e593bf06a
Gitweb: https://git.kernel.org/tip/2cc61be60e37b1856a97ccbdcca3e86e593bf06a
Author: David Wang
AuthorDate: Thu, 3 May 2018 10:32:44 +0800
Committer: Thomas Gleixner
CommitDate: Sun, 13 May 2018 12:06:12 +0200
x86/CPU: Make
Commit-ID: 13e8582245267b872dc6eb4ab695fffc797d99f5
Gitweb: https://git.kernel.org/tip/13e8582245267b872dc6eb4ab695fffc797d99f5
Author: David Wang
AuthorDate: Wed, 25 Apr 2018 18:33:39 +0800
Committer: Thomas Gleixner
CommitDate: Sun, 6 May 2018 12:46:25 +0200
x86/MCE: Enable MCE
() to make
CPU and cache topology information available and correct.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/centaur.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 80d5110..c265494 100644
--- a/arch/x86/kerne
used to report correct CPU/Cache topology by using the
functions defined in the first and the second patch;
David Wang (3):
x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores
x86/cpu/intel_cacheinfo: include cpu_detect_cache_size in
init_intel_cacheinfo
x86/Centaur: Report
intel_num_cpu_cores() is a static defination in intel.c which can't be used by
other files. Define another function called detect_num_cpu_cores() in common.c
to replace this function.
Signed-off-by: David Wang
---
arch/x86/include/asm/processor.h | 1 +
arch/x86/kernel/cpu/common.c
Clean up the silly cpu_detect_cache_sizes() calling by including the
cpu_detect_cache_sizes() inside the init_intel_cacheinfo().
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/intel.c | 8 +---
arch/x86/kernel/cpu/intel_cacheinfo.c | 6 ++
2 files changed, 7 insertions
> -Original Mail-
> Sender: Borislav Petkov [mailto:b...@alien8.de]
> Time: 2018年4月30日 17:48
> Receiver: David Wang
> CC: tony.l...@intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; gre...@linuxfoundation.org; x...@kernel.org; linux-
> ker...@vge
> -Original Mail-
> Sender: Thomas Gleixner [mailto:t...@linutronix.de]
> Time: 2018年4月26日 19:56
> Receiver: David Wang
> CC: mi...@redhat.com; h...@zytor.com; gre...@linuxfoundation.org;
> x...@kernel.org; linux-kernel@vger.kernel.org; brucechang@via-
>
() to make
CPU and cache topology information avaliable and correct
Signed-off-by: David Wang
Changes from v2 to v3:
*1 define new detect_num_cpu_cores() in common.c to replace the original
intel_num_cpu_cores;
*2 move cpu_detect_cache_sizes inside init_intel_cacheinfo.
Changes from v1 to v
> -Original Mail-
> Sender: Thomas Gleixner [mailto:t...@linutronix.de]
> Time: 2018年4月26日 17:12
> Receiver: David Wang
> CC: mi...@redhat.com; h...@zytor.com; gre...@linuxfoundation.org;
> x...@kernel.org; linux-kernel@vger.kernel.org; brucechang@via-
>
Newer Centaur multi-core CPU also support MCE broadcasting to all cores. But
no Centaur special code tell this truth to kernel.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck
Newer Centaur support CMCI mechnism, which is compatible with INTEL CMCI.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 38ccab8..f9a7295 100644
--- a
from __mcheck_cpu_apply_quirks to
mce_centaur_feature_init according to request from Boris.
Changes from v1 to v2:
* Capatilize 'Centaur' in the comments
David Wang (2):
x86/mce: new Centaur CPU support MCE broadcasting
x86/mce: add CMCI support for Centaur CPUs
arch/x86/kernel/
einfo() to
make CPU and cache topology information avaliable and correct.
Signed-off-by: David Wang
Changes from v1 to v2:
*1 replace centaur_num_cpu_cores with early_init_centaur_mc according to
suggestions from tglx;
*2 call cpu_detect_cache_sizes when init_intel_cacheinfo returns 0. For
some
> -Original Mail-
>Sender: Thomas Gleixner [mailto:t...@linutronix.de]
> Time: 2018年4月17日 18:16
> Receiver: David Wang
> CC: mi...@redhat.com; h...@zytor.com; mi...@kernel.org;
> x...@kernel.org; linux-kernel@vger.kernel.org; brucechang@via-
> alliance.com;
Commit-ID: 60882cc159e1416fb1d17210de60d4a3ba04e613
Gitweb: https://git.kernel.org/tip/60882cc159e1416fb1d17210de60d4a3ba04e613
Author: David Wang
AuthorDate: Fri, 20 Apr 2018 16:29:28 +0800
Committer: Thomas Gleixner
CommitDate: Fri, 20 Apr 2018 12:08:17 +0200
x86/Centaur: Initialize
Centaur CPU has some intel compatible capabilities,include PMC and some
CPU virtualization capabilities. These capabilities should be initialized
in the centaur init function.
Signed-off-by: David Wang
Changes from v1 to v2:
*1, move some defines outside the centaur_detect_vmx_virtcap;
*2
> -Original Mail-
> Sender: Thomas Gleixner [mailto:t...@linutronix.de]
> Time: 2018/4/17 18:19
> Receiver: David Wang
> CC: mi...@redhat.com; h...@zytor.com; mi...@kernel.org;
> gre...@linuxfoundation.org; x...@kernel.org; linux-
> ker...@vger.kernel.org; brucec
> -Original Mail-
> Sender: Thomas Gleixner [mailto:t...@linutronix.de]
> Time : 2018/4/17 18:16
> Receiver: David Wang
> CC: mi...@redhat.com; h...@zytor.com; mi...@kernel.org;
> x...@kernel.org; linux-kernel@vger.kernel.org; brucechang@via-
> alliance.com;
> -邮件原件-
> 发件人: Borislav Petkov [mailto:b...@alien8.de]
> 发送时间: 2018年4月16日 21:28
> 收件人: David Wang
> 抄送: tony.l...@intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; linux-e...@vger.kernel.org; linux-
> ker...@vger.kernel.org; brucec
> -邮件原件-
> 发件人: Christoph Hellwig [mailto:h...@infradead.org]
> 发送时间: 2018年4月16日 20:34
> 收件人: David Wang
> 抄送: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> gre...@linuxfoundation.org; x...@kernel.org; linux-
> ker...@vger.kernel.org; brucech...@via-a
This patch is used to tell kernel that new VIA HDAC controller also
support no-snoop path.
Signed-off-by: David Wang
---
sound/pci/hda/hda_intel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 96143df..439e8e9
PCI bridges integrated in new VIA chipset/SoC have no DAC issue.
Enable DAC for the platforms with these chipset/SoC can improve DMA performance
about
20% when DRAM size > 4GB.
Signed-off-by: David Wang
---
arch/x86/kernel/pci-dma.c | 22 ++
1 file changed, 22 inserti
New Centaur CPU(Family > 6) supprt Random Number Generator, but can't
support MSR_VIA_RNG. Just like VIA Nano.
Signed-off-by: David Wang
---
drivers/char/hw_random/via-rng.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/char/hw_random/via-rng.c b/driv
> -邮件原件-
> 发件人: David Wang [mailto:davidw...@zhaoxin.com]
> 发送时间: 2018年4月8日 17:36
> 收件人: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> mi...@kernel.org; gre...@linuxfoundation.org; x...@kernel.org;
> linux-kernel@vger.kernel.org
> 抄送: brucech...@via
We add this patch to show correct HW features(arch_perfmon, tpr_shadow,
vnmi, flexpriority, ept and vpid) when user execute "cat /proc/cpuinfo".
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/centaur.c | 49 +++
1 file changed, 49 insertion
> -邮件原件-
> 发件人: Borislav Petkov [mailto:b...@alien8.de]
> 发送时间: 2018年4月4日 19:18
> 收件人: David Wang
> 抄送: tony.l...@intel.com; t...@linutronix.de; mi...@redhat.com;
> h...@zytor.com; x...@kernel.org; linux-e...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Bruce C
This patch is used to support multi-core Centaur CPU. After using this
patch, we can get correct CPU topology and correct cache topology.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/centaur.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/x86/kernel/cpu
This patch is used to tell the kernel that newer Centaur CPU support CMCI.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index c3db7ce..361d95e 100644
--- a
e comments
David Wang (2):
x86/mce: new Centaur CPUs support MCE broadcasting
x86/mce: add CMCI support for centaur CPUs
arch/x86/kernel/cpu/mcheck/mce.c | 12
1 file changed, 12 insertions(+)
--
1.9.1
This patch is used to tell the kernel that newer Centaur CPU support
MCE broadcasting.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index
This patch set is to provide MCA support on new Centaur CPU.
The first patch is used to tell the kernel that newer Centaur CPU support
MCE broadcasting.
The second patch is used to tell the kernel that newer Centaur CPU support
CMCI.
David Wang (2):
x86/mce: new centaur CPUs support MCE
This patch is used to tell the kernel that centaur CPUs support CMCI
mechanism which is compatible with INTEL CMCI.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck
This patch is used to tell the kernel that newer Centaur CPU support MCE
broadcasting.
Signed-off-by: David Wang
---
arch/x86/kernel/cpu/mcheck/mce.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index
For new Centaur CPUs the ucode will take care of the preservation of
cache coherence between CPU cores in C-states and the other CPU cores
regardless of how deep the C-states are, so it is not necessary to
flush the caches in software before entering C3.
Signed-off-by: David Wang
Changes from
New centaur CPUs(Familiy == 7) also support this cpu temperature sensor.
Change from v2 to v3:
*replace "goto" with "if...else.." according to suggestion from Guenter
Change from v1 to v2:
*fixed the wrong if condition in patch v1.
Signed-off-by: David Wang
--
Newer centaur CPUs(Family == 7) also support this cpu temperature sensor.
Signed-off-by: David Wang
---
drivers/hwmon/via-cputemp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/hwmon/via-cputemp.c b/drivers/hwmon/via-cputemp.c
index 07a0cb0..2f5bd50 100644
--- a/drivers
Signed-off-by: David Wang
---
drivers/hwmon/via-cputemp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/hwmon/via-cputemp.c b/drivers/hwmon/via-cputemp.c
index 07a0cb0..aa0d040 100644
--- a/drivers/hwmon/via-cputemp.c
+++ b/drivers/hwmon/via-cputemp.c
@@ -136,6 +136,11
core entering C3 state is not
needed too. Because the chipset will automatically do this operation.
Signed-off-by: David Wang
---
arch/x86/kernel/acpi/cstate.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index
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