M5Stack are releasing a new widget based on the
SigmaStar SSD202D. We have some support for the
SSD202D so lets add a dts for it.
Link: https://m5stack-store.myshopify.com/products/unitv2-ai-camera-gc2145
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/Makefile| 1
Add a compatible for the M5Stack UnitV2 that is based on the
SigmaStar SSD202D (inifinity2m).
Signed-off-by: Daniel Palmer
---
Documentation/devicetree/bindings/arm/mstar/mstar.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml
b
else to help with cleaning
up and pushing the commits for these SoCs.
Link: https://m5stack-store.myshopify.com/products/unitv2-ai-camera-gc2145
Daniel Palmer (3):
dt-bindings: vendor-prefixes: Add vendor prefix for M5Stack
dt-bindings: arm: mstar: Add compatible for M5Stack UnitV2
ARM: dts
M5Stack make various modules for STEM, Makers, IoT.
Their UnitV2 is based on a SigmaStar SSD202D SoC which
we already have some minimal support for so add a
prefix in preparation for UnitV2 board support.
Link: https://m5stack.com/
Signed-off-by: Daniel Palmer
---
Documentation/devicetree
Hi Miquel,
On Wed, 7 Apr 2021 at 17:02, Miquel Raynal wrote:
> You may look at micron_8_ecc_get_status() helper to guide you. But
> IMHO, if there are 0-3 bf, you should probably assume there were 3 bf
> and return 3, if there were 4, return 4, if it's uncorrectable return
> -EBADMSG otherwise -E
Hi Arnd,
On Thu, 1 Apr 2021 at 20:04, Arnd Bergmann wrote:
> I found this is still in patchwork as not merged, and I have not
> seen a replacement. Marking all eight patches as 'changes requested' now,
> please resend.
Understood. I will resend.
Thanks,
Daniel
Hi Miquel,
Sorry for the constant pestering on this..
On Tue, 23 Mar 2021 at 23:06, Miquel Raynal wrote:
> > # nandbiterrs -i /dev/mtd1
> > incremental biterrors test
> > Successfully corrected 0 bit errors per subpage
> > Inserted biterror @ 0/5
> > Read reported 4 corrected bit errors
> > ECC
Hi Miquel,
On Tue, 23 Mar 2021 at 23:06, Miquel Raynal wrote:
> >
> > # nandbiterrs -i /dev/mtd1
> > incremental biterrors test
> > Successfully corrected 0 bit errors per subpage
> > Inserted biterror @ 0/5
> > Read reported 4 corrected bit errors
> > ECC failure, invalid data despite read succe
Hi Miquel,
On Tue, 23 Mar 2021 at 19:32, Miquel Raynal wrote:
> You can run nandbiterrs -i /dev/mtdX
>
> You'll see if there is ECC correction or not (and its level).
These are results I get for both of the nandbiterrs tests.
# nandbiterrs -i /dev/mtd1
incremental biterrors test
Successfully co
Hi Miquel,
On Tue, 23 Mar 2021 at 03:32, Miquel Raynal wrote:
> > I think this shows that the datasheet is right in that the complete 64
> > bytes of "spare area" is usable.
> > I have no idea where it puts the ECC though. :)
>
> Argh, I don't like when hardware tries to be smart.
I'm sort of wo
Hi Miquel,
Sorry for the resend. Gmail randomly switched to HTML email so the
original version seems to have bounced.
On Mon, 15 Feb 2021 at 20:16, Miquel Raynal wrote:
> > "2. Spare area 800H to 83FH is all available for user.
> > ECC parity codes are programmed in
> > additional space and not
On Fri, 12 Mar 2021 at 01:11, Mark-PK Tsai wrote:
> Why irq could accept either?
As the irq intc has no way to clear it's triggered state (no eoi) it
must just pass the signal through instead of latching it?
Otherwise it would latch once and never again right? That's what I
really didn't understa
Hi Mark-PK.
On Thu, 11 Mar 2021 at 12:12, Mark-PK Tsai wrote:
> For a fiq controller, the input edge signal will be convert to level and
> keep the interrupt status until we do EOI operation.
> That means if a rising edge input if trigger the ouput line will keep high
> until we clear the interru
Hi Mark-PK,
On Mon, 8 Mar 2021 at 23:30, Mark-PK Tsai wrote:
> From: Daniel Palmer
> >On Mon, 8 Mar 2021 at 15:05, Mark-PK Tsai wrote:
> >> +static int mst_irq_chip_set_type(struct irq_data *data, unsigned int type)
> > > +{
> >> + if
Hi Mark-PK,
On Mon, 8 Mar 2021 at 15:05, Mark-PK Tsai wrote:
> +static int mst_irq_chip_set_type(struct irq_data *data, unsigned int type)
> +{
> + if (type != IRQ_TYPE_LEVEL_LOW && type != IRQ_TYPE_LEVEL_HIGH)
> + return -EINVAL;
> +
Does this mean we can't do rising or fall
_device_irqs.
> And all the irqs of Mstar intc are masked by default when the IP powered on.
>
>
> Best regards,
> Mark-PK Tsai
>
>
> -Original Message-
> From: Marc Zyngier [mailto:m...@kernel.org]
> Sent: Sunday, March 7, 2021 2:28 AM
> To: Daniel Palmer
>
Hi Mark-PK,
I'm trying to understand the logic behind the changes.
It seems like the polarity of interrupts is always the same between
the MStar intc and the GIC? Low level interrupts are handled in the
mstar intc and become high level interrupts to the GIC?
I think for the Mstar MSC313(e) and Sig
All of the ARCH_MSTARV7 chips have an MPLL as the source for
peripheral clocks so select MSTAR_MSC313_MPLL.
Signed-off-by: Daniel Palmer
---
arch/arm/mach-mstar/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig
index
All of the currently known MStar/SigmaStar ARMv7 SoCs have at least
one MPLL and it seems to always be at the same place so add it to
the base dtsi.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-v7.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts
This series is just 3 small patches that got left behind
when the MPLL driver was merged.
Link:
https://lore.kernel.org/linux-arm-kernel/20210211052206.2955988-1-dan...@0x0f.com/
Daniel Palmer (3):
ARM: mstar: Select MSTAR_MSC313_MPLL
ARM: mstar: Add the external clocks to the base dsti
not usable.
The RTC node is disabled by default and should be enabled at the board
level if the RTC input is wired up.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-v7.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/b
Hi Rob's bot
On Wed, 24 Feb 2021 at 04:34, Rob Herring wrote:
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.example.dts:19:18:
> fatal error: dt-bindings/clock/mstar-msc313-mpll.h: No such file or directory
>19 | #include
> |
The infinity3 has a slightly higher max frequency
compared to the infinity so extend the OPP table.
Co-authored-by: Willy Tarreau
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity3.dtsi | 58 ++
1 file changed, 58 insertions(+)
diff --git a/arch/arm
Add an OPP table for the inifinity chips so
that cpu frequency scaling can happen.
Co-authored-by: Willy Tarreau
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/mstar
Add an OPP table for mercury5 so that cpu frequency scaling can
happen.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi
b/arch/arm/boot/dts/mstar
The second core also sources it's clock from the CPU PLL.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi
b/arch/arm/boot/dts/mstar-infinity2m.dtsi
index 6d4d1d2
The CPU clock is sourced from the CPU PLL.
Link cpupll to the cpu so that frequency scaling can happen.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-v7.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index
All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same
place so add it to the base dtsi.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-v7.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index
Signed-off-by: Daniel Palmer
---
drivers/clk/mstar/Kconfig | 7 +
drivers/clk/mstar/Makefile| 1 +
drivers/clk/mstar/clk-msc313-cpupll.c | 228 ++
3 files changed, 236 insertions(+)
create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c
di
Add a binding description for the MStar/SigmaStar CPU PLL block.
Signed-off-by: Daniel Palmer
---
.../bindings/clock/mstar,msc313-cpupll.yaml | 45 +++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml
diff
This series adds a scrappy driver for the PLL that generates
the cpu clock on MStar/SigmaStar ARMv7 SoCs.
Unfortunately there isn't much documentation for this thing
so there are few magic values and guesses.
This needs to come after the MPLL DT changes.
Daniel Palmer (8):
dt-bindings
Hi Arnd and Olof,
On Thu, 11 Feb 2021 at 14:22, Daniel Palmer wrote:
> Daniel Palmer (7):
> dt-bindings: clk: mstar msc313 mpll binding header
> dt-bindings: clk: mstar msc313 mpll binding description
> clk: fixed: add devm helper for clk_hw_register_fixed_factor()
> cl
Hi Miquel,
On Mon, 15 Feb 2021 at 20:16, Miquel Raynal wrote:
> But a changelog should always be added when you change something
> between two versions. And the changelog can be located below the three
> dashes ("---") without being part of the final commit message, it does
> not need to be in a
Hi Stephen,
On Mon, 15 Feb 2021 at 05:48, Stephen Boyd wrote:
> BTW, it would be nice to expose this driver to compile testing instead
> of putting it behind ARCH_MSTARTV7. Can we have this patch?
I like that idea. I'll send a patch.
Thanks,
Daniel
Hi Miquel,
On Mon, 15 Feb 2021 at 19:24, Miquel Raynal wrote:
>
> Can you please add a changelog here when you send a new version of a
> patch?
Sorry, I was going to add a cover letter but elsewhere got told that
one isn't needed for a single patch..
Basically I changed FS35ND01G to FS35ND01G-S
Add support for the Foresee FS35ND01G-S1Y2 manufactured by Longsys.
Signed-off-by: Daniel Palmer
Link:
https://datasheet.lcsc.com/szlcsc/2008121142_FORESEE-FS35ND01G-S1Y2QWFI000_C719495.pdf
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c| 1 +
drivers/mtd/nand/spi
All of the currently known MStar/SigmaStar ARMv7 SoCs have at least
one MPLL and it seems to always be at the same place so add it to
the base dtsi.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-v7.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts
not usable.
The RTC node is disabled by default and should be enabled at the board
level if the RTC input is wired up.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-v7.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/b
s the MPLL block found in the MSC313/MSC313E but
there is no documentation this chip so the register descriptions for
the another MStar chip the MST786 were used as they seem to match.
Signed-off-by: Daniel Palmer
---
MAINTAINERS | 1 +
drivers/clk/Kc
All of the ARCH_MSTARV7 chips have an MPLL as the source for
peripheral clocks so select MSTAR_MSC313_MPLL.
Signed-off-by: Daniel Palmer
---
arch/arm/mach-mstar/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig
index
Add a binding description for the MStar/SigmaStar MPLL clock block.
Signed-off-by: Daniel Palmer
---
.../bindings/clock/mstar,msc313-mpll.yaml | 46 +++
MAINTAINERS | 1 +
2 files changed, 47 insertions(+)
create mode 100644
Documentation
Add a devm helper for clk_hw_register_fixed_factor() so that drivers that
internally
register fixed factor clocks for things like dividers don't need to manually
unregister
them on remove or if probe fails.
Signed-off-by: Daniel Palmer
---
drivers/clk/clk-fixed-factor.c
Simple header to document the relationship between the MPLL outputs
and which divider they come from.
Output 0 is missing because it should not be consumed.
Signed-off-by: Daniel Palmer
Acked-by: Rob Herring
---
MAINTAINERS | 1 +
include/dt-bindings/clock
ed on Stephen's
feedback.
Daniel Palmer (7):
dt-bindings: clk: mstar msc313 mpll binding header
dt-bindings: clk: mstar msc313 mpll binding description
clk: fixed: add devm helper for clk_hw_register_fixed_factor()
clk: mstar: MStar/SigmaStar MPLL driver
ARM: mst
Hi Stephen,
On Wed, 10 Feb 2021 at 11:29, Stephen Boyd wrote:
> The child clks should be using clk_parent_data to point to the parent
> clks through DT. That way the name of the clk doesn't matter except for
> debug purposes.
I think I get it now. I was using of_clk_parent_fill() to get the
pare
Hi Hector,
On Wed, 10 Feb 2021 at 20:49, Hector Martin wrote:
> > Yeah, just don't use an imaginary dummy index for the reg. Use a real
> > register offset from a clock controller instance base, and a register
> > bit offset too if needed.
>
> I mean for fixed input clocks without any particular
-gpio";
>#gpio-cells = <2>;
>reg = <0x207800 0x200>;
>gpio-controller;
This is correct. The compatible string dropped the e at some point and
I must have missed the example.
Thanks for the fix.
Reviewed-by: Daniel Palmer
Hi Adrian,
On Mon, 11 Jan 2021 at 18:17, John Paul Adrian Glaubitz
wrote:
>
> Hi Daniel!
> > On Sat, 9 Jan 2021 at 07:56, Arnd Bergmann wrote:
> >> * 68000/68328 (Dragonball): these are less capable than the
> >> 68020+ or the Coldfire MCF5xxx line and similar to the 68360
> >> that was remo
Hi Arnd,
On Sat, 9 Jan 2021 at 07:56, Arnd Bergmann wrote:
> * 68000/68328 (Dragonball): these are less capable than the
> 68020+ or the Coldfire MCF5xxx line and similar to the 68360
> that was removed in 2016.
I have some patches for the DragonBall series to enable SPI etc there,
some patc
Hi Miquel,
On Mon, 4 Jan 2021 at 23:17, Miquel Raynal wrote:
> Perhaps giving the link of the datasheet here makes sense.
Noted. I'll put that into v2.
> > +#define SPINAND_MFR_LONGSYS 0xcd
>
> Nitpick: I personally prefer uppercase hex numbers.
>
Noted.
> > + NAND_M
Hi Johan,
On Mon, 4 Jan 2021 at 19:32, Johan Hovold wrote:
> Also, would you mind posting the "lsusb -v" output for this device for
> reference?
The lsusb from busybox on this system doesn't support the -v option it seems.
Here is the output from /sys/kernel/debug/usb/devices:
T: Bus=01 Lev=0
Add support for the Foresee FS35ND01G manufactured by Longsys.
Signed-off-by: Daniel Palmer
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c| 1 +
drivers/mtd/nand/spi/longsys.c | 45 ++
include/linux/mtd/spinand.h| 1 +
4 files
ied to write anything yet.
The datasheet for this chip is linked. If someone that actually
knows what they're doing could take a look and point out my
mistakes that would be great.
Link:
https://datasheet.lcsc.com/szlcsc/2008121142_FORESEE-FS35ND01G-S1Y2QWFI000_C719495.pdf
Daniel Palmer (1):
Add a vendor id for LongSung and a product id for the M5710 module.
Signed-off-by: Daniel Palmer
---
drivers/usb/serial/option.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 2c21e34235bb..2666e061c38d 100644
--- a
dts.
Signed-off-by: Daniel Palmer
---
.../dts/mstar-infinity-breadbee-common.dtsi | 49 +++
.../mstar-infinity-msc313-breadbee_crust.dts | 1 +
.../dts/mstar-infinity3-msc313e-breadbee.dts | 1 +
3 files changed, 51 insertions(+)
create mode 100644 arch/arm/boot/dts/mstar
Hi Stephen,
On Mon, 21 Dec 2020 at 03:44, Stephen Boyd wrote:
>
> Quoting Daniel Palmer (2020-12-19 22:35:41)
> > Hi Stephen,
> >
> > On Sun, 20 Dec 2020 at 12:39, Stephen Boyd wrote:
> > > > + clock-output-names:
> > > > +minItems: 8
&
Hi Stephen,
On Mon, 21 Dec 2020 at 03:43, Stephen Boyd wrote:
> Can be part of the same series.
Ok. I have added a small patch that adds devm_clk_hw_register_fixed_factor().
I'll send that in the v2 once the clock names issue is resolved.
Thanks,
Daniel
Hi Stephen,
On Sun, 20 Dec 2020 at 13:36, Stephen Boyd wrote:
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index da8fcf147eb1..b758aae17ab8 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -124,3 +124,4 @@ endif
> > obj-$(CONFIG_ARCH_ZX)
Hi Stephen,
On Sun, 20 Dec 2020 at 12:39, Stephen Boyd wrote:
> > + clock-output-names:
> > +minItems: 8
> > +maxItems: 8
> > +description: |
> > + This should provide a name for the internal PLL clock and then
> > + a name for each of the divided outputs.
>
> Is this neces
Hi all,
>[PATCH 1/7]
Sorry, this isn't actually a 1/7 it's 1/1. I forgot to fix the subject
before sending.
Thanks,
Daniel
dts.
Signed-off-by: Daniel Palmer
---
.../dts/mstar-infinity-breadbee-common.dtsi | 47 +++
.../mstar-infinity-msc313-breadbee_crust.dts | 1 +
.../dts/mstar-infinity3-msc313e-breadbee.dts | 1 +
3 files changed, 49 insertions(+)
create mode 100644 arch/arm/boot/dts/mstar
The prefix for honestar should come before honeywell.
Fixes: 43181b5d8072 ("dt-bindings: vendor-prefixes: Add honestar vendor prefix")
Link:
https://lore.kernel.org/linux-arm-kernel/cafr9pxmwoeuhha-kdel1ys8bwvovrt43mxxyy1j+hgbxwpu...@mail.gmail.com/
Signed-off-by: Dan
Hi Arnd,
On Thu, 10 Dec 2020 at 23:28, Arnd Bergmann wrote:
> > I did think about this and I did this with the clk mux driver I
> > haven't pushed yet. In that case there is a random lump of registers
> > with some muxes mixed into it so I decided to make the lump a syscon
> > and then have a nod
Hi Andy,
On Thu, 10 Dec 2020 at 23:22, Andy Shevchenko wrote:
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> Perhaps ordered?
Ok. I did try to find some rules on includes, mainly what should be
included even though it's included in an
Hi Arnd,
On Thu, 10 Dec 2020 at 02:45, Arnd Bergmann wrote:
> Daniel, please send patches on top of this series to address Rob's
> comments.
Will do. On the enabled method one I had a question for Rob so I'll
wait for a reply to that and then send the fixes.
Sorry about the trouble caused.
Than
Hi Rob,
On Thu, 10 Dec 2020 at 01:34, Rob Herring wrote:
> > + "^honestar,.*":
> > +description: Honestar Technologies Co., Ltd.
>
> Alphabetical order please.
Sorry about that. I intended to do that but apparently don't know the
alphabet anymore..
Thanks,
Daniel
Hi Rob,
On Thu, 10 Dec 2020 at 01:35, Rob Herring wrote:
> On Tue, Dec 01, 2020 at 10:43:21PM +0900, Daniel Palmer wrote:
> > This adds a YAML description of the smpctrl node needed by the
> > platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus.
>
> You n
Hi Arnd,
On Thu, 10 Dec 2020 at 06:58, Arnd Bergmann wrote:
> These seem to just be contiguous ranges, so I probably would have
> suggested describing them as separate gpio controllers to avoid
> all the complexity with the names. As Linus already merged the
> driver into the gpio tree, I won't c
Hi Paul and others,
Sorry to hijack this but I actually want to do something similar to
this in some other drivers.
The targets I'm working with have only 64MB of ram so I want to remove
code wherever possible.
Is there any reason to do it like this instead of wrapping the whole
unneeded of_device
Hi Linus,
On Sun, 6 Dec 2020 at 06:43, Linus Walleij wrote:
> OK finished!
> Patches 1, 2 & 3 applied to the GPIO tree for v5.11.
Awesome! Thank you Linus. :)
Arnd and Olof: Sorry for being a noob.. Is there anything I need to do
for patches 4 and 5 (device tree bits)?
They are in the Linux So
Hi Russell,
On Wed, 2 Dec 2020 at 00:04, Russell King - ARM Linux admin
wrote:
>
> On Tue, Dec 01, 2020 at 10:43:30PM +0900, Daniel Palmer wrote:
> > + np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl");
> > + smpctrl = of_iomap(np, 0);
,
instead of a camera interface they have display hardware and so on.
Aside from the above points the big difference about these chips is that
they include a second Cortex A7 core.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++
arch/arm/boot/dts
to handle multiple cores is fine if there is only
one core the will get booted. This might need to be reconsidered if chips
with more cores turn up.
Signed-off-by: Daniel Palmer
---
arch/arm/mach-mstar/mstarv7.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/arc
Add the smpctrl registers to the infinity2m dtsi so that the
second CPU can be enabled on chips in this family.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi
b/arch/arm
Add the specific compat string for the smpctrl registers to the
SSD201/SSD202D common dtsi.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
b/arch/arm/boot
Add a dts for the Honestar ssd201htv2 devkit.
This is for the board populated with a SSD202D.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/Makefile| 1 +
.../mstar-infinity2m-ssd202d-ssd201htv2.dts | 25 +++
2 files changed, 26 insertions(+)
create
The Honestar SSD201_HT_V2 is a full size devkit for the SigmaStar
SSD201 or SSD202D (they are pin compatible).
Currently only the SSD202D version is supported as that's the one
I have.
Link: https://linux-chenxing.org/infinity2/ssd201_ht_v2/
Signed-off-by: Daniel Palmer
---
Document
Add a chip level dtsi for the SigmaStar SSD202D
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
diff --git a/arch/arm/boot/dts/mstar
The SSD201 and SSD202D are basically the same chip with a different DDR die
packaged (64MB DDR2 or 128MB DDR3).
This patch adds a shared dtsi for the common parts of these chips like
gpio, pinctrl etc.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 7
mc5m4pdmxnwjgw_ozinku93lp+eyq8qacmh4eesh...@mail.gmail.com/
Daniel Palmer (10):
dt-bindings: mstar: Add binding details for mstar,smpctrl
dt-bindings: vendor-prefixes: Add honestar vendor prefix
dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards
ARM: mstar: Add infinity2m support
Add prefix for Honestar Technologies Co., Ltd.
Signed-off-by: Daniel Palmer
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings/vendor
This adds a YAML description of the smpctrl node needed by the
platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus.
Signed-off-by: Daniel Palmer
---
.../bindings/arm/mstar/mstar,smpctrl.yaml | 40 +++
1 file changed, 40 insertions(+)
create mode 100644
Hi Arnd,
On Mon, 30 Nov 2020 at 22:42, Arnd Bergmann wrote:
> > +struct smp_operations __initdata mstarv7_smp_ops = {
> > + .smp_boot_secondary = mstarv7_boot_secondary,
> > +};
> > +#endif
>
> So no hotplug operations?
Not yet. There are controls to power down different bits of the chip,
Hi Arnd,
On Mon, 30 Nov 2020 at 22:44, Arnd Bergmann wrote:
>
> On Mon, Nov 30, 2020 at 2:10 PM Daniel Palmer wrote:
> >
> > +&riu {
> > + smpctrl@204000 {
> > + compatible = "mstar,smpctrl";
> > + reg = &l
,
instead of a camera interface they have display hardware and so on.
Aside from the above points the big difference about these chips is that
they include a second Cortex A7 core.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++
arch/arm/boot/dts
The SSD201 and SSD202D are basically the same chip with a different DDR die
packaged (64MB DDR2 or 128MB DDR3).
This patch adds a shared dtsi for the common parts of these chips like
gpio, pinctrl etc.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 7
to handle multiple cores is fine if there is only
one core the will get booted. This might need to be reconsidered if chips
with more cores turn up.
Signed-off-by: Daniel Palmer
---
arch/arm/mach-mstar/mstarv7.c | 50 +++
1 file changed, 50 insertions(+)
diff --git a/arc
Add a chip level dtsi for the SigmaStar SSD202D
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi
diff --git a/arch/arm/boot/dts/mstar
The Honestar SSD201_HT_V2 is a full size devkit for the SigmaStar
SSD201 or SSD202D (they are pin compatible).
Currently only the SSD202D version is supported as that's the one
I have.
Link: https://linux-chenxing.org/infinity2/ssd201_ht_v2/
Signed-off-by: Daniel Palmer
---
Document
Add the smpctrl registers to the infinity2m dtsi so that the
second CPU can be enabled on chips in this family.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/mstar-infinity2m.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi
b/arch
This series adds basic support for the infinity2m series
of chips. For now the SigmaStar SSD202D which is a dual
Cortex A7 in a QFN128 package.
These chips share most of the same hardware with the
currently supported infinity, infinity3 and mercury5
chips.
Daniel Palmer (9):
dt-bindings: mstar
This adds a YAML description of the smpctrl node needed by the
platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus.
Signed-off-by: Daniel Palmer
---
.../bindings/arm/mstar/mstar,smpctrl.yaml | 38 +++
1 file changed, 38 insertions(+)
create mode 100644
Add a dts for the Honestar ssd201htv2 devkit.
This is for the board populated with a SSD202D.
Signed-off-by: Daniel Palmer
---
arch/arm/boot/dts/Makefile| 1 +
.../mstar-infinity2m-ssd202d-ssd201htv2.dts | 25 +++
2 files changed, 26 insertions(+)
create
Add prefix for Honestar Technologies Co., Ltd.
Signed-off-by: Daniel Palmer
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings/vendor
Fill in the properties needed to use the GPIO controller
in the infinity and infinity3 chips.
Signed-off-by: Daniel Palmer
Acked-by: Linus Walleij
---
arch/arm/boot/dts/mstar-infinity.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi
b/arch
somewhere
to go.
Because of the above the driver itself uses the index of a pin's offset in
an array of the possible offsets for a chip as the gpio number.
Signed-off-by: Daniel Palmer
Reviewed-by: Rob Herring
---
MAINTAINERS| 1 +
include/dt-bindings/gpio/msc313-g
The GPIO controller is at the same address in all of the
currently known chips so create a node for it in the base
dtsi.
Some extra properties are needed to actually use it so
disable it by default.
Signed-off-by: Daniel Palmer
Acked-by: Linus Walleij
---
arch/arm/boot/dts/mstar-v7.dtsi | 10
Add a binding description for the MStar/SigmaStar GPIO controller
found in the MSC313 and later ARMv7 SoCs.
Signed-off-by: Daniel Palmer
---
.../bindings/gpio/mstar,msc313-gpio.yaml | 59 +++
MAINTAINERS | 1 +
2 files changed, 60
f the lines have been mapped out.
Signed-off-by: Daniel Palmer
---
MAINTAINERS| 1 +
drivers/gpio/Kconfig | 11 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-msc313.c | 460 +
4 files changed, 473 insertions(+)
create mode 1
ociated interrupts the binding description
has been updated to add the interrupt-controller bits and remove the
description of the interrupt-names that described how the interrupts
used to be passed in.
Daniel Palmer (5):
dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver
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