Hi Yogesh, Tudor,
Le 17/10/2018 à 04:07, Yogesh Narayan Gaur a écrit :
> Hi Tudor,
>
>> -Original Message-----
>> From: Cyrille Pitchen [mailto:cyrille.pitc...@wedev4u.fr]
>> Sent: Tuesday, October 16, 2018 10:04 PM
>> To: Tudor Ambarus ; Yogesh Narayan Gaur
>
Hi Tudor,
Le 16/10/2018 à 17:14, Tudor Ambarus a écrit :
> Hi, Yogesh,
>
> On 10/16/2018 12:51 PM, Yogesh Narayan Gaur wrote:
>> Hi Tudor,
>>
>> This patch is breaking the 1-4-4 Read protocol for the spansion flash
>> "s25fl512s".
>>
>> Without this patch read request command for Quad mode, 4-by
Hi Lukasz,
Le 27/09/2018 à 00:07, Lukasz Majewski a écrit :
> The fsl-quadspi.c driver is not supporting SPINOR_OP_RDSFDP (0x5a)
> read opcode - in the legacy driver we do read some garbage
> data from AHB mapped area and then return on the first check
If your controller reads garbage then spi_no
ased on initial work done by Anurag Kumar Vulisha:
> https://patchwork.kernel.org/patch/7611271/
>
> Signed-off-by: Tudor Ambarus
Reviewed-by: Cyrille Pitchen
Best regards,
Cyrille
> ---
> drivers/mtd/spi-nor/spi-nor.c | 21 +
> include/linux/mtd/spi-nor.h
Hi Tudor,
Le 08/06/2018 à 15:48, Tudor Ambarus a écrit :
> The commit message became wall-of-text, my feeling is that I heavily
> reworked the code so I changed the author. If someone thinks differently,
> please say and I'll change back to the initial authorship. What I've done:
It's obvious tha
Hi Marek,
Le 18/03/2018 à 00:41, Marek Vasut a écrit :
> On 03/15/2018 08:04 PM, Cyrille Pitchen wrote:
>> remove myself as MTD and SPI NOR maintainer.
>>
>> Signed-off-by: Cyrille Pitchen
>
> What happened ?
>
Nothing to worry. Since I was hired for a new job,
remove myself as MTD and SPI NOR maintainer.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3bdc260e36b7..7892db9a9494 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9037,7 +9037,6 @@ M:Brian Norris
M
ub-ordinate bus numbers in
the PCI configuration space of the root port.
- remove cdns_pcie_ep_stop() function and rework cdns_pcie_ep_start() function
Cyrille Pitchen (10):
PCI: Regroup all PCI related entries into drivers/pci/Makefile
PCI: OF: Add generic function to parse and alloca
This patch updates the prototype of most handlers from 'struct
pci_epc_ops' so the EPC library can now support multi-function devices.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/dwc/pcie-designware-ep.c | 20 +
drivers/pci/endpoint/functions/pci-epf-t
Hi Lorenzo, Bjorn,
Le 30/01/2018 à 12:41, Lorenzo Pieralisi a écrit :
> On Sun, Jan 28, 2018 at 03:47:41PM -0600, Bjorn Helgaas wrote:
>> On Sun, Jan 28, 2018 at 09:40:14PM +0100, Cyrille Pitchen wrote:
>>> Hi all,
>>>
>>> this series of patches adds support to
-cadence.c and used by both the host and
endpoint controller drivers.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 2 +-
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 1 +
drivers/pci
The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 49
y, we add another comment to explain why obj-y has been chosen
instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder.
Signed-off-by: Cyrille Pitchen
---
drivers/Makefile | 5 +
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 13 ++---
drivers/pci/dwc/Mak
Call pci_free_resource_list() from pci_host_common_probe() when probing
fails, as done inside gen_pci_init() when this later function fails.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/host/pci-host
useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 22 +-
drivers/pci/probe.c| 33 +
include/linux
This patch documents the DT bindings for the Cadence PCIe controller
when configured in endpoint mode.
Signed-off-by: Cyrille Pitchen
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 22 ++
1 file changed, 22 insertions(+)
create mode
Fix the pci_epf_make() function so it can now bind many EPF devices to the
same EPF driver.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/endpoint/pci-ep-cfs.c | 46 +--
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/endpoint/pci
This patch adds support to the Cadence PCIe controller in host mode.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 7 +
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pcie-cadence-host.c | 397
From: Scott Telford
This patch adds documentation for the DT bindings of the Cadence PCIe
controller when configured in host (Root Complex) mode.
Signed-off-by: Scott Telford
Signed-off-by: Cyrille Pitchen
Reviewed-by: Rob Herring
---
.../bindings/pci/cdns,cdns-pcie-host.txt | 60
This patch adds a new PCI vendor ID for Cadence.
Signed-off-by: Cyrille Pitchen
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5db423..eb13e84e1fef 100644
--- a/include/linux/pci_ids.h
+++ b/include
This patch adds a new PCI vendor ID for Cadence.
Signed-off-by: Cyrille Pitchen
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5db423..eb13e84e1fef 100644
--- a/include/linux/pci_ids.h
+++ b/include
y, we add another comment to explain why obj-y has been chosen
instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder.
Signed-off-by: Cyrille Pitchen
---
drivers/Makefile | 5 +
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 13 ++---
drivers/pci/dwc/Mak
useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 22 +-
drivers/pci/probe.c| 33 +
include/linux
remove some useless tests
- add more comments in both drivers.
- fix DT bindings examples
- remove useless init of the primary, secondary and sub-ordinate bus numbers in
the PCI configuration space of the root port.
- remove cdns_pcie_ep_stop() function and rework cdns_pcie_ep_start() functio
Call pci_free_resource_list() from pci_host_common_probe() when probing
fails, as done inside gen_pci_init() when this later function fails.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/host/pci-host
Fix the pci_epf_make() function so it can now bind many EPF devices to the
same EPF driver.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/endpoint/pci-ep-cfs.c | 46 +--
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/endpoint/pci
-cadence.c and used by both the host and
endpoint controller drivers.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 2 +-
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 1 +
drivers/pci
From: Scott Telford
This patch adds documentation for the DT bindings of the Cadence PCIe
controller when configured in host (Root Complex) mode.
Signed-off-by: Scott Telford
Signed-off-by: Cyrille Pitchen
Reviewed-by: Rob Herring
---
.../bindings/pci/cdns,cdns-pcie-host.txt | 60
The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 49
This patch updates the prototype of most handlers from 'struct
pci_epc_ops' so the EPC library can now support multi-function devices.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/dwc/pcie-designware-ep.c | 20 +
drivers/pci/endpoint/functions/pci-epf-t
This patch documents the DT bindings for the Cadence PCIe controller
when configured in endpoint mode.
Signed-off-by: Cyrille Pitchen
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 22 ++
1 file changed, 22 insertions(+)
create mode
This patch adds support to the Cadence PCIe controller in host mode.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 7 +
drivers/pci/host/Kconfig | 10 +
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pcie-cadence-host.c | 397
Le 18/01/2018 à 23:52, Cyrille Pitchen a écrit :
> Hi all,
>
> this series of patches adds support to the Cadence PCIe controller.
> It was tested on a ARM64 platform emulated by a Palladium running the
> pci-next kernel.
>
> The host mode was tested with some PCIe dev
Hi Lorenzo
Le 16/01/2018 à 17:07, Lorenzo Pieralisi a écrit :
> On Wed, Jan 10, 2018 at 11:47:35PM +0100, Cyrille Pitchen wrote:
>> This patch adds support to the Cadence PCIe controller in host mode.
>>
>> Signed-off-by: Cyrille Pitchen
>> ---
>> MAINTAINERS
Hi Kishon,
Le 16/01/2018 à 12:16, Kishon Vijay Abraham I a écrit :
> Hi Cyrille,
>
> On Thursday 11 January 2018 04:17 AM, Cyrille Pitchen wrote:
>> This patch adds support to the Cadence PCIe controller in host mode.
>>
>> Signed-off-by: Cyrille Pitc
ndings examples
- remove useless init of the primary, secondary and sub-ordinate bus numbers in
the PCI configuration space of the root port.
- remove cdns_pcie_ep_stop() function and rework cdns_pcie_ep_start() function
Cyrille Pitchen (6):
PCI: Regroup all PCI related entries into drivers/pci/M
This patch adds support to the Cadence PCIe controller in host mode.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 7 +
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile| 1 +
drivers/pci/cadence/Kconfig
useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 22 +-
drivers/pci/probe.c| 33 +
include/linux
Call pci_free_resource_list() from pci_host_common_probe() when probing
fails, as done inside gen_pci_init() when this later function fails.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/host/pci-host
This patch adds a new PCI vendor ID for Cadence.
Signed-off-by: Cyrille Pitchen
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5db423..eb13e84e1fef 100644
--- a/include/linux/pci_ids.h
+++ b/include
The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 49
From: Scott Telford
This patch adds documentation for the DT bindings of the Cadence PCIe
controller when configured in host (Root Complex) mode.
Signed-off-by: Scott Telford
Signed-off-by: Cyrille Pitchen
Reviewed-by: Rob Herring
---
.../bindings/pci/cdns,cdns-pcie-host.txt | 60
y, we add another comment to explain why obj-y has been chosen
instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder.
Signed-off-by: Cyrille Pitchen
---
drivers/Makefile | 5 +
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 13 ++---
drivers/pci/dwc/Mak
Hi Lorenzo,
Le 16/01/2018 à 16:25, Lorenzo Pieralisi a écrit :
> On Wed, Jan 10, 2018 at 11:47:32PM +0100, Cyrille Pitchen wrote:
>> This patchs moves generic source code from
>> drivers/pci/host/pci-host-common.c into drivers/pci/probe.c.
>>
>> Indeed the extracted li
Le 18/12/2017 à 02:47, Guochun Mao a écrit :
> Since more and more Mediatek's SoC can use this driver to
> control spi-nor flash, functions' name with "mt8173_" is
> no longer properly. Replacing "mt8173_" with "mtk_" will
> be more accurate to describe these functions' usable scope.
>
> Signed-of
This patch adds a new PCI vendor ID for Cadence.
Signed-off-by: Cyrille Pitchen
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5db423..eb13e84e1fef 100644
--- a/include/linux/pci_ids.h
+++ b/include
y, we add another comment to explain why obj-y has been chosen
instead of obj-$(CONFIG_PCIE_DW) to parse the dwc/ sub-folder.
Signed-off-by: Cyrille Pitchen
---
drivers/Makefile | 5 +
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 13 ++---
drivers/pci/dwc/Mak
This patch adds support to the Cadence PCIe controller in host mode.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 7 +
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile| 1 +
drivers/pci/cadence/Kconfig
useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
We also add a missing call of pci_free_resource_list() from
pci_host_common_probe() when probing fails, as done inside gen_pci_init()
when this later function fails.
Signed-off-by: Cyrille
From: Scott Telford
This patch adds documentation for the DT bindings of the Cadence PCIe
controller when configured in host (Root Complex) mode.
Signed-off-by: Scott Telford
Signed-off-by: Cyrille Pitchen
Reviewed-by: Rob Herring
---
.../bindings/pci/cdns,cdns-pcie-host.txt | 60
hare more common code between host controller drivers
- remove some useless tests
- add more comments in both drivers.
- fix DT bindings examples
- remove useless init of the primary, secondary and sub-ordinate bus numbers in
the PCI configuration space of the root port.
- remove cdns_pcie_ep_stop() fu
The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 49
Le 02/01/2018 à 14:28, Julia Lawall a écrit :
> This driver creates a number of const structures that it stores in the
> data field of an of_device_id array.
>
> The data field of an of_device_id structure has type const void *, so
> there is no need for a const-discarding cast when putting const
Le 29/12/2017 à 10:11, Vignesh R a écrit :
> Cadence QSPI controller provides direct access mode through which flash
> can be accessed in a memory-mapped IO mode. This enables read/write to
> flash using memcpy*() functions. This mode provides higher throughput
> for both read/write operations when
Le 29/12/2017 à 10:11, Vignesh R a écrit :
> Move configuring of indirect read/write start address to
> cqspi_indirect_*_execute() function and rename cqspi_indirect_*_setup()
> function. This will help to reuse cqspi_indirect_*_setup() function for
> supporting direct access mode.
>
> Signed-off-
Remove empty lines, useless comments and sort rules by alphabetical
order.
Signed-off-by: Cyrille Pitchen
---
Hi Bjorn,
This is the kernel oops I get when I test this patch.
I've applied it on top of the series for the Cadence PCIe controller.
I didn't have time to investigate more
Hi Kishon,
Le 03/01/2018 à 10:14, Kishon Vijay Abraham I a écrit :
> Hi,
>
> On Saturday 30 December 2017 02:23 AM, Cyrille Pitchen wrote:
>> Hi Kishon,
>>
>> Le 28/12/2017 à 14:00, Kishon Vijay Abraham I a écrit :
>>> Hi Cyrille,
>>>
>>>
Hi Bjorn,
Le 29/12/2017 à 00:01, Bjorn Helgaas a écrit :
> On Mon, Dec 18, 2017 at 07:16:06PM +0100, Cyrille Pitchen wrote:
>> This patch adds support to the Cadence PCIe controller in host mode.
>>
>> The "cadence/" entry in drivers/pci/Makefile is placed after t
Hi Kishon,
Le 28/12/2017 à 14:00, Kishon Vijay Abraham I a écrit :
> Hi Cyrille,
>
> On Monday 18 December 2017 11:46 PM, Cyrille Pitchen wrote:
>> Hi all,
>>
>> this series of patches adds support to the Cadence PCIe controller.
>> It was tested on a ARM64
Hi Kishon,
Le 29/12/2017 à 10:23, Kishon Vijay Abraham I a écrit :
> Hi,
>
> On Monday 18 December 2017 11:46 PM, Cyrille Pitchen wrote:
>> This patch updates the prototype of most handlers from 'struct
>> pci_epc_ops' so the EPC library can now support multi-fun
Hi Bjorn,
Le 28/12/2017 à 23:47, Bjorn Helgaas a écrit :
> On Mon, Dec 18, 2017 at 07:16:01PM +0100, Cyrille Pitchen wrote:
>> This patch cleans drivers/Makefile up by moving the pci/endpoint and
>> pci/dwc entries from drivers/Makefile into drivers/pci/Makefile.
>
> Thanks
Le 28/12/2017 à 11:03, Romain Porte a écrit :
> Add support for a new ISSI 1MB SPI NOR chip that was tested in our lab.
> Datasheet is available at: http://www.issi.com/WW/pdf/25LP-WP080D.pdf
>
> Testing was done only without the SPI_NOR_{DUAL,QUAD}_READ flags that
> were added later, according to
Hi Trent,
Le 26/12/2017 à 20:43, Trent Piepho a écrit :
> On Sun, 2017-12-24 at 05:36 +0100, Cyrille Pitchen wrote:
>>
>> Then the patch adds two hardware capabilities for SPI flash controllers,
>> SNOR_HWCAPS_WR_BOUNCE and SNOR_HWCAPS_RD_BOUNCE.
>
> Are there any
Hi Trent,
Le 27/12/2017 à 21:15, Trent Piepho a écrit :
> On Wed, 2017-12-27 at 10:36 +, Mark Brown wrote:
>> On Tue, Dec 26, 2017 at 06:45:28PM +, Trent Piepho wrote:
>>
>>> Or, since this only fixes instances of DMA-unsafe buffers used in
>>> access to SPI NOR flash chips, and since ther
Hi Rob,
+ Ludovic Desroches, maintainer of the DMA controller drivers for AT91 SoCs.
Le 27/12/2017 à 00:23, Rob Herring a écrit :
> On Sun, Dec 24, 2017 at 05:36:05AM +0100, Cyrille Pitchen wrote:
>> The optional 'dmacap,memcpy' DT property tells the Atmel QSPI controller
&
Hi Romain,
Le 27/12/2017 à 15:46, Romain Porte a écrit :
> On 27/12/2017 14:58, Romain Porte wrote:
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index 8bafd462f..18e826d36 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@
Hi Vignesh
Le 26/12/2017 à 14:42, Vignesh R a écrit :
> Hi Cyrille,
>
> Thanks for doing this series! One comment below.
>
> On 24-Dec-17 10:06 AM, Cyrille Pitchen wrote:
> [...]
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> in
provide good
performances even if new memory parts come with even larger erase sector
sizes, limiting the memory footprint at the same time.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/devices/m25p80.c | 4 +-
drivers/mtd/spi-nor/spi-nor.c | 136 +++--
The optional 'dmacap,memcpy' DT property tells the Atmel QSPI controller
driver to reserve some DMA channel then to use it to perform DMA
memcpy() during data transfers. This feature relies on the generic
bounce buffer helper from spi-nor.c.
Signed-off-by: Cyrille Pitchen
---
Doc
is enabled only if the "dmacap,memcpy" boolean property is set in
the device-tree.
Signed-off-by: Cyrille Pitchen
---
drivers/mtd/spi-nor/atmel-quadspi.c | 132 +++-
1 file changed, 129 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi
device-tree.
I found this name in some other device-trees already using it for a
boolean property.
Best regards,
Cyrille
Cyrille Pitchen (3):
mtd: spi-nor: add optional DMA-safe bounce buffer for data transfer
dt-bindings: mtd: atmel-quadspi: add an optional property
'dmacap,mem
Hi Vignesh,
Le 07/12/2017 à 07:38, Vignesh R a écrit :
> Cadence QSPI controller provides direct access mode through which flash
> can be accessed in a memory-mapped IO mode. This enables read/write to
> flash using memcpy*() functions. This mode provides higher throughput
> for both read/write op
Hi Vignesh,
Le 07/12/2017 à 07:38, Vignesh R a écrit :
> Move configuring of indirect read/write start address to
> cqspi_indirect_*_execute() function and rename cqspi_indirect_*_setup()
> function. This will help to reuse cqspi_indirect_*_setup() function for
> supporting direct access mode.
>
re's no good reason to have two different trees.
> Move all -next branches to linux-mtd.
>
> Signed-off-by: Boris Brezillon
> Cc: Stephen Rothwell
> Cc: Marek Vasut
> Cc: Cyrille Pitchen
> Cc: Richard Weinberger
> Cc: David Woodhouse
> Cc: Brian Norris
Acked-by:
Hi Romain,
Le 19/12/2017 à 14:43, Romain Porte a écrit :
> This patch adds support for a new ISSI 1MB SPI NOR chip that was tested in our
> lab. Datasheet is available at: http://www.issi.com/WW/pdf/25LP-WP080D.pdf
>
> Tested-by: Pascal Fabreges
> Reviewed-by: Alexander Sverdlin
> ---
> driver
This patch documents the DT bindings for the Cadence PCIe controller
when configured in endpoint mode.
Signed-off-by: Cyrille Pitchen
---
.../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree
es in drivers/pci/ were updated accordingly so no file is
compiled when CONFIG_PCI is not defined.
Signed-off-by: Cyrille Pitchen
---
drivers/Makefile | 5 +
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 11 ---
drivers/pci/host/Makefile | 2 ++
4 files change
This patch adds a new PCI vendor ID for Cadence.
Signed-off-by: Cyrille Pitchen
---
include/linux/pci_ids.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5db423..eb13e84e1fef 100644
--- a/include/linux/pci_ids.h
+++ b/include
libraries would have been initialized, which would
result in a kernel crash: controllers_group would still be NULL when
devm_pci_epc_create() is called.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/cadence/Kconfig | 9 +
drivers/pci/cadence/Makefile | 1 +
drivers/pci/cadence
useless
dependency to PCI_HOST_COMMON, which selects PCI_ECAM when not needed by
most host controller drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 38 +++--
drivers/pci/probe.c| 50
The patch moves the gen_pci_parse_request_of_pci_ranges() function from
drivers/pci/host/pci-host-common.c into drivers/pci/of.c to easily share
common source code between PCI host drivers.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/host/pci-host-common.c | 49
will be
linked after drivers/pci/endpoint/*.o objects, otherwise the built-in
pci-cadence-ep driver would be probed before the PCI endpoint libraries
would have been initialized, which would result in a kernel crash.
Signed-off-by: Cyrille Pitchen
---
MAINTAINERS | 7 +
This patch updates the prototype of most handlers from 'struct
pci_epc_ops' so the EPC library can now support multi-function devices.
Signed-off-by: Cyrille Pitchen
---
drivers/pci/dwc/pcie-designware-ep.c | 20 +
drivers/pci/endpoint/functions/pci-epf-t
rivers.
- fix DT bindings examples
- remove useless init of the primary, secondary and sub-ordinate bus numbers in
the PCI configuration space of the root port.
- remove cdns_pcie_ep_stop() function and rework cdns_pcie_ep_start() function
Cyrille Pitchen (8):
PCI: Regroup all PCI related entri
From: Scott Telford
This patch adds documentation for the DT bindings of the Cadence PCIe
controller when configured in host (Root Complex) mode.
Signed-off-by: Scott Telford
Signed-off-by: Cyrille Pitchen
---
.../bindings/pci/cdns,cdns-pcie-host.txt | 60 ++
1
Hi Kishon,
Le 15/12/2017 à 06:49, Kishon Vijay Abraham I a écrit :
> Hi Cyrille,
>
> On Thursday 14 December 2017 10:33 PM, Cyrille Pitchen wrote:
>> Le 13/12/2017 à 17:50, Cyrille Pitchen a écrit :
>>> Hi Kishon,
>>>
>>> Le 05/12/2017 à 10:19
Le 13/12/2017 à 17:50, Cyrille Pitchen a écrit :
> Hi Kishon,
>
> Le 05/12/2017 à 10:19, Kishon Vijay Abraham I a écrit :
>> Hi,
>>
>> On Friday 01 December 2017 05:50 PM, Lorenzo Pieralisi wrote:
>>> On Thu, Nov 23, 2017 at 04:01:50PM +0100, Cyrille Pitchen wr
Hi Kishon,
Le 05/12/2017 à 10:19, Kishon Vijay Abraham I a écrit :
> Hi,
>
> On Friday 01 December 2017 05:50 PM, Lorenzo Pieralisi wrote:
>> On Thu, Nov 23, 2017 at 04:01:50PM +0100, Cyrille Pitchen wrote:
>>> This patch adds support to the Cadence PCIe controller in end
was it a HW trick or a specific IP SW configuration ?
>>>
I will have to ask for details to Cadence designers if needed but when I
asked them about it, they explained me that AXI bus accesses in a small
window (I guess 4KB width) were redirected to the APB bus where lay the
registers for the root port PCI configuration space.
I was some hardware trick which won't be included in the final design, so
we can't enable or disable it by software.
Actually, this is requirement from the Cadence's customer that the host
driver can access the PCI config space of any device in sub ordinates
buses through a small memory area on the AXI bus. For some reason, they
don't want an ECAM compliant controller.
I don't know the reason but my guess is that they don't want to waste to
much space allocated to the PCIe controller on the AXI bus, likely on a
32-bit platform. As I said, this is such an assumption.
>>>> Also, we now want all initialisations to be done by the linux driver
>>>> instead of the bootloader.
>>>
>>> That's a choice, I do not necessarily agree with it and I think we
>>> should aim for more standardization on the PCI host bridge set-up
>>> at firmware->kernel handover on DT platforms.
>>>
It was another requirement of Cadence's customer that the PCIe host
controller initialization is done by the Linux driver rather than by
some boot loader.
Best regards,
Cyrille
>>
>> Well, for one, it means this IP will never be supported by ACPI, which
>> seems like a huge downside to me.
>
> Yes it is - that's exactly where my comments were heading.
>
> Thanks,
> Lorenzo
>
--
Cyrille Pitchen, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Hi Philippe,
Le 07/12/2017 à 11:05, Philippe Ombredanne a écrit :
> Cyrille,
>
>
> On Tue, Dec 5, 2017 at 10:19 AM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Friday 01 December 2017 05:50 PM, Lorenzo Pieralisi wrote:
>>> On Thu, Nov 23, 2017 at
Hi all,
+ MTD maintainers
Le 12/12/2017 à 23:53, Linus Torvalds a écrit :
> On Tue, Dec 12, 2017 at 1:24 PM, Cyrille Pitchen
> wrote:
>>
>> I don't see anything wrong when fetching the tree or when browsing the
>> web server:
>> http://git.infradead.org/l2-
Hi Stephen,
I've just added 2 commits about 8 hours ago, nothing special.
Could the issue be explained by an unlikely bad timing?
I don't see anything wrong when fetching the tree or when browsing the
web server:
http://git.infradead.org/l2-mtd.git/shortlog/refs/heads/spi-nor/next
Please, let me
Le 12/12/2017 à 16:58, Marek Vasut a écrit :
> On 12/12/2017 02:40 PM, Cyrille Pitchen wrote:
>> This reverts commit b07815d4eaf658b683c345d6e643895a20d92f29.
>>
>> The reverted commit was merged into v4-15-rc1 by mistake: it was taken
>> from the IMX tree but the p
the following link for more details:
http://lists.infradead.org/pipermail/linux-mtd/2017-November/077425.html
Signed-off-by: Cyrille Pitchen
---
Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-
Le 06/12/2017 à 03:53, Zhiqiang Hou a écrit :
> From: Hou Zhiqiang
>
> Restore the status to be compatible with legacy devices.
> Take Freescale eSPI boot for example, it copies (in 3 Byte
> addressing mode) the RCW and bootloader images from SPI flash
> without firing a reset signal previously,
Le 06/12/2017 à 03:53, Zhiqiang Hou a écrit :
> From: Hou Zhiqiang
>
> Add this API to restore the status of SPI flash chip to the default
> such as addressing mode, whenever detach the driver from device or
> reboot the system.
>
> Signed-off-by: Hou Zhiqiang
Applied to the spi-nor/next branc
Hi Hou,
Le 05/12/2017 à 06:33, Zhiqiang Hou a écrit :
> From: Hou Zhiqiang
>
> To be compatible with legacy device, reset the addressing mode
> to the default mode. Such as Freescale eSPI boot, it copies the
> images from SPI flash without firing a reset signal previously,
> so the reboot comman
gt; memory and detecting possible error conditions.
>>>
>>> Signed-off-by: beanhuo
Applied to the spi-nor/next branch of l2-mtd after correcting few typos
in the commit message and the subject line.
>>
>> Otherwise,
>> Acked-by: Cyrille Pitchen
>>
>> No need to resend, I'll fix these tiny issues myself :)
>>
>
> Thanks!
>
> // Bean Huo
>
Hi Lorenzo,
Le 01/12/2017 à 13:20, Lorenzo Pieralisi a écrit :
> On Thu, Nov 23, 2017 at 04:01:50PM +0100, Cyrille Pitchen wrote:
>> This patch adds support to the Cadence PCIe controller in endpoint mode.
>
> Please add a brief description to the log to describe the most sal
; device, checking information regarding what is actually
> doing the memory and detecting possible error conditions.
>
> Signed-off-by: beanhuo
Otherwise,
Acked-by: Cyrille Pitchen
No need to resend, I'll fix these tiny issues myself :)
Best regards,
Cyrille
> ---
> v1
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