James Clark writes:
On 13/02/2025 6:03 pm, Colton Lewis wrote:
If the PMU is partitioned, keep the driver out of the guest counter
partition and only use the host counter partition. Partitioning is
defined by the MDCR_EL2.HPMN register field and saved in
cpu_pmu->hpmn. The range 0..HPMN-1
Hi James,
Thanks for the review.
James Clark writes:
On 13/02/2025 6:03 pm, Colton Lewis wrote:
For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
allowed, EL0 while counters HPMN..N are only accessible
Colton Lewis writes:
For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
allowed, EL0 while counters HPMN..N are only accessible by EL2.
Introduce a module parameter in KVM to set this register. The name
EL2.
Define some macros that take HPMN as an argument and construct
mutually exclusive bitmaps for testing which partition a particular
counter is in. Note that despite their different position in the
bitmap, the cycle and instruction counters are always in the guest
partition.
Signed-off-by: Col
It's possible the host has that many counters, but HPMN restricts us
from using them.
Signed-off-by: Colton Lewis
---
tools/testing/selftests/kvm/arm64/vpmu_counter_access.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm/
accessible to EL2.
The parameter is only configurable at boot time. Making the parameter
configurable on a running system is dangerous due to the difficulty of
knowing for sure no counters are in use anywhere so it is safe to
reporgram HPMN.
Signed-off-by: Colton Lewis
---
arch/arm64/include/asm
These bitmasks are valid for enable and interrupt registers as well as
overflow registers. Generalize the names.
Signed-off-by: Colton Lewis
---
include/linux/perf/arm_pmuv3.h | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/include/linux/perf/arm_pmuv3.h
A lot of functions in pmu-emul.c aren't specific to the emulated PMU
implementation. Move them to the more appropriate pmu.c file where
shared PMU functions should live.
Signed-off-by: Colton Lewis
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/pmu-emul.c
scm/linux/kernel/git/maz/arm-platforms.git/log/?h=kvm-arm64/pmu-includes
Colton Lewis (7):
arm64: cpufeature: Add cap for HPMN0
arm64: Generate sign macro for sysreg Enums
KVM: arm64: Reorganize PMU functions
KVM: arm64: Introduce module param to partition the PMU
perf: arm_pmuv3: General
Zyngier
Signed-off-by: Colton Lewis
---
arch/arm64/include/asm/arm_pmuv3.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 198 +--
arch/arm64/include/asm/kvm_pmu.h| 38 +
arch/arm64/kvm/arm.c| 1 -
arch/arm64/kvm/debug.c
There's no reason Enums shouldn't be equivalent to UnsignedEnums and
explicitly specify they are unsigned.
Signed-off-by: Colton Lewis
---
arch/arm64/tools/gen-sysreg.awk | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg
: Colton Lewis
---
arch/arm64/kernel/cpufeature.c | 8
arch/arm64/tools/cpucaps | 1 +
arch/arm64/tools/sysreg| 6 +++---
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 4eb7c6698ae4..396327b4da7d
Hi Oliver, thanks for the review.
Oliver Upton writes:
Hi Colton,
On Sat, Feb 08, 2025 at 02:01:09AM +, Colton Lewis wrote:
For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
allowed, EL0 while
Hi Oliver, thanks for the review.
Oliver Upton writes:
On Sat, Feb 08, 2025 at 02:01:11AM +, Colton Lewis wrote:
The ARM architecture specifies that when MDCR_EL2.HPMN is set, EL1 and
EL0, which includes KVM guests, should read that value for PMCR.N.
Signed-off-by: Colton Lewis
The ARM architecture specifies that when MDCR_EL2.HPMN is set, EL1 and
EL0, which includes KVM guests, should read that value for PMCR.N.
Signed-off-by: Colton Lewis
---
arch/arm64/kvm/debug.c | 3 +--
arch/arm64/kvm/pmu-emul.c | 8
erous due to the difficulty of
knowing for sure no counters are in use anywhere so it is safe to
reporgram HPMN.
Signed-off-by: Colton Lewis
---
arch/arm/include/asm/arm_pmuv3.h | 13 +
arch/arm64/include/asm/arm_pmuv3.h | 10 +++
drivers/perf/arm_pmuv3.c
EL2.
Define some macros that take HPMN as an argument and construct
mutually exclusive bitmaps for testing which partition a particular
counter is in. Note that despite their different position in the
bitmap, the cycle and instruction counters are always in the guest
partition.
Signed-off-by: Col
These bitmasks are valid for enable and interrupt registers as well as
overflow registers. Generalize the names.
Signed-off-by: Colton Lewis
---
include/linux/perf/arm_pmuv3.h | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/include/linux/perf/arm_pmuv3.h
asks
are only defined for arm64. I'm not sure how to avoid the
duplication.
* Wrap code for determining if a counter index belongs to the host or
guest partition in functions
* Typo fixes and additional testing
v1:
https://lore.kernel.org/kvm/20250127222031.3078945-1-coltonle...@google.c
Colton Lewis writes:
Marc Zyngier writes:
On Tue, 28 Jan 2025 22:08:27 +,
Colton Lewis wrote:
>> + bitmap_set(cpu_pmu->cntr_mask, 0, pmcr_n);
>> +
>> + if (reserved_guest_counters > 0 && reserved_guest_counters <
pmcr_n
Marc Zyngier writes:
On Tue, 28 Jan 2025 22:08:27 +,
Colton Lewis wrote:
>> + bitmap_set(cpu_pmu->cntr_mask, 0, pmcr_n);
>> +
>> + if (reserved_guest_counters > 0 && reserved_guest_counters <
pmcr_n) {
>> +
Colton Lewis writes:
Hey Marc, thanks for looking.
*for the review
Marc Zyngier writes:
On Mon, 27 Jan 2025 22:20:27 +,
Colton Lewis wrote:
/* Read the nb of CNTx counters supported from PMNC */
- bitmap_set(cpu_pmu->cntr_mask,
- 0, FIELD_
Suzuki K Poulose writes:
On 27/01/2025 22:20, Colton Lewis wrote:
/* Disable all counters */
- armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
+ if (cpu_pmu->partitioned)
+ armv8pmu_mdcr_write(armv8pmu_pmcr_read() &
~ARMV8_PM
Hey Rob, thanks for the review.
Rob Herring writes:
On Mon, Jan 27, 2025 at 4:26 PM Colton Lewis
wrote:
@@ -1215,10 +1243,19 @@ static void __armv8pmu_probe_pmu(void *info)
cpu_pmu->pmuver = pmuver;
probe->present = true;
+ pmcr_n = FIELD_GET(ARMV8_PMU_
Hey Marc, thanks for looking.
Marc Zyngier writes:
On Mon, 27 Jan 2025 22:20:27 +,
Colton Lewis wrote:
For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
allowed, EL0 while counters HPMN..N are only
EL2.
Define some macros that take HPMN as an argument and construct
mutually exclusive bitmaps for testing which partition a particular
counter is in. Note that despite their different position in the
bitmap, the cycle and instruction counters are always in the guest
partition.
Signed-off-by: Col
patch
specifically disallows that case because it's not useful given the
intention to allow guests access to their own counters.
Signed-off-by: Colton Lewis
---
arch/arm/include/asm/arm_pmuv3.h | 10 +++
arch/arm64/include/asm/arm_pmuv3.h | 10 +++
drivers/perf/arm_pmuv3.c
These bitmasks are valid for enable and interrupt registers as well as
overflow registers. Generalize the names.
Signed-off-by: Colton Lewis
---
include/linux/perf/arm_pmuv3.h | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/include/linux/perf/arm_pmuv3.h
The ARM architecture specifies that when MDCR_EL2.HPMN is set, EL1 and
EL0, which includes KVM guests, should read that value for PMCR.N.
Signed-off-by: Colton Lewis
---
arch/arm64/kvm/pmu-emul.c | 8 +++-
tools/testing/selftests/kvm/aarch64
eading the register.
[1]
https://lore.kernel.org/kvmarm/20241219224116.3941496-3-oliver.up...@linux.dev/
Colton Lewis (4):
perf: arm_pmuv3: Introduce module param to partition the PMU
KVM: arm64: Make guests see only counters they can access
perf: arm_pmuv3: Generalize counter bitmasks
perf:
Sean Christopherson writes:
On Wed, 18 Sep 2024 20:53:13 +, Colton Lewis wrote:
Extend pmu_counters_test to AMD CPUs.
As the AMD PMU is quite different from Intel with different events and
feature sets, this series introduces a new code path to test it,
specifically focusing on the
Sean Christopherson writes:
On Wed, Sep 18, 2024, Colton Lewis wrote:
Test PerfMonV2, which defines global registers to enable multiple
performance counters with a single MSR write, in its own function.
If the feature is available, ensure the global control register has
the ability to
Sean Christopherson writes:
On Wed, Sep 18, 2024, Colton Lewis wrote:
Test events on core counters by iterating through every combination of
events in amd_pmu_zen_events with every core counter.
For each combination, calculate the appropriate register addresses for
the event selection
Sean Christopherson writes:
On Wed, Sep 18, 2024, Colton Lewis wrote:
Run a basic test to ensure we can write an arbitrary value to the core
counters and read it back.
Signed-off-by: Colton Lewis
---
.../selftests/kvm/x86_64/pmu_counters_test.c | 54 +++
1 file changed
Hey Sean,
Thanks for the review.
Sean Christopherson writes:
On Wed, Sep 18, 2024, Colton Lewis wrote:
Branch in main() depending on if the CPU is Intel or AMD. They are
subject to vastly different requirements because the AMD PMU lacks
many properties defined by the Intel PMU including the
Noted about the changelog and the ordering. No objections for how you
want to apply it.
Sean Christopherson writes:
The shortlog is misleading. It's the *leaves* that are being defined,
it's the
features and properties.
On Wed, Sep 18, 2024, Colton Lewis wrote:
This defined
Bumping this for Mingwei
Colton Lewis writes:
Extend pmu_counters_test to AMD CPUs.
As the AMD PMU is quite different from Intel with different events and
feature sets, this series introduces a new code path to test it,
specifically focusing on the core counters including the
loop instruction being counted
differently. Presumably, when the counter reaches 0 and execution
continues to the next instruction, AMD counts this as a branch and
Intel doesn't.
Signed-off-by: Colton Lewis
---
.../selftests/kvm/x86_64/pmu_counters_test.c | 87 ---
1 file c
flags an overflow by the associated counter.
Signed-off-by: Colton Lewis
---
.../selftests/kvm/x86_64/pmu_counters_test.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
b/tools/testing/selftests/kvm/x86_64
Run a basic test to ensure we can write an arbitrary value to the core
counters and read it back.
Signed-off-by: Colton Lewis
---
.../selftests/kvm/x86_64/pmu_counters_test.c | 54 +++
1 file changed, 54 insertions(+)
diff --git a/tools/testing/selftests/kvm/x86_64
notion of PMU versions as Intel does. Every
feature is a separate flag and they aren't the same features as Intel.
Set up a VM for testing core AMD counters and ensure proper CPUID
features are set.
Signed-off-by: Colton Lewis
---
.../selftests/kvm/x86_64/pmu_counters_test.c
: Colton Lewis
---
tools/testing/selftests/kvm/include/x86_64/processor.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h
b/tools/testing/selftests/kvm/include/x86_64/processor.h
index a0c1440017bb..44ddfc4c1673 100644
--- a/tools
ned-off-by: Colton Lewis
---
tools/testing/selftests/kvm/x86_64/pmu_counters_test.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
index 698cb36989db..0e305e43a
...@tencent.com/
v2:
* Test all combinations of VM setup rather than only the maximum
allowed by hardware
* Add fixes tag to bug fix in patch 1
* Refine some names
v1:
https://lore.kernel.org/kvm/20240813164244.751597-1-coltonle...@google.com/
Colton Lewis (6):
KVM: x86: selftests: Fix typos in
r or member
'resume' not described in 'regulator_ops'
Signed-off-by: Colton Lewis
---
include/linux/regulator/driver.h | 2 +-
include/linux/regulator/machine.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/regulator/driver.h b/include/lin
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