of checking that the BUSY bit is 1, works around the issue. Note
this in the customary location. To minimize conflicts, this documentation
update is separate from the code changes, "tty: pl011: Work around QDF2400
E44 stuck BUSY bit".
Signed-off-by: Christopher Covington
Acked-by: Ru
early_write functions.
Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing,
check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI
table to determine if the current platform is known to be affected by the
erratum.
Signed-off-by: Christopher Covington
Acked
On 02/15/2017 03:07 PM, Greg Kroah-Hartman wrote:
> On Wed, Feb 15, 2017 at 07:50:27PM +, Mark Rutland wrote:
>> On Wed, Feb 15, 2017 at 01:01:59PM -0500, Christopher Covington wrote:
>>> Due to known (although trivial) conflicts in silicon-errata.txt, based on
>>>
early_write functions.
Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing,
check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI
table to determine if the current platform is known to be affected by the
erratum.
Signed-off-by: Christopher Covington
Acked
On 2017-02-14 21:39, Timur Tabi wrote:
Christopher Covington wrote:
The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a
custom (non-PrimeCell) implementation of the SBSA UART. Occasionally
the
BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both
2432v1
and
ARMv8 ACPI PCI quirks are detected during MCFG parsing,
check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI
table to determine if the current platform is known to be affected by the
erratum.
Signed-off-by: Christopher Covington
Acked-by: Russell King
---
Changes in v2:
* Improved
On 02/07/2017 11:31 PM, Shanker Donthineni wrote:
> Hi Cov,
>
> The same PL011 driver will be used in virtutal machine, make sure
> your changes have no side effects in VM.
Fundamentally, this is the same workaround as has been tested in the qserver
downstream kernel for over a year.
Cheers,
Cov
On 02/08/2017 06:04 PM, Timur Tabi wrote:
> On 02/08/2017 04:22 PM, Christopher Covington wrote:
>>>> >> -while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
>>>> >> +while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
On 02/07/2017 11:05 PM, Timur Tabi wrote:
> Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a
>> custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the
>> BUSY bit in the Flag Register gets stuck as 1
Hi,
On 02/08/2017 08:27 AM, Timur Tabi wrote:
> Robin Murphy wrote:
>> Is there a reason anyone would ever want to turn this off? AFAICS you
>> save a few dozen bytes in return for a kernel image which you know won't
>> work properly on some hardware. That doesn't seem particularly
>> worthwhile,
On 02/08/2017 11:34 AM, Catalin Marinas wrote:
> On Tue, Feb 07, 2017 at 07:35:16PM -0500, Christopher Covington wrote:
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kconfig
>> @@ -480,6 +480,18 @@ config CAVIUM_ERRATUM_27456
>>
>>
f-by: Christopher Covington
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 18 ++
arch/arm64/include/asm/assembler.h | 23 +++
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/mmu_context.h
available, the implementation is different than in the preceding patch.
Signed-off-by: Christopher Covington
---
drivers/tty/serial/amba-pl011.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba
available, and does not handle the erratum for earlycon, as the UAP
data is not available then.
Signed-off-by: Christopher Covington
Acked-by: Russell King
---
Changes between the previous RFC [1] and this PATCH:
* don't use arch/arm64/kernel/cpu_errata.c at Will's request
* separate out ear
On 02/01/2017 01:38 PM, Catalin Marinas wrote:
> On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote:
>> On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote:
>>> On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote:
On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin M
f-by: Christopher Covington
---
Based on
https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 12
arch/arm64/include/asm/assembler.h | 23 +++
arch/a
On 01/31/2017 12:56 PM, Marc Zyngier wrote:
> On 31/01/17 17:48, Christopher Covington wrote:
>> On 01/31/2017 07:37 AM, Mark Rutland wrote:
>>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>>>> The Qualcomm Datacenter Technologies Falkor v
), this changes applies the workaround overabundantly--
to local TLBI, DSB NSH sequences as well--for simplicity.
Based on work by Shanker Donthineni
Signed-off-by: Christopher Covington
Acked-by: Mark Rutland
---
Based on
https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for
On 01/31/2017 07:37 AM, Mark Rutland wrote:
> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
>> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
>&g
On 01/31/2017 09:38 AM, Will Deacon wrote:
> On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
>> diff --git a/arch/arm64/include/asm/tlbflush.h
>> b/arch/arm64/include/asm/tlbflush.h
>> index deab52374119..fc434f421c7b 100644
>> --- a/arch/a
400v1 SoCs. Checking that the Transmit FIFO Empty (TXFE) bit is 0,
instead of checking that the BUSY bit is 1, works around the issue. To
facilitate this substitution, introduce vendor-specific inversion of
Feature Register bits.
Signed-off-by: Christopher Covington
---
Based on
https://git.kerne
f-by: Christopher Covington
---
Based on
https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/assembler.h | 23 +++
arch/a
), this changes applies the workaround overabundantly--
to local TLBI, DSB NSH sequences as well--for simplicity.
Based on work by Shanker Donthineni
Signed-off-by: Christopher Covington
---
Based on
https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core
Hi Mark,
On 01/30/2017 05:56 AM, Mark Rutland wrote:
> Hi,
>
> On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote:
>> On 01/27/2017 09:38 AM, Mark Rutland wrote:
>>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>
>&g
Hi Mark,
On 01/27/2017 09:38 AM, Mark Rutland wrote:
> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
>> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
f-by: Christopher Covington
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 11 +++
arch/arm64/include/asm/assembler.h | 23 +++
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/mmu_context.h | 8 +++-
From: Shanker Donthineni
Define the MIDR implementer and part number field values for the Qualcomm
Datacenter Technologies Falkor processor version 1 in the usual manner.
Signed-off-by: Shanker Donthineni
Signed-off-by: Christopher Covington
---
arch/arm64/include/asm/cputype.h | 4
1
), this changes applies the workaround overabundantly--
to local TLBI, DSB NSH sequences as well--for simplicity.
Based on work by Shanker Donthineni
Signed-off-by: Christopher Covington
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 10 ++
arch
: Christopher Covington
---
arch/arm64/kvm/hyp/tlb.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c
index 88e2f2b938f0..e8e7ba2bc11f 100644
--- a/arch/arm64/kvm/hyp/tlb.c
+++ b/arch/arm64/kvm/hyp/tlb.c
@@ -16,6 +16,7
Hi Fu,
On 01/25/2017 01:46 AM, Fu Wei wrote:
> Hi Mark,
>
> On 25 January 2017 at 01:24, Mark Rutland wrote:
>> On Wed, Jan 18, 2017 at 09:25:32PM +0800, fu@linaro.org wrote:
>>> From: Fu Wei
>>>
>>> The counter frequency detection call(arch_timer_detect_rate) combines two
>>> ways to get c
Hi Will,
On 01/13/2017 11:12 AM, Will Deacon wrote:
> On Fri, Jan 13, 2017 at 10:12:36AM -0500, Christopher Covington wrote:
>> On 01/12/2017 11:58 AM, Will Deacon wrote:
>>> On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote:
>>>> +#define __tlbi
Hi Catalin,
On 01/11/2017 01:06 PM, Catalin Marinas wrote:
> Some minor comments below, nothing fundamental (as long as you say the
> new sequence doesn't have the speculative TLB load problem I mentioned
> on a previous version).
This workaround is documented as providing functional correctness
On 01/12/2017 11:12 AM, Mark Rutland wrote:
> On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote:
>> On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote:
>
>>> Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0().
>>
>> This may be fine if my assumptions about t
Hi Mark,
On 01/11/2017 01:45 PM, Mark Rutland wrote:
> On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote:
>> On 01/11/2017 12:37 PM, Mark Rutland wrote:
>>> The name, as it is, is perfectly descriptive.
>>>
>>> Let's not sacrifice legibility over a non-issue.
>>
>> I don't want to kick a
Hi Will,
On 01/12/2017 11:58 AM, Will Deacon wrote:
> Hi Christopher,
>
> On Wed, Jan 11, 2017 at 09:41:16AM -0500, Christopher Covington wrote:
>> This refactoring will allow an errata workaround that repeats tlbi dsb
>> sequences to only change one location. This is not i
-off-by: Christopher Covington
---
arch/arm64/include/asm/tlbflush.h | 104 +-
1 file changed, 69 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index deab523..f28813c 100644
--- a/arch/arm64
atum
because hardware is prohibited from performing translations from an
out-of-context translation regime.
Signed-off-by: Shanker Donthineni
Signed-off-by: Christopher Covington
---
Documentation/arm64/silicon-errata.txt | 43 +-
arch/arm64/Kco
During a TLB invalidate sequence targeting the inner shareable
domain, Falkor may prematurely complete the DSB before all loads
and stores using the old translation are observed; instruction
fetches are not subject to the conditions of this erratum.
Signed-off-by: Christopher Covington
From: Shanker Donthineni
Define the MIDR implementer and part number field values for the Qualcomm
Datacenter Technologies Falkor processor version 1 in the usual manner.
Signed-off-by: Shanker Donthineni
Signed-off-by: Christopher Covington
---
arch/arm64/include/asm/cputype.h | 4
1
.
Signed-off-by: Christopher Covington
---
arch/arm64/kvm/hyp/tlb.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c
index 88e2f2b..9669e4b 100644
--- a/arch/arm64/kvm/hyp/tlb.c
+++ b/arch/arm64
Hi Christoffer,
On 01/04/2017 05:33 AM, Christoffer Dall wrote:
> On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote:
>> From: Shanker Donthineni
>>
>> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may
>> allocate TLB entr
On 01/03/2017 10:57 AM, Mark Rutland wrote:
> On Thu, Dec 29, 2016 at 05:43:34PM -0500, Christopher Covington wrote:
>> Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which
>> will allow an errata workaround that repeats tlbi dsb sequences to only
>> chan
On 01/03/2017 10:55 AM, Mark Rutland wrote:
> Hi,
>
> On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote:
>> +config QCOM_FALKOR_E1003_RESERVED_ASID
>> +int
>> +default 1
>> +depends on QCOM_FALKOR_ERRATUM_1003
>> +
>
>
On 12/29/2016 06:08 PM, Timur Tabi wrote:
> On 12/29/2016 04:43 PM, Christopher Covington wrote:
>> +config QCOM_FALKOR_E1003_RESERVED_ASID
>> +int
>> +default 1
>> +depends on QCOM_FALKOR_ERRATUM_1003
>
> Also, since this can't be changed via
On 12/29/2016 06:02 PM, Timur Tabi wrote:
> On 12/29/2016 04:43 PM, Christopher Covington wrote:
>> -| Implementor| Component | Erratum ID | Kconfig
>>|
>> -++-+-+---
During a TLB invalidate sequence targeting the inner shareable
domain, Falkor may prematurely complete the DSB before all loads
and stores using the old translation are observed; instruction
fetches are not subject to the conditions of this erratum.
Signed-off-by: Christopher Covington
Change
-by: Christopher Covington
---
arch/arm64/include/asm/tlbflush.h | 104 +-
1 file changed, 69 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index deab523..f28813c 100644
--- a/arch/arm64
.
Signed-off-by: Christopher Covington
---
arch/arm64/kvm/hyp/tlb.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c
index 88e2f2b..66e3f72 100644
--- a/arch/arm64/kvm/hyp/tlb.c
+++ b/arch/arm64/kvm/hyp/tlb.c
From: Shanker Donthineni
Define the MIDR implementer and part number field values for the Qualcomm
Datacenter Technologies Falkor processor version 1 in the usual manner.
Signed-off-by: Shanker Donthineni
Signed-off-by: Christopher Covington
---
arch/arm64/include/asm/cputype.h | 4
1
no TLB entries
with incorrect ASID after changing the the ASID.
Pseudo code:
write TTBRx_EL1[ASID] to a reserved value
ISB
write TTBRx_EL1[BADDR] to a desired value
ISB
write TTBRx_EL1[ASID] to a desired value
ISB
Signed-off-by: Shanker Donthineni
Signed-off-by: Christopher Covington
Hi Catalin,
On 12/08/2016 05:31 AM, Catalin Marinas wrote:
> On Wed, Dec 07, 2016 at 03:00:26PM -0500, Christopher Covington wrote:
>> From: Shanker Donthineni
>>
>> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may
>> allocate TLB entries u
Since the following commit, Infiniband and Ethernet have not been
mutually exclusive.
Fixes: 4aa17b28 mlx5: Enable mutual support for IB and Ethernet
Signed-off-by: Christopher Covington
---
drivers/net/ethernet/mellanox/mlx5/core/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a
: Shanker Donthineni
Signed-off-by: Christopher Covington
---
arch/arm64/Kconfig| 10 +
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/tlbflush.h | 43 +++
arch/arm64/kernel/cpu_errata.c| 7 +++
arch/arm64/kvm/hyp
From: Shanker Donthineni
This patch adds the cputype info for Qualcomm Technologies ARMv8 CPU
implementer ID 0x51 and part number for Falkor v1 in cputype.h.
Signed-off-by: Shanker Donthineni
Signed-off-by: Christopher Covington
---
arch/arm64/include/asm/cputype.h | 4
1 file changed
no TLB entries
with incorrect ASID after changing the the ASID.
Pseudo code:
write TTBRx_EL1[ASID] to a reserved value
ISB
write TTBRx_EL1[BADDR] to a desired value
ISB
write TTBRx_EL1[ASID] to a desired value
ISB
Signed-off-by: Shanker Donthineni
Signed-off-by: Christopher Covington
Hi Wei,
On 11/21/2016 03:24 PM, Wei Huang wrote:
> From: Christopher Covington
I really appreciate your work on these patches. If for any or all of these
you have more lines added/modified than me (or using any other better
metric), please make sure to change the author to be you with
`
Hi Bjorn,
On 11/02/2016 12:08 PM, Bjorn Helgaas wrote:
> On Tue, Nov 01, 2016 at 07:06:31AM -0600, c...@codeaurora.org wrote:
>> Hi Bjorn,
>>
>> On 2016-10-31 15:48, Bjorn Helgaas wrote:
>>> On Wed, Sep 21, 2016 at 06:38:05PM -0400, Christopher Covington wrote:
On 11/07/2016 12:16 PM, Dmitry Safonov wrote:
> On 11/07/2016 08:00 PM, Christopher Covington wrote:
>> Hi Dmitry,
>>
>> On 11/01/2016 01:22 PM, Dmitry Safonov wrote:
>>> Add vdso_mremap hook which will fix context.vdso pointer after mremap()
>>> on vDSO
we can do it on top.
> Separately, I've refactored arch_remap hook out from ppc64 [3].
>
> [1]: https://marc.info/?i=1448455781-26660-1-git-send-email-...@codeaurora.org
> [2]: https://github.com/xemul/criu/blob/master/Makefile#L39
> [3]: https://marc.info/?i=2016102717094
on to prctl(PR_SET_MM) or a flag
to clone. There is no prctl(PR_GET_MM). Instead such information is
expected to come from /proc//stat[m]. For the same extendability
reason, use a per-pid proc entry rather than a system-wide entry like
/proc/sys/vm/mmap_min_addr.
Signed-off-by: Christopher Covi
As suggested by Documentation/CodingStyle right before section 3.1: Spaces,
use braces on all branches of a conditional statement if they are used on
any branch. No functional changes.
Signed-off-by: Christopher Covington
---
fs/proc/array.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Make alignment and tab usage consistent across file. No functional changes.
Signed-off-by: Christopher Covington
---
include/uapi/linux/auxvec.h | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/include/uapi/linux/auxvec.h b/include/uapi/linux/auxvec.h
index 835c065
On November 1, 2016 11:23:54 AM MDT, Dmitry Safonov <0x7f454...@gmail.com>
wrote:
>Hi Christopher,
>
> by this moment I got another patch for this. I hope, you don't mind
>if I send it concurrently. I haven't sent it yet as I was testing it in
> qemu.
Please do, that'd be great.
Thanks,
Cov
mm->context.vdso, opt-in to VDSO unmap and remap support.
Signed-off-by: Christopher Covington
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 969ef88..534df3f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kcon
ation. This is hopefully the beginning of a long process of VDSO
code de-duplication between architectures.
Signed-off-by: Christopher Covington
---
include/asm-generic/mm_hooks.h | 35 ---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/includ
Use an unsigned long type for the base address of the VDSO in order to be
compatible with the new generic VDSO remap and unmap functions originating
from PowerPC and now also used by 32-bit ARM.
Signed-off-by: Christopher Covington
---
arch/arm64/include/asm/mmu.h | 2 +-
arch/arm64/kernel
(and it's also concise). Therefore, change the variable name in
powerpc from mm->context.vdso_base to mm->context.vdso.
Signed-off-by: Christopher Covington
---
arch/powerpc/include/asm/book3s/32/mmu-hash.h | 2 +-
arch/powerpc/include/asm/book3s/64/mmu.h | 2 +-
arch/powerpc/
off-by: Christopher Covington
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/Kbuild | 1 +
arch/powerpc/include/asm/mm-arch-hooks.h | 28 -
arch/powerpc/include/asm/mmu_context.h | 35 +---
4 files chan
for PowerPC and x86. However, a generic version based on Laurent Dufour's
PowerPC implementation is now available, so begin using it on ARM.
Signed-off-by: Christopher Covington
---
arch/arm/mm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kc
On 09/23/2016 03:17 PM, Bjorn Helgaas wrote:
> On Fri, Sep 23, 2016 at 02:41:39PM -0400, Christopher Covington wrote:
>> On 09/22/2016 07:08 PM, Bjorn Helgaas wrote:
>>> On Wed, Sep 21, 2016 at 06:40:47PM -0400, Christopher Covington wrote:
>>>> Hi Bjorn,
>>&
On 09/22/2016 07:08 PM, Bjorn Helgaas wrote:
> On Wed, Sep 21, 2016 at 06:40:47PM -0400, Christopher Covington wrote:
>> Hi Bjorn,
>>
>> On 09/21/2016 09:11 AM, Bjorn Helgaas wrote:
>>> On Tue, Sep 20, 2016 at 09:15:14PM -0400, c...@codeaurora.org wrote:
>
On 09/22/2016 05:49 AM, Lorenzo Pieralisi wrote:
> On Wed, Sep 21, 2016 at 01:04:57PM -0500, Bjorn Helgaas wrote:
>> On Wed, Sep 21, 2016 at 03:05:49PM +0100, Lorenzo Pieralisi wrote:
>>> On Tue, Sep 20, 2016 at 02:17:44PM -0500, Bjorn Helgaas wrote:
On Tue, Sep 20, 2016 at 04:09:25PM +0100, A
Hi Bjorn,
On 09/21/2016 09:11 AM, Bjorn Helgaas wrote:
> On Tue, Sep 20, 2016 at 09:15:14PM -0400, c...@codeaurora.org wrote:
>>> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
>>> index eb14f74..bb3b8ad 100644
>>> --- a/drivers/acpi/pci_mcfg.c
>>> +++ b/drivers/acpi/pci_mcfg.c
>>
The Qualcomm Technologies QDF2432 SoC does not support accesses smaller
than 32 bits to the PCI configuration space. Register the appropriate
quirk.
Signed-off-by: Christopher Covington
---
drivers/acpi/pci_mcfg.c | 8
drivers/pci/ecam.c | 10 ++
include/linux/pci
On 09/16/2016 05:02 AM, Gabriele Paoloni wrote:
> Hi Lorenzo and Tomasz
>
> Many Thanks for looking at this
>
>> -Original Message-
>> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
>> Sent: 15 September 2016 11:59
>> To: liudongdong (C)
>> Cc: Tomasz Nowicki; helg...@kernel.o
Hi Richard,
On 08/18/2016 08:17 AM, Richard Weinberger wrote:
> On Wed, Aug 17, 2016 at 1:12 PM, Christopher Covington
> wrote:
>>
>>
>> On August 17, 2016 6:30:06 AM EDT, Catalin Marinas
>> wrote:
>>> On Tue, Aug 16, 2016 at 02:32:29PM -0400, Christoph
the work by Leif Lindholm [3]
> Thanks to Peter Hurley for explaining how this should work.
>
> Should be applied to v4.8-rc1
> Tested on QEMU and ThunderX.
> SPCR support is included in QEMU's ARM64 mach-virt since 2.4 release.
Tested-by: Christopher Covington
on the QDF2
On August 17, 2016 6:30:06 AM EDT, Catalin Marinas
wrote:
>On Tue, Aug 16, 2016 at 02:32:29PM -0400, Christopher Covington wrote:
>> Some userspace applications need to know the maximum virtual address
>they can
>> use (TASK_SIZE).
>
>Just curious, what are the cases n
>
> Can you check if ACPI processor idle works with this patch on QDF2432 ?
This fixes the boot hang, and I see the usage and time files in cpuidle
sysfs increasing on an idle system.
Tested-by: Christopher Covington
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qual
.
Signed-off-by: Christopher Covington
---
Tested with the following commands:
LD_SHOW_AUXV=1 sleep 1 # GNU dynamic ld-linux*.so
hexdump -v -e '4/4 "%08x " "\n"' /proc/self/auxv | \
sed -r 's/0*([^ ]+) ([^ ]+) ([^ ]+) ([^ ]+)/\1 0x\4\3/
s/^0 /NUL
Hi Sudeep,
On 08/02/2016 09:00 AM, Sudeep Holla wrote:
>
> On 29/07/16 20:05, Christopher Covington wrote:
>> Hi Sudeep,
>>
>> On 07/19/2016 01:52 PM, Sudeep Holla wrote:
>>> Now that ACPI processor idle driver supports LPI(Low Power Idle), lets
>>>
From: Brent DeGraaf
Prior gettimeofday code register read code is not architecturally
correct as there is no control flow gating logic enforced
immediately prior to the required isb. Introduce explicit
control-flow logic prior to register read in all cases so that
the mrs read will always be don
Hi Joe,
I noticed 4cad35a7ca690eabf0d241062ce9e59693ec03e7 has caused the
following change in behavior:
c=4cad35a7ca690eabf0d241062ce9e59693ec03e7
git show -n 1 $c | scripts/get_maintainer.pl
sh: 1: STDIN: not found
sh: 1: STDIN: not found
fatal: --follow requires exactly one pathspec
git revert
e is not &STDIN before checking the VCS.
>
> Fixes: 4cad35a7ca69 ("get_maintainer.pl: reduce need for command-line option
> -f")
> Reported-by: Christopher Covington
> Signed-off-by: Joe Perches
Thanks Joe, that fixes it!
Tested-by: Christopher Covington
> ---
Hi Stuart,
On 07/01/2016 11:54 AM, Stuart Yoder wrote:
> Re-opening a thread from back in early 2015...
>
>> -Original Message-
>> From: Jon Masters
>> Date: Wed, Jan 14, 2015 at 11:18 AM
>> Subject: Re: sysfs topology for arm64 cluster_id
>> To: Mark Rutland
>> Cc: "linux-arm-ker...@li
_FREQ_PSS if X86 || IA64
> default y
> help
>
This causes a boot hang on QDF2432. cpuidle.off=1 works around the
problem. I understand you're working on a fix to the problem in GICv3
code. If there's anything I can do to help, please let me know.
Thanks,
Christopher Covi
Hi Marc,
On 06/22/2016 09:34 PM, Hanjun Guo wrote:
> On 2016/6/22 22:51, Marc Zyngier wrote:
>> On 22/06/16 14:52, Tomasz Nowicki wrote:
>>> On 22.06.2016 15:25, Marc Zyngier wrote:
On 22/06/16 13:35, Tomasz Nowicki wrote:
> IORT shows representation of IO topology for ARM based systems.
On 07/01/2016 10:14 AM, Timur Tabi wrote:
> Christopher Covington wrote:
>> arch/arm64/configs/defconfig | 4
>> scripts/patch-details.sh | 21 ++---
>
> I don't think these two files should be combined.
Oops, sorry. Fixed in v2.
&
Now that ACPI is on in the defconfig, the time seems right to enable
drivers for the SD/MMC, DMA, and pin control hardware described in the ACPI
tables of the QDF2432 server platform.
Signed-off-by: Christopher Covington
---
v2: Remove unrelated script changes.
---
arch/arm64/configs/defconfig
Now that ACPI is on in the defconfig, the time seems right to enable
drivers for the SD/MMC, DMA, and pin control hardware described in the ACPI
tables of the QDF2432 server platform.
Signed-off-by: Christopher Covington
---
arch/arm64/configs/defconfig | 4
scripts/patch-details.sh
Hi Arnd,
On 06/30/2016 07:52 AM, Arnd Bergmann wrote:
> On Thursday, June 30, 2016 7:35:14 AM CEST Christopher Covington wrote:
>> Hi Arnd,
>>
>> On 06/08/2016 05:02 PM, Arnd Bergmann wrote:
>>> On Wednesday, June 8, 2016 12:19:44 PM CEST Austin Christ w
Hi Arnd,
On 06/08/2016 05:02 PM, Arnd Bergmann wrote:
> On Wednesday, June 8, 2016 12:19:44 PM CEST Austin Christ wrote:
>> + ret = device_property_read_u32(qup->dev,
>> + "src-clock-hz", &src_clk_freq);
>> + if (ret) {
>> +
Hi Tomasz,
On 06/29/2016 06:48 AM, Tomasz Nowicki wrote:
> On 28.06.2016 18:12, Duc Dang wrote:
>> On Tue, Jun 28, 2016 at 6:04 AM, Christopher Covington
>> wrote:
>>> Hi Tomasz,
>>> Ard's comments on v3 included:
>>>
>>> "... exact O
Hi Tomasz,
On 06/28/2016 03:54 AM, Tomasz Nowicki wrote:
> diff --git a/drivers/pci/host/mcfg-quirks.c b/drivers/pci/host/mcfg-quirks.c
> new file mode 100644
> index 000..fb2b184
> --- /dev/null
> +++ b/drivers/pci/host/mcfg-quirks.c
> @@ -0,0 +1,88 @@
> +static bool pci_mcfg_fixup_match(st
Hi Duc,
On 06/20/2016 05:42 AM, Lorenzo Pieralisi wrote:
> On Fri, Jun 17, 2016 at 02:37:02PM -0700, Duc Dang wrote:
>> On Thu, Jun 16, 2016 at 10:48 AM, Lorenzo Pieralisi
>> wrote:
>>> On Wed, Jun 15, 2016 at 11:34:11AM -0400, Christopher Covington wrote:
&
On 06/17/2016 04:01 AM, Gabriele Paoloni wrote:
> Hi Lorenzo and All
>
>> -Original Message-
>> From: Lorenzo Pieralisi [mailto:lorenzo.pieral...@arm.com]
>> Sent: 16 June 2016 18:49
>> To: Christopher Covington
>> Cc: Tomasz Nowicki; Duc Dang; li
: Tomasz Nowicki
Signed-off-by: Dongdong Liu
Signed-off-by: Christopher Covington
---
Changes from v2 to v3:
* Match against all three of oem_id, oem_table_id, and oem_revision.
* Perform substring match, so padding oem_id and oem_table_id isn't
required. (Using min_t() thanks to Duc Dan
From: Tomasz Nowicki
pci_generic_ecam_ops is used by default. Since there are platforms
which have non-compliant ECAM space we need to overwrite these
accessors prior to PCI buses enumeration. In order to do that
we call pci_mcfg_get_ops to retrieve pci_ecam_ops structure so that
we can use prope
Hi Dongdong,
On 06/13/2016 09:02 AM, Dongdong Liu wrote:
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index d3c3e85..49612b3 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -22,6 +22,10 @@
> #include
> #include
> #include
> +#include
> +
> +
Hi Tomasz,
Thanks for your work on this.
On 06/02/2016 04:41 AM, Tomasz Nowicki wrote:
> Some platforms may not be fully compliant with generic set of PCI config
> accessors. For these cases we implement the way to overwrite accessors
> set. Algorithm traverses available quirk list, matches again
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