Wonder what happened there?
>
> Looks like Chip's address got mangled too.
You can find me at <[EMAIL PROTECTED]> or <[EMAIL PROTECTED]> these
days, although <[EMAIL PROTECTED]> still works for the time
being.
Chip
- --
Charles M. "Chip" Coldwell
Senior
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On Tue, 18 Dec 2007, Haavard Skinnemoen wrote:
> From: Chip Coldwell <[EMAIL PROTECTED]>
>
> This patch is based on the DMA-patch by Chip Coldwell for the
> AT91/AT32 serial USARTS, with some tweaks to make it apply neatly on
nd recorded in the IRR if I understand the
Intel documentation correctly.
So I think the scenario which leaves IRR set when the kdump kernel
starts is possible.
Chip
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Charles M. "Chip" Coldwell
Senior Software Engineer
Red Hat, Inc
978-392-2426
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current TPR. If the interrupt has a higher priority, then the
processor is interrupted, otherwise the interrupt is kept pending.
So, I think if the CPU has interrupts disabled, but the Local APIC
does not, the IRR could get set. I guess we need to be sure to turn
off the Local APIC first befo
tt_base[iommu_page] = GPTE_ENCODE(addr);
SET_LEAK(iommu_page);
+ GATT_CLFLUSH(iommu_page);
addr += PAGE_SIZE;
iommu_page++;
}
Chip
--
Charles M. "Chip" Coldwell
Senior S
long-term solution for the problem.
In the past we saw corruptions from such conflicts, so this is more
than just theory. I suspect you traded a more easy to trigger
corruption with a more subtle one.
Yup. That was the inspiration for the script.
Chip
--
Charles M. "Chip" Cold
On Wed, 17 Jan 2007, Chip Coldwell wrote:
On Wed, 17 Jan 2007, Andi Kleen wrote:
On Wednesday 17 January 2007 07:31, Chris Wedgwood wrote:
On Tue, Jan 16, 2007 at 08:52:32PM +0100, Christoph Anton Mitterer wrote:
I agree,... it seems drastic, but this is the only really secure
solution
write-combining MTRR for IOMMU aperture"
printf "base=0x%08x size=0x%08x type=write-combining\n" $base $size >/proc/mtrr
exit 0
[ -- cut here-- ]
Chip
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Charles M. "Chip" Coldwell
Senior Software Engineer
Red Hat, Inc
978-392-2426
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