[PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning

2021-01-14 Thread Chia-Wei, Wang
The LPC controller has no concept of the BMC and the Host partitions. This patch fixes the documentation by removing the description on LPC partitions. The register offsets illustrated in the DTS node examples are also fixed to adapt to the LPC DTS change. Signed-off-by: Chia-Wei, Wang

[PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2021-01-14 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++-- 1 file changed, 11 insertions(+), 6

[PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout

2021-01-14 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-- drivers/soc/aspeed/aspeed-lpc-snoop.c

[PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout

2021-01-14 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang Acked-by: Haiyue Wang --- drivers/char/ipmi/kcs_bmc_aspeed.c | 27 --- 1 file

[PATCH v5 0/5] Remove LPC register partitioning

2021-01-14 Thread Chia-Wei, Wang
check as suggested by Haiyue Wang. Changes since v2: - Add v2 binding check to ensure the synchronization between the device tree change and the driver register offset fix. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): dt

[PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions

2021-01-14 Thread Chia-Wei, Wang
,ast2500-lpc-v2" "aspeed,ast2600-lpc-v2" Signed-off-by: Chia-Wei, Wang --- arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++-- arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++- 3 files c

[PATCH 3/6] clk: ast2600: Add eSPI reset bit

2021-01-05 Thread Chia-Wei, Wang
Add bit field definition for the eSPI reset control. Signed-off-by: Chia-Wei, Wang --- include/dt-bindings/clock/ast2600-clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 62b9520a00fd

[PATCH 0/6] arm: aspeed: Add eSPI support

2021-01-05 Thread Chia-Wei, Wang
flash, and operates at max frequency of 66MHz. Chia-Wei, Wang (6): dt-bindings: aspeed: Add eSPI controller MAINTAINER: Add ASPEED eSPI driver entry clk: ast2600: Add eSPI reset bit irqchip/aspeed: Add Aspeed eSPI interrupt controller soc: aspeed: Add eSPI driver ARM: dts: aspeed: Add

[PATCH 6/6] ARM: dts: aspeed: Add AST2600 eSPI nodes

2021-01-05 Thread Chia-Wei, Wang
Add eSPI nodes for the device tree of Aspeed 6th generation SoCs. Signed-off-by: Chia-Wei, Wang --- arch/arm/boot/dts/aspeed-g6.dtsi | 57 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index

[PATCH 5/6] soc: aspeed: Add eSPI driver

2021-01-05 Thread Chia-Wei, Wang
The Aspeed eSPI controller is slave device to communicate with the master through the Enhanced Serial Peripheral Interface (eSPI). All of the four eSPI channels, namely peripheral, virtual wire, out-of-band, and flash are supported. Signed-off-by: Chia-Wei, Wang --- drivers/soc/aspeed/Kconfig

[PATCH 1/6] dt-bindings: aspeed: Add eSPI controller

2021-01-05 Thread Chia-Wei, Wang
Add dt-bindings and the inclusion header for Aspeed eSPI controller. Signed-off-by: Chia-Wei, Wang --- .../devicetree/bindings/soc/aspeed/espi.yaml | 252 ++ .../interrupt-controller/aspeed-espi-ic.h | 15 ++ 2 files changed, 267 insertions(+) create mode 100644

[PATCH 4/6] irqchip/aspeed: Add Aspeed eSPI interrupt controller

2021-01-05 Thread Chia-Wei, Wang
The eSPI interrupt controller acts as a SW IRQ number decoder to correctly control/dispatch interrupts of the eSPI peripheral, virtual wire, out-of-band, and flash channels. Signed-off-by: Chia-Wei, Wang --- drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-aspeed-espi-ic.c

[PATCH 2/6] MAINTAINER: Add ASPEED eSPI driver entry

2021-01-05 Thread Chia-Wei, Wang
Add myself and Ryan Chen as maintainer of the Aspeed eSPI driver and the associated eSPI interrupt controller. Joel Stanley is also added as the reviewer. Signed-off-by: Chia-Wei, Wang --- MAINTAINERS | 14 ++ 1 file changed, 14 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS

[PATCH v4 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2020-12-28 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++-- 1 file changed, 11 insertions(+), 6

[PATCH v4 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning

2020-12-28 Thread Chia-Wei, Wang
The LPC controller has no concept of the BMC and the Host partitions. This patch fixes the documentation by removing the description on LPC partitions. The register offsets illustrated in the DTS node examples are also fixed to adapt to the LPC DTS change. Signed-off-by: Chia-Wei, Wang

[PATCH v4 5/5] soc: aspeed: Adapt to new LPC device tree layout

2020-12-28 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-- drivers/soc/aspeed/aspeed-lpc-snoop.c

[PATCH v4 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout

2020-12-28 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/char/ipmi/kcs_bmc_aspeed.c | 27 --- 1 file changed, 16 insertions

[PATCH v4 2/5] ARM: dts: Remove LPC BMC and Host partitions

2020-12-28 Thread Chia-Wei, Wang
,ast2500-lpc-v2" "aspeed,ast2600-lpc-v2" Signed-off-by: Chia-Wei, Wang --- arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++-- arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++- 3 files c

[PATCH v4 0/5] Remove LPC register partitioning

2020-12-28 Thread Chia-Wei, Wang
binding check to ensure the synchronization between the device tree change and the driver register offset fix. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): dt-bindings: aspeed-lpc: Remove LPC partitioning ARM: dts: Remove LPC

[PATCH v3 5/5] soc: aspeed: Adapt to new LPC device tree layout

2020-12-20 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-- drivers/soc/aspeed/aspeed-lpc-snoop.c

[PATCH v3 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout

2020-12-20 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/char/ipmi/kcs_bmc_aspeed.c | 35 ++ 1 file changed, 21 insertions

[PATCH v3 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout

2020-12-20 Thread Chia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei, Wang --- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 19 +-- 1 file changed, 13 insertions

[PATCH v3 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning

2020-12-20 Thread Chia-Wei, Wang
The LPC controller has no concept of the BMC and the Host partitions. This patch fixes the documentation by removing the description on LPC partitions. The register offsets illustrated in the DTS node examples are also fixed to adapt to the LPC DTS change. Signed-off-by: Chia-Wei, Wang

[PATCH v3 2/5] ARM: dts: Remove LPC BMC and Host partitions

2020-12-20 Thread Chia-Wei, Wang
,ast2500-lpc-v2" "aspeed,ast2600-lpc-v2" Signed-off-by: Chia-Wei, Wang --- arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++-- arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++- 3 files c

[PATCH v3 0/5] Remove LPC register partitioning

2020-12-20 Thread Chia-Wei, Wang
change and the driver register offset fix. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): dt-bindings: aspeed-lpc: Remove LPC partitioning ARM: dts: Remove LPC BMC and Host partitions ipmi: kcs: aspeed: Adapt to new LPC DTS layout

[PATCH v2 1/5] ARM: dts: Remove LPC BMC and Host partitions

2020-10-05 Thread Chia-Wei, Wang
parition boundary. (i.e. offset 80h) In addition, to be backward compatible, the newly added HW control bits could be located at any reserved bits over the LPC addressing space. Thereby, this patch removes the lpc-bmc and lpc-host child node and thus the LPC partitioning. Signed-off-by: Chia-Wei, Wang

[PATCH v2 3/5] ipmi: kcs: aspeed: Fix LPC register offsets

2020-10-05 Thread Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang --- drivers/char/ipmi/kcs_bmc_aspeed.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b

[PATCH v2 2/5] soc: aspeed: Fix LPC register offsets

2020-10-05 Thread Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +++--- drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +-- 2 files changed, 8 insertions(+), 9 deletions

[PATCH v2 5/5] dt-bindings: aspeed-lpc: Remove LPC partitioning

2020-10-05 Thread Chia-Wei, Wang
The LPC controller has no concept of the BMC and the Host partitions. This patch fixes the documentation by removing the description on LPC partitions. The register offsets illustrated in the DTS node examples are also fixed to adapt to the LPC DTS change. Signed-off-by: Chia-Wei, Wang

[PATCH v2 4/5] pinctrl: aspeed-g5: Fix LPC register offsets

2020-10-05 Thread Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang --- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

[PATCH v2 0/5] Remove LPC register partitioning

2020-10-05 Thread Chia-Wei, Wang
development and maintenance. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): ARM: dts: Remove LPC BMC and Host partitions soc: aspeed: Fix LPC register offsets ipmi: kcs: aspeed: Fix LPC register offsets pinctrl: aspeed-g5: Fix LPC

[PATCH 2/4] soc: aspeed: Fix LPC register offsets

2020-09-10 Thread Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +++--- drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +-- 2 files changed, 8 insertions(+), 9 deletions

[PATCH 0/4] Remove LPC register partitioning

2020-09-10 Thread Chia-Wei, Wang
development and maintenance. Chia-Wei, Wang (4): ARM: dts: Remove LPC BMC and Host partitions soc: aspeed: Fix LPC register offsets ipmi: kcs: aspeed: Fix LPC register offsets pinctrl: aspeed-g5: Fix LPC register offsets arch/arm/boot/dts/aspeed-g4.dtsi | 74 +-- arch

[PATCH 4/4] pinctrl: aspeed-g5: Fix LPC register offsets

2020-09-10 Thread Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang --- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

[PATCH 3/4] ipmi: kcs: aspeed: Fix LPC register offsets

2020-09-10 Thread Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed. Signed-off-by: Chia-Wei, Wang --- drivers/char/ipmi/kcs_bmc_aspeed.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b

[PATCH 1/4] ARM: dts: Remove LPC BMC and Host partitions

2020-09-10 Thread Chia-Wei, Wang
maintenance. Signed-off-by: Chia-Wei, Wang --- arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++-- arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++- 3 files changed, 148 insertions(+), 196

[PATCH 2/2] dt-bindings: peci: aspeed: Add AST2600 compatible

2019-10-01 Thread Chia-Wei, Wang
Document the AST2600 PECI controller compatible string. Signed-off-by: Chia-Wei, Wang --- Documentation/devicetree/bindings/peci/peci-aspeed.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/peci/peci-aspeed.txt b/Documentation/devicetree/bindings/peci

[PATCH 0/2] peci: aspeed: Add AST2600 compatible

2019-10-01 Thread Chia-Wei, Wang
Update the Aspeed PECI driver with the AST2600 compatible string. A new comptabile string is needed for the extended HW feature of AST2600. Chia-Wei, Wang (2): peci: aspeed: Add AST2600 compatible string dt-bindings: peci: aspeed: Add AST2600 compatible Documentation/devicetree/bindings

[PATCH 1/2] peci: aspeed: Add AST2600 compatible string

2019-10-01 Thread Chia-Wei, Wang
The AST2600 SoC contains the same register set as AST25xx. Signed-off-by: Chia-Wei, Wang --- drivers/peci/peci-aspeed.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/peci/peci-aspeed.c b/drivers/peci/peci-aspeed.c index 51cb2563ceb6..4eed119dc83b 100644 --- a/drivers/peci/peci