On Thu, Jan 16, 2025 at 10:46:46PM +0530, Manivannan Sadhasivam wrote:
> Hi,
>
> This series carries forward the effort to add Kselftest for PCI Endpoint
> Subsystem started by Aman Gupta [1] a while ago. I reworked the initial
> version
> based on another patch that fixes the return values of IO
On Mon, Dec 02, 2024 at 06:28:45PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Nov 29, 2024 at 01:55:37PM -0600, Bjorn Helgaas wrote:
> > On Fri, Nov 29, 2024 at 02:54:12PM +0530, Manivannan Sadhasivam wrote:
> > > On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default
On Fri, Nov 29, 2024 at 02:54:12PM +0530, Manivannan Sadhasivam wrote:
> On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default and software
> cannot change the type. So mark the those BARs as 64bit BARs and also mark
> the successive BAR1/BAR3 as RESERVED BARs so that the EPF drivers canno
On Mon, Nov 11, 2024 at 03:21:36PM +0800, Joseph Jang wrote:
> On 2024/10/19 3:34 AM, Bjorn Helgaas wrote:
> > On Tue, Sep 03, 2024 at 06:44:26PM -0700, Joseph Jang wrote:
> > > Validate there are no duplicate hwirq from the irq debug
> > > file system /sys/kernel/deb
On Tue, Sep 03, 2024 at 06:44:26PM -0700, Joseph Jang wrote:
> Validate there are no duplicate hwirq from the irq debug
> file system /sys/kernel/debug/irq/irqs/* per chip name.
>
> One example log show 2 duplicated hwirq in the irq debug
> file system.
>
> $ sudo cat /sys/kernel/debug/irq/irqs/1
On Tue, Apr 20, 2021 at 07:10:06AM +0100, Christoph Hellwig wrote:
> On Mon, Apr 19, 2021 at 05:30:49PM -0700, Rajat Jain wrote:
> > The current flag name "untrusted" is not correct as it is populated
> > using the firmware property "external-facing" for the parent ports. In
> > other words, the fi
On Mon, Mar 01, 2021 at 12:51:45PM +0530, chakravarthikulkarni wrote:
> In this commit fixed coding style for braces and comments.
>
> Signed-off-by: chakravarthikulkarni
Applied to pci/hotplug for v5.13, thanks!
I dropped the comment change because it's really one comment that
should remain co
nk this should be EXPORT_SYMBOL_GPL(), I can make this change
> but this requires Bjorn's ACK to go upstream (Bjorn, it is my fault,
> it was assigned to me on patchwork, now updated, please have a look).
Yep, looks good to me, and I agree it should be EXPORT_SYMBOL_GPL().
Acked-by: Bjorn Helgaas
> > >
> > > unsigned long __weak pci_address_to_pio(phys_addr_t address)
> > > {
> > > --
> > > 2.25.1
> > >
On Wed, Mar 24, 2021 at 11:05:03AM +0800, Jianjun Wang wrote:
> These series patches add pcie-mediatek-gen3.c and dt-bindings file to
> support new generation PCIe controller.
Incidental: b4 doesn't work on this thread, I suspect because the
usual subject line format is:
[PATCH v9 9/7]
instead
On Fri, Apr 16, 2021 at 07:15:37PM +0530, Vidya Sagar wrote:
> The PCIe controller in Tegra194 SoC is not completely ECAM-compliant.
> With the current hardware design limitations in place, ECAM can be enabled
> only for one controller (C5 controller to be precise) with bus numbers
> starting from
On Thu, Apr 15, 2021 at 04:30:22PM +0800, Jiapeng Chong wrote:
> Fix the following clang warning:
>
> drivers/pci/hotplug/shpchp_hpc.c:177:20: warning: unused function
> 'shpc_writeb' [-Wunused-function].
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
Applied to pci/hotplug for v5
[+cc Alex]
On Fri, Apr 09, 2021 at 11:26:33AM +0200, Ingmar Klein wrote:
> Edit: Retry, as I did not consider, that my mail-client would make this
> party html.
>
> Dear maintainers,
> I recently encountered an issue on my Proxmox server system, that
> includes a Qualcomm QCA6174 m.2 PCIe wifi mo
On Tue, Apr 06, 2021 at 08:06:37PM +0800, Huang Guobin wrote:
> From: Guobin Huang
>
> spinlock can be initialized automatically with DEFINE_SPINLOCK()
> rather than explicitly calling spin_lock_init().
>
> Reported-by: Hulk Robot
> Signed-off-by: Guobin Huang
Applied to pci/hotplug for v5.13
On Tue, Apr 13, 2021 at 10:39:16AM +0200, Pali Rohár wrote:
> On Monday 12 April 2021 14:27:40 Bjorn Helgaas wrote:
> > On Mon, Apr 12, 2021 at 02:46:02PM +0200, Pali Rohár wrote:
> > > Define new PCI_EXP_DEVCTL_PAYLOAD_* macros in linux/pci_regs.h header file
> > > f
e is no conflict and we can just expose the UID under the "index"
> attribute whenever UID Uniqueness Checking is active and get systemd's
> interface naming support for free.
>
> Signed-off-by: Niklas Schnelle
> Acked-by: Viktor Mihajlovski
This seems like a nice so
On Sat, Apr 10, 2021 at 01:22:18AM +0900, Kunihiko Hayashi wrote:
> This patch adds misc interrupt handler to detect and invoke PME/AER event.
>
> In UniPhier PCIe controller, PME/AER signals are assigned to the same
> signal as MSI by the internal logic. These signals should be detected by
> the
On Thu, Apr 08, 2021 at 07:13:38PM -0700, Dan Williams wrote:
> Hi Bjorn, thanks for taking a look.
>
> On Thu, Apr 8, 2021 at 3:42 PM Bjorn Helgaas wrote:
> >
> > [+cc Greg, Rafael, Matthew: device model questions]
> >
> > Hi Dan,
> >
> > On Thu, A
On Tue, Apr 13, 2021 at 11:42:15PM +0530, Vidya Sagar wrote:
> On 4/13/2021 3:23 AM, Bjorn Helgaas wrote:
> > The existing port services (AER, DPC, hotplug, etc) are things the
> > device advertises via the PCI Capabilities defined by the generic PCIe
> > spec, and in my op
[+cc Matthew for portdrv comment]
On Mon, Apr 12, 2021 at 10:31:02PM +0530, Vidya Sagar wrote:
> Hi
> I'm starting this mail to seek advice on the best approach to be taken to
> add support for the driver of the PCIe root port's DMA engine.
> To give some background, Tegra194's PCIe IPs are dual-m
On Mon, Apr 12, 2021 at 02:46:02PM +0200, Pali Rohár wrote:
> Define new PCI_EXP_DEVCTL_PAYLOAD_* macros in linux/pci_regs.h header file
> for Max Payload Size. Macros are defined in the same style as existing
> macros PCI_EXP_DEVCTL_READRQ_* macros.
>
> Signed-off-by: Pali Rohár
> ---
> include
On Thu, Apr 08, 2021 at 07:05:27PM +, Raphael Norwitz wrote:
> Like the Intel DC P3700 NVMe, the Intel P4510 NVMe exhibits a timeout
> failure when the driver tries to interact with the device to soon after
> an FLR. The same reset quirk the P3700 uses also resolves the failure
> for the P4510,
[+cc Greg, Rafael, Matthew: device model questions]
Hi Dan,
On Thu, Apr 01, 2021 at 07:31:20AM -0700, Dan Williams wrote:
> Once the cxl_root is established then other ports in the hierarchy can
> be attached. The cxl_port object, unlike cxl_root that is associated
> with host bridges, is associa
On Thu, Apr 08, 2021 at 09:22:52PM +0800, Yicong Yang wrote:
> On 2021/4/8 2:55, Bjorn Helgaas wrote:
> > On Tue, Apr 06, 2021 at 08:45:53PM +0800, Yicong Yang wrote:
> >> +On Kunpeng 930 SoC, the PCIe root complex is composed of several
> >> +PCIe cores.
>
> &
returns a PCI device.
>
> Signed-off-by: Feilong Lin
> Signed-off-by: Zhiqiang Liu
Applied with Rafael's reviewed-by to pci/hotplug for v5.13, thanks!
> --
> v2: rewrite subject and commit log as suggested by Bjorn Helgaas.
> ---
> drivers/pci/hotplug/acpiphp_glue.
eak.
> >
> > Fix it by calling pci_dev_put() to decrement its reference count after that
> > pci_get_slot() returns a PCI device.
> >
> > Signed-off-by: Feilong Lin
> > Signed-off-by: Zhiqiang Liu
> > --
> > v2: rewrite subject and commit log as sugge
Move important info in the subject earlier, e.g.,
docs: Add HiSilicon PTT device documentation
On Tue, Apr 06, 2021 at 08:45:53PM +0800, Yicong Yang wrote:
> Document the introduction and usage of HiSilicon PTT device driver.
>
> Signed-off-by: Yicong Yang
> ---
> Documentation/trace/hisi-pt
On Tue, Apr 06, 2021 at 05:28:25PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Currently the core struct dw_pcie includes both struct pcie_port
> and dw_pcie_ep and the RC and EP platform drivers directly
> includes the dw_pcie. So it results in a RC or EP platform driver
> has 2 indirect
On Thu, Apr 01, 2021 at 09:23:04PM +0300, Andy Shevchenko wrote:
> On Thu, Apr 01, 2021 at 11:42:56AM -0500, Bjorn Helgaas wrote:
> > On Thu, Apr 01, 2021 at 06:45:02PM +0300, Andy Shevchenko wrote:
> > > On Tue, Mar 09, 2021 at 09:42:52AM +0100, Henning Schild wrote:
> > &
On Thu, Apr 01, 2021 at 06:45:02PM +0300, Andy Shevchenko wrote:
> On Tue, Mar 09, 2021 at 09:42:52AM +0100, Henning Schild wrote:
> > Am Mon, 8 Mar 2021 19:42:21 -0600
> > schrieb Bjorn Helgaas :
> > > On Mon, Mar 08, 2021 at 09:16:50PM +0200, Andy Shevchenko wrote:
>
On Thu, Mar 25, 2021 at 07:57:51PM +0100, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> If PCI_D3cold is passed to acpi_pci_set_power_state() as the second
> argument and there is no ACPI D3cold support for the given device,
> the debug message printed by that function will state that th
On Wed, Mar 31, 2021 at 11:55:08PM +0800, Zhang Rui wrote:
> ...
> From e18c942855e2f51e814d057fff4dd951cd0d0907 Mon Sep 17 00:00:00 2001
> From: Zhang Rui
> Date: Wed, 31 Mar 2021 20:34:13 +0800
> Subject: [PATCH] ACPI: tables: FPDT: Fix 64bit alignment issue
>
> Some of the 64bit items in FPDT
On Sun, Mar 28, 2021 at 10:41:18PM +0800, Dejin Zheng wrote:
> It has a wrong modification to the xgene driver by the commit
> e2dcd20b1645a. it use devm_platform_ioremap_resource_byname() to
> simplify codes and remove the res variable, But the following code
> needs to use this res variable, So a
On Mon, Mar 29, 2021 at 04:47:59PM +0800, Kai-Heng Feng wrote:
> Built-in grahpics on HP EliteDesk 805 G6 doesn't work because graphics
> can't get the BAR it needs:
> [0.611504] pci_bus :00: root bus resource [mem
> 0x1002020-0x100303f window]
> [0.611505] pci_bus :00: roo
On Sun, Mar 28, 2021 at 12:04:35AM +0100, Heiner Kallweit wrote:
> On 26.03.2021 22:26, Bjorn Helgaas wrote:
> > [+cc Randy, Andrew (though I'm sure you have zero interest in this
> > ancient question :))]
> >
> > On Wed, Dec 09, 2020 at 09:31:21AM +0100, Heiner
On Fri, Mar 26, 2021 at 11:42:46PM +0200, Andy Shevchenko wrote:
> On Fri, Mar 26, 2021 at 04:26:55PM -0500, Bjorn Helgaas wrote:
> > [+cc Randy, Andrew (though I'm sure you have zero interest in this
> > ancient question :))]
> >
> > On Wed, Dec 09, 2020 at 0
[+cc Randy, Andrew (though I'm sure you have zero interest in this
ancient question :))]
On Wed, Dec 09, 2020 at 09:31:21AM +0100, Heiner Kallweit wrote:
> pci_set_mwi() and pci_try_set_mwi() do exactly the same, just that the
> former one is declared as __must_check. However also some callers of
On Fri, Mar 26, 2021 at 03:19:04PM -0400, Jim Quinlan wrote:
> The check was missing on PCIe resume.
"PCIe resume" isn't really a thing, per se. PCI/PCIe gives us device
power states (D0, D3hot, etc), and Linux power management builds
suspend/resume on top of those. Maybe:
Check for failure o
On Fri, Mar 26, 2021 at 03:19:01PM -0400, Jim Quinlan wrote:
> If any downstream device may wake up during S2/S3 suspend, we do not want
> to turn off its power when suspending.
>
> Signed-off-by: Jim Quinlan
> ---
> drivers/pci/controller/pcie-brcmstb.c | 58 +++
> 1 fil
On Fri, Mar 26, 2021 at 03:19:00PM -0400, Jim Quinlan wrote:
> Control of EP regulators by the RC is needed because of the chicken-and-egg
Can you expand "EP"? Not sure if this refers to "endpoint" or
something else.
If this refers to a device in a slot, I guess it isn't necessarily a
PCIe *endp
ice completely disappears from lspci output if any configuration
> register in the request is exclusive. Instead skip the actual
> configuration cycle on a per-access basis and return all f's as if the
> read had failed.
>
> Cc: Bjorn Helgaas
> Cc: Greg Kroah-Hartman
> Cc: J
I'd promote J721E earlier in subject so it doesn't get truncated, e.g.,
PCI: j721e: Add J721E PCI legacy interrupt support
On Thu, Mar 25, 2021 at 02:39:34PM +0530, Kishon Vijay Abraham I wrote:
> +static void j721e_pcie_legacy_irq_handler(struct irq_desc *desc)
> +{
> + int i;
> + u32
1f99cf3a ("PCI: dwc: Detect number of iATU windows")
Link: https://lore.kernel.org/r/20210125044803.4310-1-zhiqiang@nxp.com
Tested-by: Kunihiko Hayashi
Signed-off-by: Hou Zhiqiang
Signed-off-by: Bjorn Helgaas
Reviewed-by: Rob Herring
Cc: sta...@vger.kernel
tors() is a device-managed function.
>
> Suggested-by: Andy Shevchenko
> Signed-off-by: Dejin Zheng
Acked-by: Bjorn Helgaas
Let me know if you'd like me to take the series.
> ---
> v4 -> v5:
> - Remove the check of enable device in pcim_alloc_irq_vectors()
&
On Sun, Mar 21, 2021 at 01:51:08AM -0400, Tong Zhang wrote:
> There is an issue in the error path, which cpci_thread may remain NULL.
> Calling kthread_stop(cpci_thread) will trigger a BUG().
> It is better to check whether the thread is really created and started
> before stop it.
>
> [1.2928
On Mon, Mar 22, 2021 at 05:18:31PM +0800, Chunyan Zhang wrote:
> From: Hongtao Wu
>
> This series adds PCIe controller driver for Unisoc SoCs.
> This controller is based on DesignWare PCIe IP.
>
> Signed-off-by: Hongtao Wu
> Signed-off-by: Chunyan Zhang
> ---
> drivers/pci/controller/dwc/Kcon
On Sun, Mar 21, 2021 at 11:29:30PM +0800, Zhiqiang Liu wrote:
> From: Feilong Lin
>
> Repeated hot-plugging of pci devices for a virtual
> machine driven by virtio, we found that there is a
> leak in kmalloc-4k, which was confirmed as the memory
> of the pci_device structure. Then we found out th
[-cc Dilip (mail to him bounced)]
On Tue, Mar 23, 2021 at 11:01:15AM +0800, Jisheng Zhang wrote:
> On Mon, 22 Mar 2021 20:24:41 -0500 Bjorn Helgaas wrote:
> >
> > [+cc Kishon, Richard, Lucas, Dilip]
> >
> > On Mon, Mar 01, 2021 at 11:10:31AM +0800, Jisheng Zhang
[+cc Kishon, Richard, Lucas, Dilip]
On Mon, Mar 01, 2021 at 11:10:31AM +0800, Jisheng Zhang wrote:
> After we move dw_pcie_msi_init() into core -- dw_pcie_host_init(), the
> MSI stops working after resume. Because dw_pcie_host_init() is only
> called once during probe. To fix this issue, we move d
On Mon, Jan 25, 2021 at 12:48:03PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> In the dw_pcie_ep_init(), it depends on the detected iATU region
> numbers to allocate the in/outbound window management bit map.
> It fails after the commit 281f1f99cf3a ("PCI: dwc: Detect number
> of iATU win
[+cc Arnd (author of 37d6a0a6f470 ("PCI: Add
pci_register_host_bridge() interface"), which I think would make my
idea below possible), Marc (IRQ domains maintainer)]
On Sat, Mar 20, 2021 at 12:19:55AM +0800, Boqun Feng wrote:
> Currently, if an architecture selects CONFIG_PCI_DOMAINS_GENERIC, the
On Sat, Mar 20, 2021 at 12:19:54AM +0800, Boqun Feng wrote:
> Hi Bjorn,
>
> I'm currently working on virtual PCI support for Hyper-V ARM64 guests.
> Similar to virtual PCI on x86 Hyper-V guests, the PCI root bus is not
> probed via ACPI (or of), it's probed from Hyper-V VMbus, therefore it
Prime
On Fri, Mar 19, 2021 at 02:59:47PM +0200, Leon Romanovsky wrote:
> On Thu, Mar 18, 2021 at 07:34:56PM +0100, Enrico Weigelt, metux IT consult
> wrote:
> > On 18.03.21 18:22, Leon Romanovsky wrote:
> >
> > > Which email client do you use? Your responses are grouped as
> > > one huge block without
On Tue, Mar 16, 2021 at 10:08:47PM +0800, Chiqijun wrote:
> When multiple VFs do FLR at the same time, the firmware is
> processed serially, resulting in some VF FLRs being delayed more
> than 100ms, when the virtual machine restarts and the device
> driver is loaded, the firmware is doing the corr
On Mon, Mar 01, 2021 at 11:10:31AM +0800, Jisheng Zhang wrote:
> After we move dw_pcie_msi_init() into core -- dw_pcie_host_init(), the
> MSI stops working after resume. Because dw_pcie_host_init() is only
> called once during probe. To fix this issue, we move dw_pcie_msi_init()
> to dw_pcie_setup_
the single
> architecture hand-rolling. Both approach support ioport mmap through a
> special pfn range and not through magic pte attributes. Aliasing is
> therefore not a problem.
>
> The only difference in access checks left is that sysfs PCI mmap does
> not check for CAP_RAWIO.
On Fri, Mar 12, 2021 at 02:11:03PM -0800, Kuppuswamy, Sathyanarayanan wrote:
> On 3/12/21 1:33 PM, Bjorn Helgaas wrote:
> > On Mon, Mar 08, 2021 at 10:34:10PM -0800,
> > sathyanarayanan.kuppusw...@linux.intel.com wrote:
> > > From: Kuppuswamy Sathyanaraya
aby
Applied with Krzysztof's reviewed-by to pci/misc for v5.13, thanks!
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> ---
> include/linux/pci_ids.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
>
[+cc Lukas, pciehp expert]
On Mon, Mar 08, 2021 at 10:34:10PM -0800,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan
>
> When hotplug and DPC are both enabled on a Root port or
> Downstream Port, during DPC events that cause a DLLSC link
> down/up events, su
On Mon, Mar 08, 2021 at 02:21:30PM +, Antti Järvinen wrote:
> Some TI KeyStone C667X devices do no support bus/hot reset. Its PCIESS
> automatically disables LTSSM when secondary bus reset is received and
> device stops working. Prevent bus reset by adding quirk_no_bus_reset to
> the device. Wi
On Thu, Mar 11, 2021 at 04:31:32PM -0700, Logan Gunthorpe wrote:
> In order to use upstream_bridge_distance_warn() from a dma_map function,
> it must not sleep. However, pci_get_slot() takes the pci_bus_sem so it
> might sleep.
>
> In order to avoid this, try to get the host bridge's device from
>
all to use a passed in gfp_mask and don't print that
> message if the buffer fails to be allocated.
>
> Signed-off-by: Logan Gunthorpe
Acked-by: Bjorn Helgaas
> ---
> drivers/pci/p2pdma.c | 21 +++--
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
fore, can be used for
> indirect calls in instrumented code without tripping CFI checks.
>
> Signed-off-by: Sami Tolvanen
If you need it:
Acked-by: Bjorn Helgaas# pci.h
> ---
> include/linux/compiler-clang.h | 1 +
> include/linux/compiler_types.h | 4
> include
On Wed, Mar 10, 2021 at 10:02:55PM +0100, Arnd Bergmann wrote:
> On Wed, Mar 10, 2021 at 8:32 PM Bjorn Helgaas wrote:
> >
> > On Mon, Mar 08, 2021 at 04:24:46PM +0100, Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > > Compile-testing this dri
On Thu, Mar 11, 2021 at 03:12:23PM -0600, Bjorn Helgaas wrote:
> From: Bjorn Helgaas
>
> We now use the kernel.org patchwork instance. Update the links in
> MAINTAINERS.
>
> Signed-off-by: Bjorn Helgaas
I put this on for-linus for v5.12.
> ---
> MAINTAINERS | 4 +
From: Bjorn Helgaas
We now use the kernel.org patchwork instance. Update the links in
MAINTAINERS.
Signed-off-by: Bjorn Helgaas
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..a3c2e930b3d5 100644
--- a
On Thu, Jan 28, 2021 at 03:52:42PM +, Victor Ding wrote:
> Certain PCIe devices (e.g. GL9750) have high penalties (e.g. high Port
> T_POWER_ON) when exiting L1 but enter L1 aggressively. As a result,
> such devices enter and exit L1 frequently during pci_save_state and
> pci_restore_state; even
[+cc Daniel, Mika (author, reviewer of 3030df209aa8]
On Thu, Mar 11, 2021 at 10:11:35AM +0530, Shirish S wrote:
> From: Julian Schroeder
>
> This allows for an extra 10ms for the state transition.
> Currently only AMD PCO based APUs are covered by this table.
I'm really glad to see this coming
On Mon, Feb 22, 2021 at 09:17:17AM +0800, Qiuxu Zhuo wrote:
> Function rcec_assoc_rciep() incorrectly used "rciep->devfn" (a single
> byte encoding the device and function number) as the device number to
> check whether the corresponding bit was set in the RCiEPBitmap of the
> RCEC (Root Complex Ev
On Mon, Mar 08, 2021 at 04:24:46PM +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Compile-testing this driver without ECAM support results in a link
> failure:
>
> ld.lld: error: undefined symbol: pci_ecam_map_bus
> >>> referenced by pcie-al.c
> >>> pci/controller/dwc/pcie-a
ot; contains more information than "quirks"?
In the 03/13 commit log, s/appaling/appalling/ :)
In the patch, it sounds like the MSI capture address change might be
separable into its own patch? If it were separate, it would be easier
to see the problem/fix and watch for
> Signed-off-by: Thomas Gleixner
> Cc: "K. Y. Srinivasan"
> Cc: Haiyang Zhang
> Cc: Stephen Hemminger
> Cc: Wei Liu
> Cc: Lorenzo Pieralisi
> Cc: Rob Herring
> Cc: Bjorn Helgaas
> Cc: linux-hyp...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
Acked-b
On Mon, Mar 08, 2021 at 09:16:50PM +0200, Andy Shevchenko wrote:
> On Mon, Mar 08, 2021 at 12:52:12PM -0600, Bjorn Helgaas wrote:
> > On Mon, Mar 08, 2021 at 02:20:16PM +0200, Andy Shevchenko wrote:
> > > From: Jonathan Yong
> > >
> > > There is already one
If you update this, please fix the s/nPCI: /PCI: / in the subject
On Mon, Mar 08, 2021 at 02:50:37PM -0500, Jim Quinlan wrote:
> The Brcmstb PCIe RC uses a reset control "rescal" for certain chips. This
> reset implements a "pulse reset" so it matches more the reset/rearm
> calls instead of the d
On Mon, Mar 08, 2021 at 02:20:16PM +0200, Andy Shevchenko wrote:
> From: Jonathan Yong
>
> There is already one and at least one more user is coming which
> requires an access to Primary to Sideband bridge (P2SB) in order to
> get IO or MMIO bar hidden by BIOS. Create a library to access P2SB
> f
[+cc Krzysztof for .bus_shift below]
This is [2/2] but I don't see a [1/2]. Is there something missing?
On Sat, Jan 11, 2020 at 12:45:00AM +0530, Vidya Sagar wrote:
> The PCIe controller in Tegra194 SoC is not completely ECAM-compliant.
> With the current hardware design limitations in place, EC
On Fri, Mar 05, 2021 at 01:42:34PM +0530, Om Prakash Singh wrote:
> PCIe EP compliance expect PTM capabilities (ROOT_CAPABLE, RES_CAPABLE,
> CLK_GRAN) to be disabled.
I guess this is just enforcing the PCIe spec requirements that only
Root Ports, RCRBs, and Switches are allowed to set the PTM Resp
[+cc Rafael, linux-pm]
On Thu, Mar 04, 2021 at 02:07:18PM +0800, Kai-Heng Feng wrote:
> On Sat, Feb 27, 2021 at 2:17 AM Bjorn Helgaas wrote:
> > On Fri, Feb 26, 2021 at 02:31:31PM +0100, Heiner Kallweit wrote:
> > > On 26.02.2021 13:18, Kai-Heng Feng wrote:
> > > >
Make the subject like this:
PCI: fu740: Add SiFive FU740 PCIe host controller driver
since you're adding a "fu740" driver, not a "designware" driver.
Future commits will then look like:
PCI: fu740: ...
On Tue, Mar 02, 2021 at 06:59:16PM +0800, Greentime Hu wrote:
> From: Paul Walmsley
>
>
[+cc Alex, reset expert]
On Mon, Mar 01, 2021 at 06:12:21PM +0100, Pali Rohár wrote:
> Hello!
>
> PCIe card can be reset via in-band Hot Reset signal which can be
> triggered by PCIe bridge via Secondary Bus Reset bit in PCI config
> space.
>
> Kernel already exports sysfs node "reset" for trigg
On Fri, Feb 26, 2021 at 02:31:31PM +0100, Heiner Kallweit wrote:
> On 26.02.2021 13:18, Kai-Heng Feng wrote:
> > On Fri, Feb 26, 2021 at 8:10 PM Heiner Kallweit
> > wrote:
> >>
> >> On 26.02.2021 08:12, Kalle Valo wrote:
> >>> Kai-Heng Feng writes:
> >>>
> Now we have a generic D3 shutdown
On Thu, Feb 25, 2021 at 09:44:12AM -0800, Kuppuswamy, Sathyanarayanan wrote:
> On 2/25/21 6:37 AM, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > Compile-testing these drivers is currently broken. Enabling
> > it causes a couple of build failures though:
> >
> > drivers/pci/controller/pci-
14036.GA1586541@bjorn-Precision-5520
Enumeration:
- Remove unnecessary locking around _OSC (Bjorn Helgaas)
- Clarify message about _OSC failure (Bjorn Helgaas)
- Remove notification of PCIe bandwidth changes (Bjorn Helgaas)
On Wed, Feb 24, 2021 at 11:21:44AM -0800, Linus Torvalds wrote:
> On Wed, Feb 24, 2021 at 11:03 AM Bjorn Helgaas wrote:
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
> > tags/pci-v5.12-changes
>
> I pulled this, but I'm now unpullin
On Thu, Feb 25, 2021 at 07:21:31AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Commits
>
> 557fb5faf4ca ("PCI: qcom: Add support for ddrss_sf_tbu clock")
> 3d0e5cf9c062 ("dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for
> sm8250")
>
> are missing a Signed-off-by from their committer
2bd36c391515cba855b8db8ae5708154f1082b8e:
Merge branch 'remotes/lorenzo/pci/misc' (2021-02-24 11:17:05 -0600)
Enumeration:
- Remove unnecessary locking around _OSC (Bjorn Helgaas)
- Clarify message about _OSC failure (Bjo
On Tue, Feb 16, 2021 at 10:38:40AM +0800, Chen Lin wrote:
> From: Chen Lin
>
> Remove the 'acpiphp_callback' typedef as it is not used.
>
> Signed-off-by: Chen Lin
Applied to pci/hotplug for v5.12, thanks!
> ---
> drivers/pci/hotplug/acpiphp.h |3 ---
> 1 file changed, 3 deletions(-)
>
d by the vendor which aren't standard
> or shared between vendors.
>
> Signed-off-by: Gustavo Pimentel
Beautiful, thanks!
Acked-by: Bjorn Helgaas
> ---
> drivers/pci/pci.c | 30 ++
> include/linux/pci.h | 1 +
> 2 files changed, 31 in
On Thu, Feb 04, 2021 at 05:51:25PM +0800, mingchuang.q...@mediatek.com wrote:
> From: Mingchuang Qiao
>
> In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is
> configured in pci_configure_ltr(). If device and bridge both support LTR
> mechanism, the "LTR Mechanism Enable" bit
On Tue, Feb 02, 2021 at 11:03:32AM +0100, Geert Uytterhoeven wrote:
> Kmemleak reports:
>
> unreferenced object 0xc328de40 (size 64):
> comm "kworker/1:1", pid 21, jiffies 4294938212 (age 1484.670s)
> hex dump (first 32 bytes):
> 00 00 00 00 00 00 00 00 e0 d8 fc eb 00 00 00
[+cc Krzysztof, since he commented on a previous version]
[+cc Lukas, who previously proposed exactly what I suggest below,
sorry for repeating. I think Lukas was right to propose passing in
the vendor ID because it makes it easier to read the caller.]
When you post new versions of a series, plea
On Thu, Jan 21, 2021 at 05:55:47PM -0600, Bjorn Helgaas wrote:
> On Tue, Jan 12, 2021 at 03:36:43PM +, Antti Järvinen wrote:
> > TI C667X does not support bus/hot reset.
> > See https://e2e.ti.com/support/processors/f/791/t/954382
>
> You can cite the URL as the sou
On Tue, Feb 16, 2021 at 07:52:08AM +, Wasim Khan wrote:
> > -Original Message-
> > From: Bjorn Helgaas
> > Sent: Tuesday, February 16, 2021 2:43 AM
> > To: Wasim Khan (OSS)
> > Cc: bhelg...@google.com; linux-...@vger.kernel.org; linux-
> >
On Fri, Feb 12, 2021 at 11:08:56AM +0100, Wasim Khan wrote:
> From: Wasim Khan
>
> Log a message if all BARs of type 0 devices are of
> size zero. This can help detecting type 0 devices
> not reporting BAR size correctly.
I could be missing something, but I don't think we can do this. I
would t
[+cc Rafael, linux-pm]
On Thu, Feb 04, 2021 at 11:06:40PM +0100, Maximilian Luz wrote:
> On some devices and platforms, the initial platform power state is not
> in sync with the power state of the PCI device.
>
> pci_enable_device_flags() updates the state of a PCI device by reading
> from the P
o/
s/pci mmap/PCI mmap/
s/Both approach/Both approaches/
s/pfn/PFN/
s/pte/PTE/
> The only difference in access checks left is that sysfs PCI mmap does
> not check for CAP_RAWIO. I'm not really sure whether that should be
> added or not.
>
> Acked-by: Bjorn Helgaas
> Re
ially.
>
> v2: Improve commit message (Bjorn)
>
> Signed-off-by: Daniel Vetter
Acked-by: Bjorn Helgaas
I wish we weren't extending a known-racy mechanism to do this, but at
least we're not *adding* a brand new race.
> Cc: Stephen Rothwell
> Cc: Jason Gunthorpe
>
On Wed, Feb 10, 2021 at 12:22:35AM -0800, Kees Cook wrote:
> On Thu, Dec 17, 2020 at 04:50:41PM -0800, Joe Perches wrote:
> > On Thu, 2020-12-17 at 17:56 -0600, Bjorn Helgaas wrote:
> > > From: Bjorn Helgaas
> > >
> > > The lkml.org, marc.info, spinics.net,
drivers/pci/.
Add -DDEBUG to CFLAGS for all files below drivers/pci/ so CONFIG_PCI_DEBUG
applies to the entire hierarchy.
[bhelgaas: commit log]
Link:
https://lore.kernel.org/r/1612438215-33105-1-git-send-email-yangyic...@hisilicon.com
Signed-off-by: Junhao He
On Mon, Feb 08, 2021 at 04:01:57PM +0100, Martin Hundebøll wrote:
> Update pci_ids.h with the vendor ID for Silicom Denmark. The define is
> going to be referenced in driver(s) for FPGA accelerated smart NICs.
>
> Signed-off-by: Martin Hundebøll
Applied to pci/misc for v5.12 with reviewed-by fro
On Tue, Feb 09, 2021 at 03:28:16PM +, Gustavo Pimentel wrote:
> On Mon, Feb 8, 2021 at 22:53:54, Krzysztof Wilczyński
> wrote:
> > [...]
> > > Thanks for your review. I will wait for a couple of days, before sending
> > > a new version of this patch series based on your feedback.
> >
> > Th
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