On 2021/4/15, 10:44 PM,Rob Herringwrote:
>On Wed, Apr 14, 2021 at 10:44 PM Billy Tsai
wrote:
>>
>> Hi Rob,
>>
>> On 2021/4/15, 6:16 AM,Rob Herringwrote:
>>
>> On Wed, Apr 14, 2021 at 06:49:38PM +0800, Billy Tsai wrot
Hi Rob,
On 2021/4/15, 6:16 AM,Rob Herringwrote:
On Wed, Apr 14, 2021 at 06:49:38PM +0800, Billy Tsai wrote:
>> This patch adds device bindings for aspeed pwm-tach device which is a
>> multi-function device include pwn and tach function and pwm device which
>>
This patch adds device bindings for aspeed pwm-tach device which is a
multi-function device include pwn and tach function and pwm device which
should be the sub-node of pwm-tach device.
Signed-off-by: Billy Tsai
Change-Id: I18d9dea14c3a04e1b7e38ffecd49d45917b9b545
---
.../bindings/mfd/aspeed
This patch add the support of PWM controller which can be found at aspeed
ast2600 soc. The pwm supoorts up to 16 channels and it's part function
of multi-funciton device "pwm-tach controller".
Signed-off-by: Billy Tsai
---
drivers/pwm/Kconfig | 7 +
drivers/pwm/Makefi
ction
- Implement .get_state pwm api
Billy Tsai (2):
dt-bindings: Add bindings for aspeed pwm-tach and pwm.
pwm: Add Aspeed ast2600 PWM support
.../bindings/mfd/aspeed,ast2600-pwm-tach.yaml | 60
.../bindings/pwm/aspeed,ast2600-pwm.yaml | 44 +++
drivers/pwm/Kc
Thanks for your review
Best Regards,
Billy Tsai
On 2021/4/12, 8:35 PM,Uwe Kleine-Königwrote:
Hello Billy,
On Mon, Apr 12, 2021 at 05:54:56PM +0800, Billy Tsai wrote:
>> This patch add the support of PWM controller which can find at aspeed
>> ast2600 soc chip. Thi
Hi Rob,
Best Regards,
Billy Tsai
On 2021/4/12, 9:20 PM,Rob Herringwrote:
On Mon, 12 Apr 2021 17:54:55 +0800, Billy Tsai wrote:
>> This patch adds device bindings for aspeed pwm device which should be
>> the sub-node of aspeed,ast2600-pwm-tach.
>>
>&
Hi,
Best Regards,
Billy Tsai
On 2021/4/12, 8:55 PM,Uwe Kleine-Königwrote:
> Hello,
On Mon, Apr 12, 2021 at 05:54:54PM +0800, Billy Tsai wrote:
> + - Billy Tsai
> I object because the MTA at aspeedtech.com doesn't know this email
> address.
This is typ
Thanks for your review
Best Regards,
Billy Tsai
On 2021/4/12, 7:14 PM,Uwe Kleine-Königwrote:
>Hello,
>On Mon, Apr 12, 2021 at 05:54:57PM +0800, Billy Tsai wrote:
>> Add support for the pwm controller which can be found at aspeed ast2600
>> soc. This driver i
This patch add the support of PWM controller which can find at aspeed
ast2600 soc chip. This controller supoorts up to 16 channels.
Signed-off-by: Billy Tsai
---
drivers/pwm/pwm-aspeed-g6.c | 291
1 file changed, 291 insertions(+)
create mode 100644 drivers
Add support for the pwm controller which can be found at aspeed ast2600
soc. This driver is part function of multi-funciton of device "pwm-tach
controller".
Signed-off-by: Billy Tsai
---
drivers/pwm/Kconfig | 6 ++
drivers/pwm/Makefile | 1 +
2 files changed, 7 insertions(+)
di
The legacy driver of aspeed pwm is binding with tach controller and it
doesn't follow the pwm framworks usage. In addition, the pwm register
usage of the 6th generation of ast26xx has drastic change. So these
patch serials add the new aspeed pwm driver to fix up the problem above.
Billy Ts
This patch adds device bindings for aspeed pwm device which should be
the sub-node of aspeed,ast2600-pwm-tach.
Signed-off-by: Billy Tsai
---
.../bindings/pwm/aspeed,ast2600-pwm.yaml | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree
This patch adds device bindings for aspeed pwm-tach device which is a
multi-function device include pwn and tach function.
Signed-off-by: Billy Tsai
---
.../bindings/mfd/aspeed,ast2600-pwm-tach.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644
Documentation
The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
SCU414 to SCU4B4.
Signed-off-by: Billy Tsai
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
b/drivers/pinctrl
Hi Andrew,
Best Regards,
Billy Tsai
On 2020/12/17, 8:38 AM, Andrew Jeffery wrote:
> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
> SCU414 to SCU4B4.
> Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits
> at the same time.
The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
SCU414 to SCU4B4.
Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits
at the same time.
Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Billy Tsai
---
drive
Hi Joel,
On 2020/12/11, 6:55 PM, Joel Stanley wrote:
On Fri, 11 Dec 2020 at 03:18, Billy Tsai wrote:
>
> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
> SCU414 to SCU4B4.
> Besides that, When PWM8~15 of PWMG0 set it needs to clear SC
The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from
SCU414 to SCU4B4.
Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits at
the same time.
Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Billy Tsai
---
drive
Some gpio pin at aspeed soc is input only and the prefix name of these
pin is "GPI" only. This patch fine-tune the condition of GPIO check from
"GPIO" to "GPI".
Signed-off-by: Billy Tsai
---
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 2 +-
1 file changed, 1 ins
On 2020/10/26, 10:21 AM, Andrew Jeffery wrote:
On Mon, 26 Oct 2020, at 12:33, Billy Tsai wrote:
>
> On 2020/10/26, 9:27 AM, Andrew Jeffery wrote:
>
> On Mon, 12 Oct 2020, at 14:01, Billy Tsai wrote:
> > > At ast2600a1 we cha
On 2020/10/26, 9:27 AM, Andrew Jeffery wrote:
On Mon, 12 Oct 2020, at 14:01, Billy Tsai wrote:
> > At ast2600a1 we change feature of master sgpio to 2 sets.
> > So this patch is used to add the pinctrl setting of the new sgpio.
> >
> > S
This patch organizes the define of adc to multiple partitions
and adds the new bit field define for ast2600 driver.
Signed-off-by: Billy Tsai
---
drivers/iio/adc/aspeed_adc.c | 42
1 file changed, 38 insertions(+), 4 deletions(-)
diff --git a/drivers/iio
This patch is used to handle the difference between ast2600
and previous versions.
Signed-off-by: Billy Tsai
---
drivers/iio/adc/aspeed_adc.c | 129 ++-
1 file changed, 95 insertions(+), 34 deletions(-)
diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc
extend the field length of the scaler.
4. Ref_voltage becomes configurable.
Billy Tsai (3):
iio: adc: aspeed: Orgnaize and add the define of adc
iio: adc: aspeed: Make driver compatible with ast2600
iio: adc: aspeed: Setting ref_voltage in probe
.../bindings/iio/adc/aspeed_adc.txt
At ast2600 ref_voltage becomes configurable and this property is board
dependency.
Signed-off-by: Billy Tsai
---
.../devicetree/bindings/iio/adc/aspeed_adc.txt | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iio/adc
Hi Joel,
On 2020/10/8, 11:49 AM, Joel Stanley wrote:
On Thu, 8 Oct 2020 at 01:51, Billy Tsai wrote:
> >
> > This patch is used to add sgpiom and sgpios nodes and add pinctrl
setting
> > for sgpiom1
>
> The code looks good Billy.
>
&
Hi Joel,
Thanks for the review.
On 2020/10/12, 12:35 PM, Joel Stanley wrote:
> On Mon, 12 Oct 2020 at 03:32, Billy Tsai
wrote:
> >
> > This patch is used to add sgpiom and sgpios nodes and add compatible
> > string for sgpiom.
>
>
This patch series is used to add sgpiom and sgpios nodes and add pinctrl
setting for sgpiom1
v2:
- Split the change of dts and pinctrl to two commit.
- Add the compatible string for aspeed,ast2600-sgpiom.
aspeed,ast2600-sgpios will implement in the future.
Billy Tsai (3):
Arm: dts
This patch is used to add sgpiom and sgpios nodes and add compatiable
string for sgpiom.
Signed-off-by: Billy Tsai
---
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 8 +--
arch/arm/boot/dts/aspeed-g6.dtsi | 52 +++
2 files changed, 57 insertions(+), 3 deletions
This patch is used to fix the memory range of gpio0
Signed-off-by: Billy Tsai
---
arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 97ca743363d7..ad19dce038ea 100644
At ast2600a1 we change feature of master sgpio to 2 sets.
So this patch is used to add the pinctrl setting of the new sgpio.
Signed-off-by: Billy Tsai
---
arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 30 +++---
2 files
Hi Joel,
Thanks for your advice.
On 2020/10/8, 11:49 AM, Joel Stanley wrote:
> On Thu, 8 Oct 2020 at 01:51, Billy Tsai wrote:
> >
> > This patch is used to add sgpiom and sgpios nodes and add pinctrl
setting
> > for sgpiom1
>
>
Fix the memory layout and add sgpio node for aspeed g6
Billy Tsai (2):
Arm: dts: aspeed-g6: Fix the register range of gpio
Arm: dts: aspeed-g6: Add sgpio node and pinctrl setting
arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 ++
arch/arm/boot/dts/aspeed-g6.dtsi | 55
This patch is used to fix the memory range of gpio0
Signed-off-by: Billy Tsai
---
arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 97ca743363d7..ad19dce038ea 100644
This patch is used to add sgpiom and sgpios nodes and add pinctrl setting
for sgpiom1
Signed-off-by: Billy Tsai
---
arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 ++
arch/arm/boot/dts/aspeed-g6.dtsi | 53 ++
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 30
Hi Andrew,
On 2020/10/1, 8:36 AM, Andrew Jeffery wrote:
Hi Billy,
On Wed, 30 Sep 2020, at 14:41, Billy Tsai wrote:
> This commit add two sgpiom and two sgpios node into aspeed-g6.dtsi
> and change the register range of gpio0 to fix the hardware design.
>
Signed-off-by: Billy Tsai
---
arch/arm/boot/dts/aspeed-g6.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 97ca743363d7..b9ec8b579f73 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm
This commit add two sgpiom and two sgpios node into aspeed-g6.dtsi
and change the register range of gpio0 to fix the hardware design.
Signed-off-by: Billy Tsai
---
arch/arm/boot/dts/aspeed-g6.dtsi | 51 +++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git
39 matches
Mail list logo
