Thanks Lorenzo.
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: Wednesday, April 7, 2021 9:32 PM
> To: linux-...@vger.kernel.org; Bharat Kumar Gogada ;
> linux-kernel@vger.kernel.org
> Cc: lorenzo.pieral...@arm.com; bhelg...@google.com
> Subject: Re: [PATCH v3
Hi Lorenzo,
Any inputs on this ?
Regards,
Bharat
> -Original Message-
> From: Bharat Kumar Gogada
> Sent: Tuesday, March 23, 2021 4:48 PM
> To: Bharat Kumar Gogada ; linux-
> p...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelg...@google.com; Lorenzo Pieral
> Subject: Re: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains
>
> On Wed, 24 Mar 2021 13:56:16 +,
> Bharat Kumar Gogada wrote:
>
> > > Thanks for that. Can you please try the following patch and let me
> > > know if it helps?
> > >
> > &
> > Hi Marc,
> >
> > Thanks for the patch.
> >
> > > Subject: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains
> > >
> > > In anticipation of the removal of the msi_controller structure,
> > > convert the ancient xilinx host controller driver to MSI domains.
> > >
> > > We end-up with the usual
Hi Marc,
Thanks for the patch.
> Subject: [PATCH v2 05/15] PCI: xilinx: Convert to MSI domains
>
> In anticipation of the removal of the msi_controller structure, convert the
> ancient xilinx host controller driver to MSI domains.
>
> We end-up with the usual two domain structure, the top one
Thanks Marc for the patch.
> Subject: [PATCH v2 04/15] PCI: xilinx: Don't allocate extra memory for the
> MSI capture address
>
> A long cargo-culted behaviour of PCI drivers is to allocate memory to obtain
> an address that is fed to the controller as the MSI capture address (i.e. the
> MSI doorb
Ping.
> -Original Message-
> From: Bharat Kumar Gogada
> Sent: Monday, March 15, 2021 11:43 AM
> To: Bharat Kumar Gogada ; linux-
> p...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelg...@google.com
> Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable cohe
Ping.
> -Original Message-
> From: Bharat Kumar Gogada
> Sent: Monday, February 22, 2021 2:18 PM
> To: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelg...@google.com; Bharat Kumar Gogada
> Subject: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coheren
Add optional dma-coherent property to support coherent PCIe DMA traffic.
Signed-off-by: Bharat Kumar Gogada
---
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
b
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/pcie-xilinx-nwl.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
b/drivers/pci/controller/pcie-xilinx-nwl.c
index 07e36661bbc2..8689311c5ef6 100644
--- a/drivers/pci/controller/p
> Hi Bharat,
>
> Thank you for sending the patches over!
>
> > Add support for routing PCIe DMA traffic coherently when Cache
> > Coherent Interconnect (CCI) is enabled in the system.
> > The "dma-coherent" property is used to determine if CCI is enabled or
> > not.
> > Refer https://developer.ar
ned-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/pcie-xilinx-nwl.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
b/drivers/pci/controller/pcie-xilinx-nwl.c
index 07e36661bbc2..08e060574cb7 100644
--- a/drivers/pci/controller/pcie-xi
Add optional dma-coherent property to support coherent PCIe DMA traffic.
Signed-off-by: Bharat Kumar Gogada
---
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
b
> [+cc Rob]
>
> s/coherenct/coherent/ in subject
> s/traffic/DMA/ (this applies specifically to DMA, not to MMIO)
>
> On Thu, Jan 21, 2021 at 03:29:16PM +0530, Bharat Kumar Gogada wrote:
> > - Add support for routing PCIe traffic coherently when Cache Coherent
> >
- Add support for routing PCIe traffic coherently when
Cache Coherent Interconnect(CCI) is enabled in the system.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/pcie-xilinx-nwl.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> Subject: Re: [PATCH v9 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
>
> On Fri, Jul 10, 2020 at 09:16:57AM -0600, Rob Herring wrote:
> > On Tue, Jun 16, 2020 at 6:57 AM Bharat Kumar Gogada
> > wrote:
> > >
> > > - Add support for Versal CP
Hi All,
Gentle ping.
Regards,
Bharat
> -Original Message-
> From: Bharat Kumar Gogada
> Sent: Tuesday, June 16, 2020 6:27 PM
> To: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelg...@google.com; lorenzo.pieral...@arm.com; r...@kernel.org;
> m...@
interrupt line.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-xilinx-cpm.c | 617 +++
3 files changed, 626 insertions(+)
create mode 100644 drivers/pci
interrupts.
- Bridge error and legacy interrupts in Versal CPM are handled using
Versal CPM specific interrupt line.
Changes for v9:
- Removed interrupt enablement outside irqchip flow as suggested
by Marc.
- Removed using WARN_ON in if statement.
Bharat Kumar Gogada (2):
PCI: xilinx-cpm: Add
Add YAML schemas documentation for Versal CPM Root Port driver.
Signed-off-by: Bharat Kumar Gogada
---
.../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 99 ++
1 file changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal
> Subject: Re: [PATCH v8 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
>
> On Mon, Jun 08, 2020 at 06:48:58PM +0530, Bharat Kumar Gogada wrote:
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrate
> Subject: Re: [PATCH v8 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
>
> On 2020-06-11 16:51, Bharat Kumar Gogada wrote:
>
> [...]
>
> >> > +/**
> >> > + * xilinx_cpm_pcie_init_port - Initialize hardware
> >> > + * @port:
>
> Hi Bharat,
>
> On 2020-06-08 14:18, Bharat Kumar Gogada wrote:
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The
> > integrated
> > block for CPM along with the integrated bridge
.
Bharat Kumar Gogada (2):
PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port
PCI: xilinx-cpm: Add Versal CPM Root Port driver
.../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 99
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile
interrupt line.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-xilinx-cpm.c | 621 +++
3 files changed, 630 insertions
Add YAML schemas documentation for Versal CPM Root Port driver.
Signed-off-by: Bharat Kumar Gogada
---
.../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 99 ++
1 file changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal
> Bharat,
>
> On 2020-05-07 12:58, Bharat Kumar Gogada wrote:
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The
> > integrated
> > block for CPM along with the integrated bridge can function
>
> Subject: Re: [PATCH v7 1/2] PCI: xilinx-cpm: Add YAML schemas for Versal
> CPM Root Port
>
> On Thu, May 07, 2020 at 05:28:35PM +0530, Bharat Kumar Gogada wrote:
> > Add YAML schemas documentation for Versal CPM Root Port driver.
> >
> > Sign
Hi Rob,
Can you please let us know if you have any inputs on this.
Regards,
Bharat
> -Original Message-
> From: Bharat Kumar Gogada
> Sent: Thursday, May 7, 2020 5:29 PM
> To: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: lorenzo.pieral...@arm.com; bhel
> Subject: Re: [PATCH v7 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
>
> On Thu, May 07, 2020 at 05:28:36PM +0530, Bharat Kumar Gogada wrote:
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrate
interrupt line.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-xilinx-cpm.c | 506 +++
3 files changed, 516 insertions(+)
create mode 100644 drivers/pci
Add YAML schemas documentation for Versal CPM Root Port driver.
Signed-off-by: Bharat Kumar Gogada
---
.../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 105 +
1 file changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal
interrupts.
- Bridge error and legacy interrupts in Versal CPM are handled using
Versal CPM specific interrupt line.
Changes for v7:
- Adding device tree documentation as schema.
- Using pci_host_probe for registering bridge.
Bharat Kumar Gogada (2):
PCI: xilinx-cpm: Add YAML schemas for Versal
> Subject: Re: [PATCH v6 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
>
> On Fri, Apr 24, 2020 at 05:34:04PM +0530, Bharat Kumar Gogada wrote:
> > - Add support for Versal CPM as Root Port.
> > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrate
> On Fri, Apr 24, 2020 at 05:34:03PM +0530, Bharat Kumar Gogada wrote:
> > Add device tree binding documentation for Versal CPM Root Port driver.
> >
> > Signed-off-by: Bharat Kumar Gogada
> > ---
> > .../devicetree/bindings/pci/xilinx-versal-cpm.txt | 68
>
Hi All,
We are testing NVMe cards on ARM64 platform, the card uses MSI-X interrupts.
We are hitting following case in drivers/nvme/host/pci.c
/*
* Did we miss an interrupt?
*/
if (__nvme_poll(nvmeq, req->tag)) {
dev_warn(dev->ctrl.device,
> On Sat, Jun 22, 2019 at 11:40:29PM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > In commit
> >
> > 46c1bfcfcd87 ("PCI: xilinx-nwl: Fix Multi MSI data programming")
> >
> > Fixes tag
> >
> > Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL
> > PCIe
> >
> > has these probl
>
> On Wed, Jun 12, 2019 at 03:47:59PM +0530, Bharat Kumar Gogada wrote:
> > The current Multi MSI data programming fails if multiple end points
> > requesting MSI and multi MSI are connected with switch, i.e the
> > current multi MSI data being given is not considering t
ndled.
Fix Multi MSI data programming with required alignment by
using number of vectors being requested.
Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
Host Controller")
Signed-off-by: Bharat Kumar Gogada
---
V4:
- Using a different bitmap registration API whci
> On 31/05/2019 17:09, Lorenzo Pieralisi wrote:
> > [+Marc]
> >
> > On Wed, May 29, 2019 at 06:07:49PM +0530, Bharat Kumar Gogada wrote:
> >> The current Multi MSI data programming fails if multiple end points
> >> requesting MSI and multi MSI are connected
ndled.
Fix Multi MSI data programming with required alignment by
using number of vectors being requested.
Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
Host Controller")
Signed-off-by: Bharat Kumar Gogada
---
V3:
- Added example description of the issue
-
> Subject: Re: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
>
> On Mon, 11 Mar 2019 at 12:46, Bharat Kumar Gogada
> wrote:
> >
> > The current Multi MSI data programming fails if multiple end points
> > requesting MSI and multi MSI are connected wi
> On Mon, Apr 01, 2019 at 05:00:40PM +0000, Bharat Kumar Gogada wrote:
> > Hi All,
> >
> > Please let me know if anyone has any inputs on this.
> >
> > Regards,
> > Bharat
> > >
> > > The current Multi MSI data programming fails if m
ing with required alignment by using number
> of vectors being requested.
>
> Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host
> Controller")
> Signed-off-by: Bharat Kumar Gogada
> ---
> V2:
> - Added more description of fix
> ---
>
ilinx NWL PCIe
Host Controller")
Signed-off-by: Bharat Kumar Gogada
---
V2:
- Added more description of fix
---
drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
b/drivers/pci/controller/p
> Subject: Re: [PATCH] PCI: xilinx-nwl: Fix Multi MSI data programming
>
> On Wed, Feb 13, 2019 at 07:55:39PM +0530, Bharat Kumar Gogada wrote:
> > The current Multi MSI data programming fails if a end point is
> > connected with switch.
> >
> > Fix Multi M
The current Multi MSI data programming fails if a
end point is connected with switch.
Fix Multi MSI data, by programming data with required alignment.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
t; Currently PCI_BRIDGE_CTL_SERR is being enabled only in ACPI flow.
> This patch enables PCI_BRIDGE_CTL_SERR for Type-1 PCI device.
>
> Signed-off-by: Bharat Kumar Gogada
> ---
> drivers/pci/probe.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
Hi All,
Please let me know if anyone has any issue with this patch series.
Regards,
Bharat
> -Original Message-
> From: Bharat Kumar Gogada [mailto:bharat.kumar.gog...@xilinx.com]
> Sent: Wednesday, November 14, 2018 8:18 PM
> To: linux-kernel@vger.kernel.org
> Cc: bhel
Adding method pci_check_platform_service_irqs to check if platform
has registered method to proivde dedicated IRQ lines for PCIe services
like AER.
Signed-off-by: Bharat Kumar Gogada
---
include/linux/pci.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/include/linux
for Type-1 PCI device.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/probe.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index b1c05b5..ed71e8e 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
.
This hook is to register platform IRQ's to PCIe port services.
Signed-off-by: Bharat Kumar Gogada
---
include/linux/pci.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 11c71c4..28e5e06b 100644
--- a/include/linux/pci.h
+++ b/include/
Add nwl_setup_service_irqs hook to setup_platform_service_irq to
register platform provided IRQ number to kernel AER service.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/pcie-xilinx-nwl.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller
Platforms may have dedicated IRQ lines for PCIe services like
AER/PME etc., check for such IRQ lines.
Check if platform has any dedicated IRQ lines for PCIe
services.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/pcie/portdrv_core.c | 8
1 file changed, 8 insertions(+)
diff --git
of platforms to register the
platform IRQ number with respective PCIe services.
Bharat Kumar Gogada (4):
PCI: Add setup_platform_service_irq hook to struct pci_host_bridge
PCI: Add pci_check_platform_service_irqs
PCI/portdrv: Check platform supported service IRQ's
PCI: xilinx-nwl: Add m
> Subject: Re: [PATCH 3/4] PCI/portdrv: Check platform supported service IRQ's
>
> On Fri, Aug 10, 2018 at 09:09:39PM +0530, Bharat Kumar Gogada wrote:
> > Platforms may have dedicated IRQ lines for PCIe services like AER/PME
> > etc., check for such IRQ lines.
> >
> Subject: Re: [PATCH 4/4] PCI: xilinx-nwl: Add method to
> setup_platform_service_irq hook
>
> On Fri, Aug 10, 2018 at 09:09:40PM +0530, Bharat Kumar Gogada wrote:
> > Add nwl_setup_service_irqs hook to setup_platform_service_irq IRQs to
> > register platform provided
MSI/MSI-X/INTx
> interrupts for these services.
> These patches will add new method for these kind of platforms to register
> the platform IRQ number with respective PCIe services.
>
> Bharat Kumar Gogada (4):
> PCI: Add setup_platform_service_irq hook to st
> Subject: Re: [PATCH v2] PCI/AER: Enable SERR# forwarding in non ACPI flow
>
> On 2018-08-09 20:27, Bharat Kumar Gogada wrote:
> > As per Figure 6-3 in PCIe r4.0, sec 6.2.6, ERR_ messages will be
> > forwarded from the secondary interface to the primary interface, if
> &
Agreed, will Fix it in next version.
Regards,
Bharat
> -Original Message-
> From: kbuild test robot [mailto:l...@intel.com]
> Sent: Monday, August 13, 2018 2:39 PM
> To: Bharat Kumar Gogada
> Cc: kbuild-...@01.org; linux-...@vger.kernel.org; linux-
> ker...@vger
Add setup_platform_service_irq hook to struct pci_host_bridge.
Some platforms have dedicated interrupt line from root complex to
interrupt controller for PCIe services like AER/PME etc.
This hook is to register platform IRQ's to PCIe port services.
Signed-off-by: Bharat Kumar Gogada
---
in
Add nwl_setup_service_irqs hook to setup_platform_service_irq IRQs to
register platform provided IRQ number to kernel AER service.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/pcie-xilinx-nwl.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff
of platforms
to register the platform IRQ number with respective PCIe services.
Bharat Kumar Gogada (4):
PCI: Add setup_platform_service_irq hook to struct pci_host_bridge
PCI: Add pci_check_platform_service_irqs
PCI/portdrv: Check platform supported service IRQ's
PCI: xilinx-nwl: Add m
Platforms may have dedicated IRQ lines for PCIe services like
AER/PME etc., check for such IRQ lines.
Check mask and fill legacy irq line for services other than
platform supported service IRQ number.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/pcie/portdrv_core.c | 19
Adding method pci_check_platform_service_irqs to check if platform
has registered method to proivde dedicated IRQ lines for PCIe services
like AER/PME etc.
Signed-off-by: Bharat Kumar Gogada
---
include/linux/pci.h | 24
1 files changed, 24 insertions(+), 0 deletions
for Type-1 PCI device.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/pcie/aer.c | 23 +++
1 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index a2e8838..4fb0d24 100644
--- a/drivers/pci/pcie/aer.c
+++ b
> Subject: Re: [PATCH 3/3] PCI/portdrv: Add support for sharing xilinx
> controller irq with AER
>
> On Wed, Aug 01, 2018 at 11:05:09AM -0700, Sinan Kaya wrote:
> > On 8/1/2018 9:44 AM, Bharat Kumar Gogada wrote:
> > > Xilinx ZynqMP PS PCIe does not report AE
irq handler.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/quirks.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f439de8..e666373 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirk
. This irq number is set
using PCI quirk.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/pcie/portdrv_core.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e0261ad..fa9150e 100644
--- a/drivers
Xilinx ZynqMP PS PCIe has dedicated interrupt line for
reporting PCIe errors along with AER.
Save this error irq number in struct device_node private data,
this will be used via PCI qiurks for AER kernel service.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/controller/pcie-xilinx-nwl.c
to save xilinx controller
error irq line. Using PCI quirks this data is passed to sysdata of
root port pci_dev which is retrieved and used for AER handler registration.
Bharat Kumar Gogada (3):
PCI: xilinx-nwl: Save error IRQ number in device_node private data
PCI: Use dedicated Xilinx
Hi Bjorn,
> Subject: Re: [PATCH] PCI/AER: Enable SERR# forwarding in non ACPI flow
>
> On Thu, Jul 12, 2018 at 08:15:19PM +0530, Bharat Kumar Gogada wrote:
> > Currently PCI_BRIDGE_CTL_SERR is being enabled only in ACPI flow.
> > This bit is required for forwarding errors r
> Subject: Re: [PATCH] PCI/AER: Enable SERR# forwarding in non ACPI flow
>
> On 2018-07-18 19:04, Bharat Kumar Gogada wrote:
> >> On 2018-07-13 19:25, Bharat Kumar Gogada wrote:
> >> >> > Currently PCI_BRIDGE_CTL_SERR is being enabled only in ACPI flow
> On 2018-07-13 19:25, Bharat Kumar Gogada wrote:
> >> > Currently PCI_BRIDGE_CTL_SERR is being enabled only in ACPI flow.
> >> > This bit is required for forwarding errors reported by EP devices
> >> > to upstream device.
> >> > This patch enable
> > Currently PCI_BRIDGE_CTL_SERR is being enabled only in ACPI flow.
> > This bit is required for forwarding errors reported by EP devices to
> > upstream device.
> > This patch enables SERR# for Type-1 PCI device.
> >
> > Signed-off-by: Bharat Kumar Gogada
Currently PCI_BRIDGE_CTL_SERR is being enabled only in
ACPI flow.
This bit is required for forwarding errors reported
by EP devices to upstream device.
This patch enables SERR# for Type-1 PCI device.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/pcie/aer.c | 23 +++
1
> > Hi,
> >
> > As per NVME specification:
> > 7.5.1.1 Host Software Interrupt Handling It is recommended that host
> > software utilize the Interrupt Mask Set and Interrupt Mask Clear
> > (INTMS/INTMC) registers to efficiently handle interrupts when configured
> to use pin based or MSI messages.
>
Hi,
As per NVME specification:
7.5.1.1 Host Software Interrupt Handling
It is recommended that host software utilize the Interrupt Mask Set and
Interrupt Mask Clear (INTMS/INTMC)
registers to efficiently handle interrupts when configured to use pin based or
MSI messages.
In kernel 4.14, drive
> I recall we did observe issues like this when legacy interrupts were used, so
> the driver does try to use MSI/MSIx if possible.
>
> The nvme_timeout() is called from the block layer when the driver didn't
> provide a completion within the timeout (default is 30 seconds for IO,
> 60 seconds for
Hi,
Does anyone have any inputs ?
Regards,
Bharat
> Hi,
>
> We are testing NVMe cards on ARM64 platform, the card uses legacy
> interrupts.
> Intermittently we are hitting following case in drivers/nvme/host/pci.c
>/*
> * Did we miss an interrupt?
> */
> if (__
Hi,
We are testing NVMe cards on ARM64 platform, the card uses legacy interrupts.
Intermittently we are hitting following case in drivers/nvme/host/pci.c
/*
* Did we miss an interrupt?
*/
if (__nvme_poll(nvmeq, req->tag)) {
dev_warn(dev->ctrl.device
Hi,
A switch is connected to an RC with 2 EP’s, the RC supports multi MSI.
1st EP requests one MSI vector, 2nd EP requests 4 MSI vectors.
If we are programming hwirq as MSI data (hwirq being obtained from
bitmap_find_next_zero_area, with number of zeroed bits being requested
based on number of i
On Tue, Dec 19, 2017 at 11:28:49AM +, Bharat Kumar Gogada wrote:
> In our case the peripheral returns SLVERR first time and we see the following
> print but kernel do not hang.
> [ 231.484186] Unhandled fault: synchronous external abort
> (0x92000210) at 0x007f9241f8
Hi,
> When Linux is booted on ARM64 platform and an access to peripheral
> returns DECERR or SLVERR on AXI.
>
> In the above error cases how would Linux kernel handle these faults ?
> Will it hang/recover ?
I believe that on contemporary CPUs these will result in an SError. As SErrors
are asy
interrutps after End point handler is executed.
- Legacy interrupts are level triggered, virtual irq line of End
Point shows as edge in /proc/interrupts.
- Setting irq flags of virtual irq line of EP to level triggered
at the time of mapping.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/host/pcie
ailto:marc.zyng...@arm.com]
> > > Sent: Thursday, February 09, 2017 9:33 PM
> > > To: Bharat Kumar Gogada ; bhelg...@google.com;
> > > r...@kernel.org; paul.gortma...@windriver.com;
> > > colin.k...@canonical.com; linux-...@vger.kernel.org
> > > Cc:
Hi,
Any one is working on fix for this issue ?
Regards,
Bharat
> -Original Message-
> From: Bjorn Helgaas [mailto:helg...@kernel.org]
> Sent: Tuesday, September 13, 2016 8:35 PM
> To: Marc Zyngier
> Cc: Bharat Kumar Gogada ; r...@kernel.org;
> bhelg...@g
Waiting for Marc's Reply...
> > -Original Message-
> > From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> > Sent: Thursday, February 09, 2017 9:33 PM
> > To: Bharat Kumar Gogada ; bhelg...@google.com;
> > r...@kernel.org; paul.gortma...@windriver.com;
> On Tue, Jan 31, 2017 at 02:29:30PM +0530, Bharat Kumar Gogada wrote:
> > - Removing support for vendor defined messages which are not
> > suppoerted by AXI
> >
> > Signed-off-by: Bharat Kumar Gogada
>
> Applied to pci/host-xilinx for v4.11, thanks.
>
Thank
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Thursday, February 09, 2017 9:33 PM
> To: Bharat Kumar Gogada ; bhelg...@google.com;
> r...@kernel.org; paul.gortma...@windriver.com; colin.k...@canonical.com;
> linux-...@vger.kernel.org
&
>
> On 09/02/17 12:01, Bharat Kumar Gogada wrote:
> >> On 06/02/17 07:03, Bharat Kumar Gogada wrote:
> >>> +static struct irq_chip nwl_leg_irq_chip = {
> >>> + .name = "nwl_pcie:legacy",
> >>> + .irq_enable = nwl_unmask_leg_irq,
>
> On 06/02/17 07:03, Bharat Kumar Gogada wrote:
> > - Adding spinlock for protecting legacy mask register
> > - Few wifi end points which only support legacy interrupts,
> > performs hardware reset functionalities after disabling interrupts
> > by invoking disable_i
interrutps after End point handler is executed.
- Legacy interrupts are level triggered, virtual irq line of End
Point shows as edge in /proc/interrupts.
- Setting irq flags of virtual irq line of EP to level triggered
at the time of mapping.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/host/pcie
Hi,
Im using linux 4.6 kernel, I get following error when I do interface up.
Here is the boot log.
[4.407681] iwlwifi :01:00.0: loaded firmware version 16.242414.0
op_mode iwlmvm
[4.407742] iwlwifi :01:00.0: Detected Intel(R) Wireless N 7260,
REV=0x144
[4.407831] iwlwifi 000
> On 03/02/17 12:16, Bharat Kumar Gogada wrote:
> >> On 03/02/17 11:08, Bharat Kumar Gogada wrote:
> >>> - Adding mutex lock for protecting legacy mask register
> >>> - Few wifi end points which only support legacy interrupts, performs
> >>>
> On 03/02/17 11:08, Bharat Kumar Gogada wrote:
> > - Adding mutex lock for protecting legacy mask register
> > - Few wifi end points which only support legacy interrupts, performs
> > hardware reset functionalities after disabling interrupts by invoking
> > disable_i
interrutps after End point handler is executed.
- Legacy interrupts are level triggered, virtual irq line of End
Point shows as edge in /proc/interrupts.
- Setting irq flags of virtual irq line of EP to level triggered
at the time of mapping.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/host
> Subject: Re: [PATCH v3] PCI: Xilinx NWL: Modifying irq chip for legacy
> interrupts
>
> On Tue, Jan 31 2017 at 09:34:43 AM, Bharat Kumar Gogada
> wrote:
> > > On Tue, Jan 31 2017 at 08:59:12 AM, Bharat Kumar Gogada
> >> wrote:
> >> > - Adding m
> On Tue, Jan 31 2017 at 08:59:12 AM, Bharat Kumar Gogada
> wrote:
> > - Adding mutex lock for protecting legacy mask register
> > - Few wifi end points which only support legacy interrupts, performs
> > hardware reset functionalities after disabling interrupts by invo
interrutps after End point handler is executed.
- Legacy interrupts are level triggered, virtual irq line of End
Point shows as edge in /proc/interrupts.
- Setting irq flags of virtual irq line of EP to level triggered
at the time of mapping.
Signed-off-by: Bharat Kumar Gogada
---
drivers/pci/host
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