Hi,
On Sat, Jul 06, 2013 at 05:09:33, Stephen Boyd wrote:
> In a uniprocessor implementation the interrupt processor targets
> registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> gic_get_cpumask() will print a critical message saying
>
> GIC CPU mask not found - kernel will fail t
(removing Anil's email-id since it's no longer valid)
On Sat, Apr 20, 2013 at 05:54:10, Kondratiuk, Taras wrote:
> On 04/19/2013 07:21 PM, Nishanth Menon wrote:
> > On 14:55-20130419, Taras Kondratiuk wrote:
> >> Using a "voltage tolerance" for doing DVFS is not a proper way.
> >> It leads to a fe
Hi Kevin,
On Thu, Apr 11, 2013 at 19:45:33, Kevin Hilman wrote:
> Kevin Hilman writes:
>
> > "Bedia, Vaibhav" writes:
> >
> >> Hi Sourav,
> >>
> >> On Wed, Apr 10, 2013 at 15:13:44, Poddar, Sourav wrote:
> >> [...]
> &
Hi Sourav,
On Wed, Apr 10, 2013 at 15:13:44, Poddar, Sourav wrote:
[...]
> Yes, had a look at that and found your situation similar to UART.
>
> But how exactly this gets used, I mean I don't see any drivers/ in mainline
> making use of this compatible string "ti,am3352-ocmcram". ?
OCMC clock
Hi Sourav, Kevin,
On Wed, Apr 10, 2013 at 11:37:28, Poddar, Sourav wrote:
> Hi,
> On Wednesday 10 April 2013 12:37 AM, Kevin Hilman wrote:
> > Sourav Poddar writes:
> >
> >> Hi Kevin,
> >> On Friday 05 April 2013 11:10 PM, Kevin Hilman wrote:
> >>> Sourav Poddar writes:
> >>>
> With dt boo
On Thu, Mar 07, 2013 at 18:43:27, Andreas Fenkart wrote:
> This fixes JTAG support on am33xx.
>
Please refer to http://www.spinics.net/lists/linux-omap/msg87476.html
Regards,
Vaibhav
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Hi Antoniou,
On Wed, Jan 30, 2013 at 19:07:19, Pantelis Antoniou wrote:
> Hi Vaibhav,
>
> On Jan 30, 2013, at 3:29 PM, Bedia, Vaibhav wrote:
>
> > On Wed, Jan 30, 2013 at 18:14:30, Pantelis Antoniou wrote:
> >> Hi Vaibhav,
> >>
> >> On J
On Wed, Jan 30, 2013 at 18:14:30, Pantelis Antoniou wrote:
> Hi Vaibhav,
>
> On Jan 30, 2013, at 2:38 PM, Bedia, Vaibhav wrote:
>
> > On Wed, Jan 30, 2013 at 16:38:50, Pantelis Antoniou wrote:
> > [...]
> >>
> >> TBH I haven't found a simp
On Wed, Jan 30, 2013 at 16:38:50, Pantelis Antoniou wrote:
[...]
>
> TBH I haven't found a simple way to print out the silicon revision number.
> Anyone on the list know a quick and dirty method?
>
You can dump the DEVICE_ID register @ 0x44e10600.
Bits 31:28 should be 0 for PG1.0 and 1 for PG2.
On Wed, Jan 09, 2013 at 17:59:39, Loic PALLARDY wrote:
> Hi Vaibhav,
>
> On 01/09/2013 01:11 PM, Bedia, Vaibhav wrote:
> > Hi Loic,
> >
> > On Fri, Dec 21, 2012 at 16:23:24, Loic PALLARDY wrote:
> >>
> >>
> >> On 12/21/2012 11:49 AM, Bedia,
Hi Loic,
On Fri, Dec 21, 2012 at 16:23:24, Loic PALLARDY wrote:
>
>
> On 12/21/2012 11:49 AM, Bedia, Vaibhav wrote:
> > On Fri, Dec 21, 2012 at 14:24:26, Loic PALLARDY wrote:
> >>
> > I have a few patches which are dependent on this patch series.
> > Co
On Fri, Dec 21, 2012 at 14:24:26, Loic PALLARDY wrote:
>
>
> On 12/18/2012 05:59 PM, Tony Lindgren wrote:
> > * Loic Pallardy [121218 05:15]:
> >>
> >> Signed-off-by: Omar Ramirez Luna
> >
> > AFAIK the first two patches should have:
> > From: Omar Ramirez Luna
> Yes right, my mistake.
> I'll fi
On Tue, Dec 18, 2012 at 18:40:07, Loic Pallardy wrote:
> Current message type is a u32 to fit HW fifo format.
> This should be extended to support any message exchanges
> and type of mailbox.
> Propose structure owns the original u32 and an optional
> pointer on additional data.
>
> Signed-off-by:
On Tue, Dec 18, 2012 at 18:40:08, Loic Pallardy wrote:
> TX: replace spin by mutex
> RX: replace spin_lock_irq by spin_lock_irqsave
>
Can you please add a short note on why this is being done?
Regards,
Vaibhav
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the bo
On Thu, Dec 20, 2012 at 11:55:24, Stephen Boyd wrote:
> On 12/19/2012 8:48 PM, Bedia, Vaibhav wrote:
> > I tried out 3 variants of AM335x boards - 2 of these (BeagleBone and EVM)
> > have DDR2
> > and 1 has DDR3 (EVM-SK). The BUG is triggered on all of these at the same
&g
On Thu, Dec 20, 2012 at 01:53:42, Stephen Boyd wrote:
> On 12/19/12 08:53, Paul Walmsley wrote:
> > On Wed, 19 Dec 2012, Bedia, Vaibhav wrote:
> >
> >> Current mainline on Beaglebone using the omap2plus_defconfig + 3 build
> >> fixes
> >> is trigger
On Wed, Dec 19, 2012 at 07:52:47, Fengguang Wu wrote:
> [add more CC]
>
> On Wed, Dec 19, 2012 at 10:11:02AM +0800, Fengguang Wu wrote:
> > Hi Linus, Wolfram,
> >
> > FYI, kernel build failed on
> >
> > tree: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux master
> > head: 75245
Hi Benoit,
On Mon, Nov 26, 2012 at 14:32:59, Cousson, Benoit wrote:
> Hi Vaibhav,
>
> On 11/26/2012 06:19 AM, Bedia, Vaibhav wrote:
> > On Fri, Nov 23, 2012 at 16:36:06, Philip, Avinash wrote:
> >> On Tue, Nov 20, 2012 at 10:33:44, Philip, Avinash wrote:
> &
On Fri, Nov 23, 2012 at 16:36:06, Philip, Avinash wrote:
> On Tue, Nov 20, 2012 at 10:33:44, Philip, Avinash wrote:
> > As part of PWM subsystem integration, PWM subsystem are sharing
> > resources like clock across submodules (ECAP, EQEP & EHRPWM).
> > To handle resource sharing & IP integration
>
On Mon, Nov 05, 2012 at 14:42:24, Philip, Avinash wrote:
[...]
> +
> +static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
> + .master = &am33xx_epwmss0_hwmod,
> + .slave = &am33xx_ecap0_hwmod,
> + .clk= "l4ls_gclk",
> + .addr = am33xx_ec
On Mon, Nov 05, 2012 at 14:42:29, Philip, Avinash wrote:
[...]
> + am33xx_pinmux: pinmux@44e10800 {
> + ecap0_pins: backlight_pins {
> + pinctrl-single,pins = <
> + 0x164 0x0 /*
> eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>
On Mon, Nov 05, 2012 at 14:42:26, Philip, Avinash wrote:
[...]
> +#include
> +#include
Pinctrl changes should be separate patch. Morevoer, you don't mention
that you making this change.
> +
> +#include "tipwmss.h"
>
> /* EHRPWM registers and bits definitions */
>
> @@ -107,6 +111,10 @@
>
On Mon, Nov 05, 2012 at 14:42:27, Philip, Avinash wrote:
[...]
> + /* Some platforms require explicit tbclk gating */
> + if (of_property_read_bool(pdev->dev.of_node, "tbclkgating")) {
> + pc->tbclk = clk_get(&pdev->dev, "tbclk");
> + if (IS_ERR(pc->tbclk)) {
> +
On Mon, Nov 05, 2012 at 14:42:22, Philip, Avinash wrote:
[...]
> +pwmss0: pwmss@4830 {
> + compatible = "ti,am33xx-pwmss";
> + reg = <0x4830 0x10
> + 0x48300100 0x80
> + 0x48300180 0x80
> + 0x48300200 0x80>;
Do you really need the 4 address ranges
On Fri, Oct 19, 2012 at 22:16:15, Porter, Matt wrote:
> On Fri, Oct 19, 2012 at 12:02:42PM +0000, Bedia, Vaibhav wrote:
> > On Fri, Oct 19, 2012 at 16:45:58, Porter, Matt wrote:
> > > On Fri, Oct 19, 2012 at 10:26:20AM +0000, Bedia, Vaibhav wrote:
> > [...]
> > >
On Fri, Oct 19, 2012 at 16:45:58, Porter, Matt wrote:
> On Fri, Oct 19, 2012 at 10:26:20AM +0000, Bedia, Vaibhav wrote:
[...]
> >
> > I didn't see all the patches that you posted on edma-dmaengine-v3
> > but I do seem them on edma-dmaengine-am33xx-v3 branch.
>
&
Hi Matt,
On Thu, Oct 18, 2012 at 18:56:39, Porter, Matt wrote:
> Changes since v2:
> - Rebased on 3.7-rc1
> - Fixed bug in DT/pdata parsing first found by Gururaja
> that turned out to be masked by some toolchains
> - Dropped unused mach-omap2/devices.c hsmmc patch
>
On Sat, Jul 28, 2012 at 03:53:05, Linus Walleij wrote:
> On Tue, Jul 24, 2012 at 11:16 AM, Bedia, Vaibhav wrote:
>
> >> > A connecting theme is that of being avle to flag clock sources as
> >> > sched_clock providers. If all clocksources were tagged with
> >&g
On Tue, Jul 24, 2012 at 05:58:32, Colin Cross wrote:
> On Mon, Jul 23, 2012 at 5:14 PM, Linus Walleij
> wrote:
> > On Mon, Jul 23, 2012 at 9:27 PM, Colin Cross wrote:
> >> On Mon, Jul 23, 2012 at 11:55 AM, Linus Walleij
> >
> >> Does the clock you use for sched_clock continue to run in all suspe
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