On Friday 27 April 2018 03:11 AM, Laurent Pinchart wrote:
Hi Peter,
Thank you for the patch.
On Friday, 27 April 2018 00:36:44 EEST Peter Rosin wrote:
Could perhaps prevent some confusion.
queued to drm-misc-next
Thanks,
Archit
Signed-off-by: Peter Rosin
Reviewed-by: Laurent Pinchar
On Friday 27 April 2018 03:46 AM, Laurent Pinchart wrote:
Hi Jia-Ju,
Thank you for the patch.
On Wednesday, 11 April 2018 11:33:42 EEST Jia-Ju Bai wrote:
adv7511_probe() is never called in atomic context.
This function is only set as ".probe" in struct i2c_driver.
Despite never getting call
On Tuesday 13 February 2018 11:18 PM, Kieran Bingham wrote:
From: Kieran Bingham
The ADV7511 has four 256-byte maps that can be accessed via the main I2C
ports. Each map has it own I2C address and acts as a standard slave
device on the I2C bus.
Extend the device tree node bindings to be able
On Tuesday 13 February 2018 11:18 PM, Kieran Bingham wrote:
From: Kieran Bingham
The ADV7511 has four 256-byte maps that can be accessed via the main I2C
ports. Each map has it own I2C address and acts as a standard slave
device on the I2C bus.
Allow a device tree node to override the defaul
dges.
Reviewed-by: Archit Taneja
Signed-off-by: Philippe Cornu
Signed-off-by: Laurent Pinchart
---
This patch follows discussions in:
- "drm: clarify adjusted_mode for a bridge connected to a crtc"
https://patchwork.freedesktop.org/patch/206801/
- "drm: bridge: Constify mode
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).
Reviewed-by: Archit Taneja
Changes in v2:
- None
Signed-o
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Don't leave the event != NULL once it's consumed, this is used a signal
s/used a/used as a ?
to the atomic helpers that the event will be handled by the driver.
Reviewed-by: Archit Taneja
Changes in v2:
- None
Cc: Jeykuma
On Thursday 29 March 2018 12:36 AM, Sean Paul wrote:
Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.
Reviewed-by: Archit Taneja
Changes in v2:
- None
Cc: Jeykumar Sankaran
Signed-off-by
- None
Cc: Jeykumar Sankaran
Cc: Archit Taneja
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 77 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 11 +--
drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c | 12 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe
Signed-off-by: Stefan Agner
Reviewed-by: Archit Taneja
Archit
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0f7324a686ca..d729b2b4b66d 1006
ler or the eDP panel. I don't have any strong opinion
about it, though.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Alexandru M Stan
---
Documentation/devicetree/bindings/display/bridge/analogix_dp.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documenta
could adjust
the comment, but it seems more likely that we want the same retry
behavior across all platforms.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: 征增 王
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by:
bug.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: 征增 王
Signed-off-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu/drm/bridge/analogix/analogi
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
It's too early to detect fast link training, if other step after it
failed, we will set fast_link flag to 1, and retry set_bridge again. In
this case we will power down and power up panel power supply, and we
wi
was finding AUX channel errors and eventually
reported "Failed to apply PSR", where I had a kgdb breakpoint. Presumably
the device would have eventually given up and shut down anyway, but it
seems better to fix the order to be more correct.
Reviewed-by: Archit Taneja
Thanks,
Archit
C
edp phy,
BIT 7 reserved
BIT 6 RK_VID_CAP_FUNC_EN_N
BIT 5 RK_VID_FIFO_FUNC_EN_N
So, we should do some private operations to Rockchip.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Reviewed-by: Archit Taneja
streamclk is ok if we wait enough time,
it does no effect on display.
Let's change this error to warn.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signe
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
If we failed disable psr, it would hang the display until next psr
cycle coming. So we should restore psr->state when it failed.
For the bridge part,
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tom
EMOTEIO;
A couple of ETIMEDOUTs have been replaced with EREMOTEIOs after this
change. Maybe we set it the error no in ret and return ret?
With those changes,
Reviewed-by: Archit Taneja
Thanks,
Archit
}
ht? AUX_PD
sounds like just one of the fields of the register.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i Serra
Tested
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We need to check the dpcd write/read return value to see whether the
write/read was successful
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Kristian H. Kristensen
Signed-off-by: Lin Huang
Signed-off
, we just
enable it at the beginning of link training and then keep it on all the
time.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Tomasz Figa
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Reviewed-by: Andrzej Hajda
Signed-off-by: Enric Balletbo i
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
There was a 1ms delay to detect the hpd signal, which is too short to
detect a short pulse. This patch extends this delay to 100ms.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: 征
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
When panel is shut down, we should make sure edp can be disabled to avoid
undefined behavior.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by:
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker
must first detect that the HPD signal is asserted high by the Downstream
Device before establishing a link with it.
Reviewed-by: Archit
On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote:
From: zain wang
When we enable bridge failed, we have to retry it, otherwise we would get
the abnormal display.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by
27;s reset fast_train_enable in
analogix_dp_bridge_disable();
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu/
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We should check AUX_EN bit to confirm the AUX CH operation is completed.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: zain wang
Signed-off
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Lin Huang
We need to enable video before analogix_dp_is_video_stream_on(), so
we can get the right video stream status.
Cc: 征增 王
Cc: Stéphane Marchesin
Signed-off-by: Lin Huang
Signed-off-by: Sean Paul
Signed-off-by:
exiting.
With the subject fix:
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Stéphane Marchesin
Cc: Sonny Rao
Signed-off-by: zain wang
Signed-off-by: Sean Paul
Signed-off-by: Thierry Escande
Signed-off-by: Enric Balletbo i Serra
Tested-by: Marek Szyprowski
---
drivers/gpu
this patch,
you can let it stay if it happens to cause conflicts with future
patches. Other than that:
Reviewed-by: Archit Taneja
Thanks,
Archit
#include
#include
@@ -35,6 +36,8 @@
#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
+static const
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: zain wang
There is a race between AUX CH bring-up and enabling bridge which will
cause link training to fail. To avoid hitting it, don't change psr state
while enabling the bridge.
Reviewed-by: Archit Taneja
On Saturday 10 March 2018 03:52 AM, Enric Balletbo i Serra wrote:
From: Yakir Yang
Make sure the request PSR state takes effect in analogix_dp_send_psr_spd()
function, or print the sink PSR error state if we failed to apply the
requested PSR setting.
Reviewed-by: Archit Taneja
Cc: 征增 王
Hi,
On Friday 09 March 2018 07:21 PM, Jacopo Mondi wrote:
Hello,
after some discussion on the proposed bindings for generic lvds decoder and
Thine THC63LVD1024, I decided to drop the THC63 specific part and just live with
a transparent decoder that does not support any configuration from DT.
Hi,
On Tuesday 06 March 2018 03:23 PM, Neil Armstrong wrote:
Hi Architt,
On 23/02/2018 12:44, Neil Armstrong wrote:
The Amlogic Meson GX SoCs, embedded the v2.01a controller, has been also
identified needing this workaround.
This patch adds the corresponding version to enable a single iteratio
structure when needed.
Idea was taken from the following commit:
8242ecbd597d ("drm/bridge/synopsys: stop clobbering drvdata")
Reviewed-by: Archit Taneja
Cc: p.za...@pengutronix.de
Cc: narmstr...@baylibre.com
Cc: laurent.pinch...@ideasonboard.com
Cc: h...@rock-chips.com
Cc: he..
reused.
Functions exported here are actually not specific to Synopsys PHYs but
to DWC HDMI controller PHY interface. This means that even if the PHY is
completely custom, i.e. not designed by Synopsys, exported functions can
be useful.
Reviewed-by: Archit Taneja
Reviewed-by: Neil Armstrong
On Thursday 15 February 2018 01:38 AM, Jernej Skrabec wrote:
Allwinner SoCs have dw hdmi controller v1.32a which exhibits same
magenta line issue as i.MX6Q and i.MX6DL. Enable workaround for it.
Tests show that one iteration is enough.
Acked-by: Laurent Pinchart
Reviewed-by: Archit Taneja
On 01/26/2018 06:14 AM, Brian Norris wrote:
On Thu, Jan 25, 2018 at 11:37:59AM +0100, Philippe Cornu wrote:
The dcs/generic dsi read feature is not yet implemented so it
is important to warn the host_transfer() caller in case of
read operation requests.
Signed-off-by: Philippe Cornu
Awesom
On 01/26/2018 06:16 AM, Brian Norris wrote:
On Thu, Jan 25, 2018 at 11:38:00AM +0100, Philippe Cornu wrote:
The dw_mipi_dsi_host_transfer() must return the number of
bytes transmitted/received on success instead of 0.
Note: As the read feature is not implemented, only the
transmitted number of
On 01/26/2018 03:24 PM, Philippe CORNU wrote:
Hi Brian,
And a big thanks for your Tested-by
On 01/25/2018 11:47 PM, Brian Norris wrote:
On Thu, Jan 25, 2018 at 7:55 AM, Philippe Cornu wrote:
The "adjusted_mode" clock value (ie the real pixel clock) is more
accurate than "mode" clock value (
Hi,
On 01/22/2018 06:20 PM, Kieran Bingham wrote:
The ADV7511 has four 256-byte maps that can be accessed via the main I²C
ports. Each map has it own I²C address and acts as a standard slave
device on the I²C bus.
Allow a device tree node to override the default addresses so that
address confli
On 01/10/2018 02:02 AM, Brian Norris wrote:
This takes care of 2 TODOs in this driver, by using the common DSI
packet-marshalling code instead of our custom short/long write code.
This both saves us some duplicated code and gets us free support for
command types that weren't already part of our
On 01/10/2018 08:03 PM, Andrzej Hajda wrote:
On 09.01.2018 21:32, Brian Norris wrote:
We're filling the "remainder" word with little-endian data, then writing
it out to IO registers with endian-correcting writel(). That probably
won't work on big-endian systems.
Let's mark the "remainder" var
On 01/09/2018 08:18 PM, Thierry Escande wrote:
From: Jeffy Chen
Add missing pm_runtime_disable() in bind()'s error handling path.
Also cleanup encoder & connector in unbind().
I guess you'll need to drop this commit if this patch goes in first:
https://patchwork.kernel.org/patch/10106105/
On 12/12/2017 06:40 AM, Nickey Yang wrote:
Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.
Reviewed-by: Archit Taneja
Signed-off-by: Nickey Yang
Signed-off-by: Brian Norris
Reviewed-by: Brian Norris
Reviewed-by: Sean Paul
On 01/09/2018 08:18 PM, Thierry Escande wrote:
Hi,
This patchset makes edp display work on Chromebook kevin.
This patchset has been originally posted by Jeffy Chen and the 2 first
commits from the previous version (v6) are already merged in mainline.
This v7 has been rebased on top of next-20
On 01/09/2018 08:18 PM, Thierry Escande wrote:
From: Jeffy Chen
Let plat drivers own the drvdata, so that they could cleanup resources
in their unbind().
Signed-off-by: Jeffy Chen
Signed-off-by: Thierry Escande
Reviewed-by: Neil Armstrong
Reviewed-by: Archit Taneja
---
drivers/gpu
On 01/09/2018 08:18 PM, Thierry Escande wrote:
From: Jeffy Chen
We inited connector in attach(), so need a detach() to cleanup.
Also fix wrong use of dw_hdmi_remove() in bind().
Signed-off-by: Jeffy Chen
Signed-off-by: Thierry Escande
Reviewed-by: Archit Taneja
---
drivers/gpu/drm
On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
Parts of PHY code could be useful also for custom PHYs. For example,
Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
with few additional memory mapped registers, so most of the Synopsys PHY
related code could be reused.
It turns o
On 12/05/2017 06:49 AM, Brian Norris wrote:
Hi Archit,
I'm a relative n00b here, but I'm trying to follow along and I have some
questions:
On Fri, Dec 01, 2017 at 06:29:04PM +0530, Archit Taneja wrote:
On 11/30/2017 11:02 PM, Nickey Yang wrote:
I try to follow as you sug
On 11/30/2017 11:02 PM, Nickey Yang wrote:
Hi Archit,
On 2017年10月26日 12:53, Archit Taneja wrote:
On 10/25/2017 09:21 AM, Nickey Yang wrote:
Configure dsi slave channel when driving a panel
which needs 2 DSI links.
Signed-off-by: Nickey Yang
---
.../devicetree/bindings/display/rockchip
ported-by: Naresh Kamboju
Cc: Xinliang Liu
Cc: Dan Carpenter
Cc: Sean Paul
Cc: Archit Taneja
Cc: John Stultz
Link: https://bugs.linaro.org/show_bug.cgi?id=3345
Link: https://lkft.validation.linaro.org/scheduler/job/48017#L3551
Fixes: 7af35b0addbc ("drm/kirin: Checking for IS_ERR() instead
On 11/15/2017 03:29 PM, Lothar Waßmann wrote:
Hi,
On Tue, 14 Nov 2017 11:16:47 -0800 Eric Anholt wrote:
The panel_bridge bridge attaches to the panel's OF node, not the
lvds-encoder's node. Put in a little no-op bridge of our own so that
our consumers can still find a bridge where they expec
On 11/29/2017 03:02 AM, John Stultz wrote:
On Sun, Nov 26, 2017 at 4:56 AM, Archit Taneja wrote:
On 11/17/2017 04:29 AM, John Stultz wrote:
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 0e14f15..939c3b9 100644
--- a/drivers
On 11/28/2017 06:35 AM, Brian Norris wrote:
Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.
Reviewed-by: Archit Tan
Hi,
Thanks a lot for working on this. Some comments below.
On 11/28/2017 07:25 AM, Nickey Yang wrote:
Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.
Signed-off-by: Nickey Yang
---
drivers/gpu/drm/rockchip/Kconfig|
g
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link:
http://patchwork.freedesktop.org/patch/msgid/20170305233557.11945-1-laurent.pinchart+rene...@ideasonboard.com
:04 04 0defad9d1a61c0355f49c679b18eebae2c4b9495
5d260e6db25d6abc1211d61ec3405be99e693a23 M drive
ng Liu
Cc: Dan Carpenter
Cc: Sean Paul
Cc: Hans Verkuil
Cc: Archit Taneja
Link: https://bugs.linaro.org/show_bug.cgi?id=3345
Link: https://lkft.validation.linaro.org/scheduler/job/48017#L3551
Fixes: 7af35b0addbc ("drm/kirin: Checking for IS_ERR() instead of NULL")
Fixes: 3b1b975003e4 (&q
On 11/26/2017 01:48 AM, Pierre-Hugues Husson wrote:
Support the "cec" optional clock. The documentation already mentions "cec"
optional clock and it is used by several boards, but currently the driver
doesn't enable it, thus preventing cec from working on those boards.
And even worse: a /dev/c
Hi,
On 11/20/2017 06:00 PM, Hans Verkuil wrote:
I didn't see this merged for 4.15, is it too late to include this?
All other changes needed to get CEC to work on rk3288 and rk3399 are all merged.
Sorry for the late reply. I was out last week.
Dave recently sent the second pull request for 4.1
On 11/08/2017 09:15 AM, Bjorn Andersson wrote:
Add a missing #phy-cells to the dsi-phy, to silence dtc warning.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Archit Taneja
Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support")
Signed-off-by: Bjorn Andersson
---
ridge: Link encoder and bridge in core code
This was merged only in 4.11.
Thanks,
Archit
--
From: Archit Taneja
[ Upstream commit 0bb70b82c2f91e4667f3c617505235efd6d77e46 ]
The commit "drm: bridge: Link encoder and bridge in core code" updated
the drm_bridge_attac
On 10/25/2017 01:34 PM, Sean Paul wrote:
On Wed, Oct 25, 2017 at 11:51:01AM +0800, Nickey Yang wrote:
This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.
Signed-off-by:
On 10/25/2017 09:21 AM, Nickey Yang wrote:
Configure dsi slave channel when driving a panel
which needs 2 DSI links.
Signed-off-by: Nickey Yang
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/d
Hi,
On 10/26/2017 06:39 AM, Brian Norris wrote:
On Wed, Oct 25, 2017 at 03:57:19AM -0400, Sean Paul wrote:
Archit asked a question about moving to
dw-mipi-dsi
That question made me think though: this approach seems backwards. It
seems like someone did copy/paste/fork, and then we're asking th
crtc(crtc);
struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
- uint32_t lm = mdp5_cstate->pipeline.mixer->lm;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w;
uint32_t roi_h;
I guess we could get rid of roi_w, r
On 10/20/2017 05:47 PM, Rob Clark wrote:
It's only likely to paper over bugs. Unlike the gpu, where we want to
keep things alive a bit longer in expectation of the next frame's
submit, when the display is shut down we can power off immediately.
Acked-by: Archit Taneja
Signed-o
Acked-by: Archit Taneja
Acked-by: Jingoo Han
Best regards,
Jingoo Han
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 50 +
-
drivers/gpu/drm/exynos/exynos_dp.c | 26 ++-
dr
Hi,
Comment below.
On 09/26/2017 01:25 PM, Nickey Yang wrote:
This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.
@@ -1226,6 +1367,13 @@ static int rockchip_mipi_pa
Hi,
On 09/26/2017 01:25 PM, Nickey Yang wrote:
This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divid
dge" flag
from stm driver internal structure.
version 2:
- does the same for vc4 and dw-mipi-dsi
For the series:
Reviewed-by: Archit Taneja
Feel free to queue to drm-misc-next.
Thanks,
Archit
Benjamin Gaignard (5):
drm/bridge: make drm_panel_bridge_remove more robust
drm/drm_of:
vc4 will create the host early on.
Reviewed-by: Archit Taneja
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/panel/Kconfig | 8 +
drivers/gpu/drm/panel/Makefile | 1 +
.../gpu/drm/panel/panel-raspberrypi-touchscreen.c | 517 +
Hi Benjamin,
This should be pushed to drm-misc by you, right?
Thanks,
Archit
On 09/06/2017 06:43 PM, Arnd Bergmann wrote:
gcc-7 complains about multiplying within a condition being
suspicious:
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c: In function 'dsi_pll_get_clkout_khz':
drivers/gpu/drm/stm/dw_
On 09/01/2017 07:15 PM, Andrzej Hajda wrote:
On 01.08.2017 15:23, Philippe CORNU wrote:
Based on patch "Convert drivers to explicit reset API" from Philipp Zabel
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control requ
On 09/01/2017 06:59 PM, Andrzej Hajda wrote:
On 01.08.2017 15:23, Philippe CORNU wrote:
This patch cleans up the Synopsys mipi dsi register list:
- rename registers according to the Synopsys documentation
(1.30 & 1.31)
- fix typos
- re-order registers for a better coherency
Signed-off-by:
dge lookup/attach into the component bind process.
Reviewed-by: Archit Taneja
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_dsi.c | 97 +--
1 file changed, 57 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/g
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ4019 QPIC NAND controller
version 1.4.0 which uses BAM DMA.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 10 ++
1 file changed, 10
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ8074 QPIC NAND controller
version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers
starting offset is 0x7000.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 108 +++---
1 file changed, 92 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index d17c466
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 19
in the registers
defined above, it might get confusing for someone who doesn't have access
to the HW docs. Could you explicitly mention in this comment all the register
names that are required to go through this translation, it should make things
more readable. With that:
Reviewed-by: Archit T
descriptor formation function.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
e required later if we want the controller to support multiple NAND chips?
If not,
then we could consider dropping this. Anyway, that can be posted as a separate
patch
later.
Reviewed-by: Archit Taneja
Thanks,
Archit
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
write_reg_dma(nandc, NAND_
codeword/page detection controller. This register should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 21 +
1 file
nandc_set_readl(nandc, 0, 0, size, 1);
The READ_LOC reg should already be set up in update_rw_regs, right? If so, we
could
drop this line.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
config_nand_single_cw_page_read(nandc);
@@ -1502,6 +1551,7 @@ static int qcom_nandc_r
using
BAM.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
*/
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsigned int flags)
{
bool flow_control = false;
void *
.
- The size of the buffer used for BAM transactions
is calculated based on the NAND device with the maximum page size,
among all the devices connected to the
controller.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 94
time. Before starting of any operation, this buffer will
be synced for device operation and after operation
completion, it will be synced again for CPU.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c
On 08/09/2017 02:08 PM, Laurent Pinchart wrote:
Hi Arvind,
Thank you for the patch.
On Wednesday 09 Aug 2017 13:08:37 Arvind Yadav wrote:
snd_pcm_ops are not supposed to change at runtime. All functions
working with snd_pcm_ops provided by work with
const snd_pcm_ops. So mark the non-const
On 08/08/2017 09:33 PM, Laurent Pinchart wrote:
Hi Bhumika,
Thank you for the patch.
On Tuesday 08 Aug 2017 21:24:10 Bhumika Goyal wrote:
Make these structures const as they are only stored in the funcs field
of drm_bridge structure, which is of type const.
Done using Coccinelle.
Signed-off
On 08/08/2017 04:58 PM, Bhumika Goyal wrote:
Declare drm_connector_funcs structures as const.
Could you rebase this series over the latest drm-misc-next? The
recently merged patch "drm: Nuke drm_atomic_helper_connector_dpms"
causes conflicts with these.
drm-misc-next:
https://cgit.freedeskt
ased on today's drm-misc-next branch.
Signed-off-by: Jose Abreu
Tested-by: Mark Yao
This is needed for RK3399 support. Can you please apply it?
Best regards,
Jose Miguel Abreu
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Mark Yao
Cc: Carlos Palminh
On 08/07/2017 09:39 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp.
This patch updates the year, because this driver was moved
into synopsys folder in 2017.
Thanks. Queued to drm-misc-next.
Archit
Signed-off-by: Kuninori Mor
On 08/07/2017 09:25 AM, Kuninori Morimoto wrote:
Hi Archit
Thank you for your feedback
On 08/07/2017 07:41 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp
Can we update the year to 2017 while we're at it?
The original patc
On 08/07/2017 07:41 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp
Can we update the year to 2017 while we're at it?
Archit
Signed-off-by: Kuninori Morimoto
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 3 ++-
On 08/03/2017 05:20 PM, Arnd Bergmann wrote:
When CONFIG_PM is disabled, we get harmless warnings about unused
functions:
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1025:12: error: 'mdp5_runtime_resume'
defined but not used [-Werror=unused-function]
static int mdp5_runtime_resume(struct device
write) or rx channel
(for read) and all the registers read/write descriptors in
command channel.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 143 ++
1 file changed, 130 insertions(+), 13
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