Hi,
Am Mittwoch, 19. März 2025, 10:46:18 CET schrieb Daniel Baluta:
> Enable MU2 node and add mu2 root clock.
> MU2 is used to communicate with DSP core.
>
> Reviewed-by: Iuliana Prodan
> Reviewed-by: Peng Fan
> Signed-off-by: Daniel Baluta
> ---
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts
Am Montag, 17. März 2025, 14:33:03 CET schrieb Daniel Baluta:
> Enable MU2 node and add mu2 root clock.
> MU2 is used to communicate with DSP core.
>
> Reviewed-by: Iuliana Prodan
> Reviewed-by: Peng Fan
> Signed-off-by: Daniel Baluta
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
>
no-map;
> > + };
> > +
> > + dsp_vdev0buffer: vdev0buffer@9430 {
> > + compatible = "shared-dma-pool";
> > + reg = <0 0x9430 0 0x10>;
> > + no-map;
> > + };
&g
Hi Iuliana,
Am Freitag, 13. Oktober 2023, 10:35:17 CEST schrieb Iuliana Prodan:
> Hi Alexander,
>
> On 10/11/2023 8:37 AM, Alexander Stein wrote:
> > Hi Iuliana,
> >
> > Am Dienstag, 10. Oktober 2023, 11:09:29 CEST schrieb Iuliana Prodan (OSS):
> >> From
Hi Iuliana,
Am Dienstag, 10. Oktober 2023, 11:09:29 CEST schrieb Iuliana Prodan (OSS):
> From: Iuliana Prodan
>
> Add the reserve-memory nodes used by DSP when the rpmsg
> feature is enabled.
>
> Signed-off-by: Iuliana Prodan
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16
Hello,
On Thursday, October 10, 2019, 3:30:58 AM CEST Navid Emamdoost wrote:
> In the implementation of bcm2835_register_pll(), the allocated memory
> for pll should be released if devm_clk_hw_register() fails.
>
> Fixes: b19f009d4510 ("clk: bcm2835: Migrate to clk_hw based registration and
> OF
In case the result is -0.3252 tmp0 is 0 after the div_s64_rem, so tmp0 is
non-negative which results in an output of 0.3252.
Fix this by explicitly handling the negative sign ourselves.
Signed-off-by: Alexander Stein
---
Changes in v2:
* Support vals[0] >= and vals[1] < 0 in IIO_VAL_FRAC
In case the result is -0.3252 tmp0 is 0 after the div_s64_rem, so tmp0 is
non-negative which results in an output of 0.3252.
Fix this by explicitly handling the negative sign ourselves.
Signed-off-by: Alexander Stein
---
drivers/iio/industrialio-core.c | 5 +++--
1 file changed, 3 insertions
On Wednesday, August 7, 2019, 1:44:06 PM CEST Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> The imx I2C controller is used in some ARM64 SoCs such as i.MX8M.
> To make use of it, append ARM64 to the list of dependencies.
>
> Signed-off-by: Frieder Schrempf
> ---
> drivers/i2c/busses/Kco
On Monday, August 5, 2019, 11:14:32 AM CEST Hui Song wrote:
> From: Song Hui
>
> Update the NXP GPIO node dt-binding file for QorIQ and
> Layerscape platforms, and add one more example with
> ls1028a GPIO node.
>
> Signed-off-by: Song Hui
> ---
> Documentation/devicetree/bindings/gpio/gpio-mpc
On Tuesday, October 16, 2018, 3:30:24 PM CEST claudiu.bez...@microchip.com
wrote:
> Hi Jonas,
>
> On 07.10.2018 15:57, Jonas Danielsson wrote:
> > From: Jonas Danielsson
> >
> > This fixes a bug where our embedded system (AT91SAM9260 based) would
> > hang at reboot. At the most we managed 16 bo
Do you have CONFIG_CPU_ICACHE_DISABLE enabled?
I wonder why I-cache is disabled. I know about this errata, AT91SAM9G20 is
affected as well.
Best regards,
Alexander
On Sunday, October 7, 2018, 2:57:45 PM CEST Jonas Danielsson wrote:
> From: Jonas Danielsson
>
> This fixes a bug where our embedd
Hello Arnd,
On Tuesday, September 25, 2018, 2:06:38 PM CEST Arnd Bergmann wrote:
> We don't really want an empty macro any more, this was used in
> the past, but causes compile-time warnings and undefined behavior
> for no good reason.
Can you elaborate or point me to some other discussion about
On Wednesday, September 5, 2018, 11:46:05 AM CEST Colin King wrote:
> From: Colin Ian King
>
> Currently we have structrues comp (which is empty) and comp_info being
> used to register and deregister the component. This mismatch in naming
> occurred from a previous commit that renamed aim_info t
On Monday, July 9, 2018, 4:56:03 PM CEST Arnd Bergmann wrote:
> Gcc cannot always see that BUG_ON(1) is guaranteed to not
> return, so we get a warning message in some configurations:
>
> drivers/gpio/gpio-aspeed.c: In function 'bank_reg':
> drivers/gpio/gpio-aspeed.c:244:1: error: control reaches
On Tuesday, June 12, 2018, 7:27:52 AM CEST Keerthy wrote:
> This is needed in case of PROBE_DEFER if IRQ resource is not yet ready.
>
> Signed-off-by: Keerthy
> ---
> [...]
> --- a/drivers/gpio/gpio-davinci.c
> +++ b/drivers/gpio/gpio-davinci.c
> [...]
> @@ -168,7 +168,7 @@ static int davinci_gpi
On Friday, March 16, 2018, 11:26:47 AM CET Jakob Unterwurzacher wrote:
> On 15.03.18 23:30, John Fastabend wrote:
> >> I have reproduced it using two USB network cards connected to each other.
> >> The test tool sends UDP packets containing a counter and listens on the
> >> other interface, it is
On Monday, December 11, 2017, 3:06:52 PM CET Rasmus Villemoes wrote:
> On 2017-12-11 14:45, Rasmus Villemoes wrote:
> > On 2017-12-11 11:02, Alexander Stein wrote:
> >
> >> Oh, and what is the content of register SCFG_SCFGREVCR?
> >
> > Good point. On my boar
On Monday, December 11, 2017, 10:45:09 AM CET Alexander Stein wrote:
> On Monday, December 11, 2017, 10:08:20 AM CET Rasmus Villemoes wrote:
> > >>> +static int
> > >>> +ls1021a_extirq_set_type(struct irq_data *data, unsigned int type)
> > >>> +{
>
On Monday, December 11, 2017, 10:08:20 AM CET Rasmus Villemoes wrote:
> >>> +static int
> >>> +ls1021a_extirq_set_type(struct irq_data *data, unsigned int type)
> >>> +{
> >>> + irq_hw_number_t hwirq = data->hwirq;
> >>> + struct extirq_chip_data *chip_data = data->chip_data;
> >>> + u32 value, mas
Hi Rasmus,
thanks for your effort. unfortunatly I won't be able to test it currently :(
But some comments below.
On Friday, December 8, 2017, 3:33:00 PM CET Rasmus Villemoes wrote:
> The LS1021A allows inverting the polarity of six interrupt lines
> IRQ[0:5] via the scfg_intpcr register, effectiv
On Monday, December 4, 2017, 4:37:20 PM CET Marc Zyngier wrote:
> On 04/12/17 15:31, Alexander Stein wrote:
> > On Monday, December 4, 2017, 4:11:06 PM CET Rasmus Villemoes wrote:
> >> The LS1021A has a standard GIC-400, but allows inverting the polarity of
> >> six ext
Hi Rasmus,
On Monday, December 4, 2017, 4:11:06 PM CET Rasmus Villemoes wrote:
> The LS1021A has a standard GIC-400, but allows inverting the polarity of
> six external interrupt lines via a certain register, effectively
> supporting IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those.
>
> I'm
Hi,
I tried to compile the new v4.14 kernel and hit a race condition in the build
system of tools/iio.
Here is my output (sorry for German strings, I wasn't able to reproduce with
LANG=C):
> {master linux} % make O=build_x86/ -j9 tools/iio
> make[1]: Verzeichnis „/home/alex/Dokumente/repo/linux/
On Wednesday 16 August 2017 17:15:55, Ken Goldman wrote:
> On 8/15/2017 4:13 PM, Haris Okanovic wrote:
> > ioread8() operations to TPM MMIO addresses can stall the cpu when
> > immediately following a sequence of iowrite*()'s to the same region.
> >
> > For example, cyclitest measures ~400us laten
On Monday 14 August 2017 17:53:47, Haris Okanovic wrote:
> --- a/drivers/char/tpm/tpm_tis.c
> +++ b/drivers/char/tpm/tpm_tis.c
> @@ -52,6 +52,22 @@ static inline struct tpm_tis_tcg_phy
> *to_tpm_tis_tcg_phy(struct tpm_tis_data *da return container_of(data,
> struct tpm_tis_tcg_phy, priv);
> }
>
>
Hi,
On Wednesday 02 August 2017 09:51:24, Bartosz Golaszewski wrote:
> Use resource managed variants of irq_alloc_generic_chip() and
> irq_setup_generic_chip().
Is this really useful for drivers which can only be built-in? This is probably
valid for the other drives as well.
Best regards,
Alexa
On Tuesday 13 June 2017 15:58:45, Dong Aisheng wrote:
> diff --git a/drivers/clocksource/timer-imx-tpm.c
> b/drivers/clocksource/timer-imx-tpm.c new file mode 100644
> index 000..940a4f75
> --- /dev/null
> +++ b/drivers/clocksource/timer-imx-tpm.c
> @@ -0,0 +1,227 @@
> [...]
> +static int tpm_s
On Wednesday, June 7, 2017, 2:37:41 PM CEST Phil Elwell wrote:
> On 07/06/2017 13:07, Alexander Stein wrote:
> > On Wednesday 07 June 2017 12:11:45, Phil Elwell wrote:
> >> Devices in the AUX block share a common interrupt line, with a register
> >> indicating whi
On Wednesday 07 June 2017 12:11:45, Phil Elwell wrote:
> Devices in the AUX block share a common interrupt line, with a register
> indicating which devices have active IRQs. Expose this as a nested
> interrupt controller to avoid IRQ sharing problems (easily observed if
> UART1 and SPI1/2 are enabl
If unset, the gpc drivers fails to link with this error:
drivers/built-in.o: In function `imx_gpc_probe':
core.c:(.text+0x1e16c): undefined reference to
`__devm_regmap_init_mmio_clk'
As the gpc driver is built when ARCH_MXC is set, enable REGMAP_MMIO in
this case too.
Signed-off-by:
On Wednesday 08 February 2017 16:17:45, Mathias Nyman wrote:
> On 08.02.2017 15:44, Alexander Stein wrote:
> > This patch adds support for USB2 test mode (Test_J, Test_K,
> > Test_SE0_NAK and Test_Packet) per XHCI spec 4.19.6.
> >
> > USB2 test mode is a required
;Wang, Yu"
Signed-off-by: "Li, Guanglei"
Signed-off-by: "Wu, Hao"
Signed-off-by: Alexander Stein
---
Changes in v2:
* Added additional info about USB2 test modes itself into commit message
* Add URL for same test mode feature on ehci hosts.
dr
On Wednesday 08 February 2017 13:53:30, Greg Kroah-Hartman wrote:
> On Wed, Feb 08, 2017 at 11:26:35AM +0100, Alexander Stein wrote:
> > This patch adds support for USB2 test mode (Test_J, Test_K,
> > Test_SE0_NAK and Test_Packet) per XHCI spec 4.19.6.
>
> What does that m
This patch adds support for USB2 test mode (Test_J, Test_K,
Test_SE0_NAK and Test_Packet) per XHCI spec 4.19.6.
Signed-off-by: "Wang, Yu"
Signed-off-by: "Li, Guanglei"
Signed-off-by: "Wu, Hao"
Signed-off-by: Alexander Stein
---
This patch was taken
Hi,
On Thursday 22 December 2016 22:48:32, Mark Rutland wrote:
> On Wed, Dec 21, 2016 at 04:03:40PM +0100, Alexander Stein wrote:
> > This driver can only built into the kernel. So disallow driver bind/unbind
> > and also prevent a kernel error in case DEBUG_TEST_DRIVER_REMOVE
This driver can only built into the kernel. So disallow driver bind/unbind
and also prevent a kernel error in case DEBUG_TEST_DRIVER_REMOVE is
enabled.
Signed-off-by: Alexander Stein
---
arch/arm/kernel/perf_event_v7.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/kernel
This eliminates several calls to kfree.
Signed-off-by: Alexander Stein
---
drivers/perf/arm_pmu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index b37b572..a9bbdbf 100644
--- a/drivers/perf/arm_pmu.c
+++ b
from [<806febcc>] (kernel_init+0x10/0x11c)
r10: r9: r8: r7: r6: r5:806febbc
r4:
[<806febbc>] (kernel_init) from [<80208388>] (ret_from_fork+0x14/0x2c)
r5:806febbc r4:
---[ end trace 9d251d389382804f ]---
This patchset marks the dr
On Wednesday 21 December 2016 14:38:54, Peter Zijlstra wrote:
> On Wed, Dec 21, 2016 at 11:19:34AM +0100, Alexander Stein wrote:
> > Add ARM PMU removal function. This will be required by perf event drivers
> > when option DEBUG_TEST_DRIVER_REMOVE is enabled.
> >
> &g
Add ARM PMU removal function. This will be required by perf event drivers
when option DEBUG_TEST_DRIVER_REMOVE is enabled.
Signed-off-by: Alexander Stein
---
drivers/perf/arm_pmu.c | 14 ++
include/linux/perf/arm_pmu.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a
bbc
r4:
[<806febbc>] (kernel_init) from [<80208388>] (ret_from_fork+0x14/0x2c)
r5:806febbc r4:
---[ end trace 9d251d389382804f ]---
This patchset add a removal support for arm_pmu and perf_events_v7 and while
at it, use devm_ allocators in arm_pmu.
Alexander Stein
This eliminates several calls to kfree.
Signed-off-by: Alexander Stein
---
drivers/perf/arm_pmu.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index b37b572..a9bbdbf 100644
--- a/drivers/perf/arm_pmu.c
+++ b
Despite the driver cannot be built as a module using the option
DEBUG_TEST_DRIVER_REMOVE requires the drivers to actually remove the
device.
Signed-off-by: Alexander Stein
---
arch/arm/kernel/perf_event_v7.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/kernel/perf_event_v7
On Monday 14 November 2016 16:12:27, Michael Walle wrote:
> Since commit 87a18a6a5652 ("mmc: mmc: Use ->card_busy() to detect busy
> cards in __mmc_switch()") the ESDHC driver is broken:
> mmc0: Card stuck in programming state! __mmc_switch
> mmc0: error -110 whilst initialising MMC card
>
> S
MBUS_BYTE_DATA |
> I2C_FUNC_SMBUS_WORD_DATA |
> + I2C_FUNC_SMBUS_BLOCK_DATA |
> I2C_FUNC_SMBUS_I2C_BLOCK;
>
> dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
Shouldn't those functionality bits moved to a common place, like i2c
On Monday 24 October 2016 02:53:31, Linus Walleij wrote:
> On Fri, Oct 21, 2016 at 5:00 PM, Enric Balletbo i Serra
>
> wrote:
> > Default is without pullups, but if property is specified in DT and the bit
> > is set, set a pullup on GPIO-n.
> >
> > Signed-off-by: Enric Balletbo i Serra
>
> I d
Hi Alexandre,
On Friday 07 October 2016 18:34:25, Alexandre Belloni wrote:
> Hi,
>
> This patch set improves LPDDR support on SoCs using the Atmel MPDDR
> controller.
>
> LPDDR memoris can only handle up to 400 uncontrolled power offs in their
> life. The proper power off sequence has to be appl
On Thursday 08 September 2016 10:04:55, Meng Yi wrote:
> If the FTM counter reaches the FTM_MOD value between the reading of the
> TOF bit and the writing of 0 to the TOF bit, the process of clearing the
> TOF bit does not work as expected when FTMx_CONF[NUMTOF] != 0 and the
> current TOF count is
On Thursday 18 August 2016 14:38:47, Yuan Yao wrote:
> From: Yuan Yao
>
> Add the QDMA node for ls1043a platform to
> support QDMA driver.
>
> Signed-off-by: Yuan Yao
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/ar
On Thursday 18 August 2016 14:38:47, Yuan Yao wrote:
> From: Yuan Yao
>
> Add the QDMA node for ls1043a platform to
> support QDMA driver.
>
> Signed-off-by: Yuan Yao
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/ar
On Thursday 04 August 2016 15:58:35, York Sun wrote:
> Add DDR EDAC for ARM-based compatible controllers. Both big-endian
> and little-endian are supported.
>
> Signed-off-by: York Sun
>
> ---
> Change log
> v3: no change
> v2: Create new driver using shared DDR object
>
> arch/arm64/Kconf
On Thursday 04 August 2016 15:28:18, Ksenija Stanojevic wrote:
> Add core files for mxs-lradc MFD driver.
>
> Note: this patch won't compile in iio/testing without this patch:
> a8f447be8056 ("mfd: Add resource managed APIs for mfd_add_devices")
>
> Signed-off-by: Ksenija Stanojevic
> ---
> [..
On Tuesday 26 July 2016 11:33:59, Quentin Schulz wrote:
> On 26/07/2016 11:05, Alexander Stein wrote:
> > On Tuesday 26 July 2016 10:24:48, Quentin Schulz wrote:
> >> On 26/07/2016 10:21, Alexander Stein wrote:
> >>> On Tuesday 26 July 2016
On Tuesday 26 July 2016 10:24:48, Quentin Schulz wrote:
> On 26/07/2016 10:21, Alexander Stein wrote:
> > On Tuesday 26 July 2016 09:43:44, Quentin Schulz wrote:
> >> iio_channel_get_all returns -ENODEV when it cannot find either phandles
> >> and
> >> prope
On Tuesday 26 July 2016 09:43:44, Quentin Schulz wrote:
> iio_channel_get_all returns -ENODEV when it cannot find either phandles and
> properties in the Device Tree or channels whose consumer_dev_name matches
> iio_hwmon in iio_map_list. The iio_map_list is filled in by iio drivers
> which might b
On Wednesday 29 June 2016 09:57:14, Alexandre Belloni wrote:
> On 29/06/2016 at 08:12:21 +0200, Alexander Stein wrote :
> > > +#if defined(CONFIG_CPU_V7)
> > > + dsb();
> > > + wfi();
> > > +#else
> > > + asm volatile ("mcr p15, 0, %0, c7,
On Wednesday 29 June 2016 00:44:46, Alexandre Belloni wrote:
> Using the PIE infrastructure allows to write the whole suspend/resume
> functions in C instead of assembly.
>
> The only remaining assembly instruction is wfi for armv5
> It makes the code shorter and clearer.
>
> Signed-off-by: Alexa
On Tuesday 28 June 2016, 10:37:52 wrote Arnd Bergmann:
> > > I think the commit should just be reverted, it clearly breaks
> > > stuff, and whatever needs it can be fixed in a better way.
> >
> > Why not depend PINCTRL_IPROC_GPIO on CONFIG_OF as Randy stated
> > pinconf_generic_dt_node_to_map_pin
d ...
> > but OF_GPIO is enabled due to this in drivers/gpio/Kconfig:
> >
> > config OF_GPIO
> >
> > def_bool y
> > depends on OF || COMPILE_TEST
> >
> > (above from commit 1e4a80640338924b9f9fd7a121ac31d08134410a
> > f
On Thursday 26 May 2016 08:23:42, Meng Yi wrote:
> Hi Mark,
>
> > You've not specifically described the problem here - what are the
> > endiannesses of both the CPU and the device you're talking to? What
> > specifically is the endianess problem you are seeing, what are you seeing
> > and what do
On Thursday 26 May 2016 08:18:30, Meng Yi wrote:
> Hi Alexander,
>
> > From your backtrace I guess wait_event_timeout is called in some atomic
> > context (might_sleep(); is called inside wait_event_timeout). This has
> > nothing to do with regmap.
>
> Here is my view of point:
> Since IRQ setup
On Wednesday 25 May 2016 10:25:29, Meng Yi wrote:
> Hi Alexander,
> Thanks for your reply.
>
> > Commit d761701c55a99598477f3cb25c03d939a7711e74 only has one child
> > commit in my repo. Both touch only i915 related things. Please do a proper
> > bisect and name the offending commit. On which comm
Hi,
On Wednesday 25 May 2016 08:58:31, Meng Yi wrote:
> > On Tuesday 24 May 2016 23:20:02, Stefan Agner wrote:
> > > On 2016-05-24 19:14, Meng Yi wrote:
> > > > I found that its regmap endianness issue, so I want to replace the
> > > > "regmap".
> > >
> > > Hm, replace with what? Note that we nee
On Tuesday 24 May 2016 23:20:02, Stefan Agner wrote:
> On 2016-05-24 19:14, Meng Yi wrote:
> > I found that its regmap endianness issue, so I want to replace the
> > "regmap".
> Hm, replace with what? Note that we need some kind of endianness
> convertion since the IP is big endian on LS1021a and l
Hi Hauke,
On Monday 23 May 2016 09:12:54, Mehrtens, Hauke wrote:
> > On Thursday 19 May 2016 12:03:10, Mathias Kresin wrote:
> > > 2016-05-19 9:03 GMT+02:00 John Crispin :
> > > > On 19/05/2016 08:57, Alexander Stein wrote:
> > > >> Thanks for the link,
On Thursday 19 May 2016 12:03:10, Mathias Kresin wrote:
> 2016-05-19 9:03 GMT+02:00 John Crispin :
> > On 19/05/2016 08:57, Alexander Stein wrote:
> >> Thanks for the link, I wasn't aware of that patch. I like it in general,
> >> but there are some things
On Thursday 19 May 2016 09:03:26, John Crispin wrote:
> [ changing haukes mail addr to the intel one ]
>
> On 19/05/2016 08:57, Alexander Stein wrote:
> > Hi John,
> >
> > On Thursday 19 May 2016 06:50:56, John Crispin wrote:
> >> On 18/05/2016 18:24, Florian
On Wednesday 18 May 2016 19:01:09, Andrew Lunn wrote:
> > For LEDs, we had a patch series floating around adding LED triggers [1],
> > and it seems to me like the LEDs class subsystem would be a good fit for
> > controlling PHY LEDs, possibly with the help of PHYLIB when it comes to
> > doing the l
Hi John,
On Thursday 19 May 2016 06:50:56, John Crispin wrote:
> On 18/05/2016 18:24, Florian Fainelli wrote:
> > CC'ing Andrew, John,
>
> also CC'ing Matthias and Hauke. we have had a driver in OpenWrt/LEDE for
> several years that seems a little more complete than this one.
>
> https://git.led
This currently only supports PEF7071 and allows to specify max-speed and
is able to read the LED configuration from device-tree.
Signed-off-by: Alexander Stein
---
The main purpose for now is to set a LED configuration from device tree and
to limit the maximum speed. The latter one in my case
; 1 file changed, 16 insertions(+)
Tested-by: Alexander Stein
Best regards,
Alexander
On Thursday 31 March 2016 10:41:24, Linus Walleij wrote:
> On Wed, Mar 23, 2016 at 6:01 PM, Alexander Stein
>
> wrote:
> > The interrupt for the corresponding pin is configured to trigger when the
> > pin state changes compared to a preconfigured state (Bit set in INTCON).
explict call in the MMIO code to do this.
>
> Reported-by: Alexander Stein
> Signed-off-by: Mark Brown
> ---
>
> Completely untested, I had been hoping you'd be able to write and test
> something yourself.
>
> drivers/base/regmap/regmap-mmio.c | 4 +++-
&g
| 1 +
> 1 file changed, 1 insertion(+)
Tested-by: Alexander Stein
Best regards,
Alexander
You missed CC'ing Phil (Added for this post)
On Tuesday 29 March 2016 20:53:58, Yong Li wrote:
> Thanks for your comment, I think I can change it to val[0] | (val[1]
> << 8), is it okay ?
Mh, currently there is only one caller (device_pca953x_init) which passes only
0, 0 or 0xff, 0xff, so endian
On Tuesday 29 March 2016 00:11:13, Stefan Agner wrote:
> >> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> >>
> >> @@ -14,6 +14,7 @@ Required properties:
> >> Optional properties:
> >> - clocks: Second handle
On Friday 25 March 2016 09:24:28, Stefan Agner wrote:
> Hi Alexander,
>
> On 2016-03-24 06:33, Alexander Stein wrote:
> > Using REGCACHE_RBTREE for MMIO regmap is not valid as spinlock's will be
> > used during cache allocation.
> >
> > This fixes the fol
If max_register is unset, regcache_flat_get_index will return 0 and only
memory for 1 unsigned int will be allocated, resulting in writing out
of bounds.
Signed-off-by: Alexander Stein
---
drivers/base/regmap/regcache-flat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Hi,
some comments below.
On Monday 28 March 2016 19:00:00, Stefan Agner wrote:
> Add driver for the TCON (timing controller) module. The TCON module
> is a separate module attached after the DCU (display controller
> unit). Each DCU instance has its own, directly connected TCON
> instance. The DC
On Friday 25 March 2016 11:24:59, Mark Brown wrote:
> On Wed, Mar 23, 2016 at 03:20:46PM +0100, Alexander Stein wrote:
> > The difference in those drivers is that syscon manually sets
> > config.val_format_endian before calling regmap_init_mmio.
> > spi-fsl-dspi does not
Using REGCACHE_RBTREE for MMIO regmap is not valid as spinlock's will be
used during cache allocation.
This fixes the following bug:
BUG: sleeping function called from invalid context at mm/slab.h:388
in_atomic(): 1, irqs_disabled(): 128, pid: 192, name: udevd
[...]
Signed-off-by: Alex
interrupts.
Signed-off-by: Alexander Stein
---
drivers/gpio/gpio-mcp23s08.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
index c882c2b..ac22efc 100644
--- a/drivers/gpio/gpio-mcp23s08.c
+++ b/drivers/gpio
On Wednesday 23 March 2016 13:17:59, Mark Brown wrote:
> Currently when selecting value endianness we check the register
> endiannes, not the value endianness.
>
> Reported-by: Alexander Stein
> Signed-off-by: Mark Brown
Mh, while this _does_ fix the problem regarding accessing
On Wednesday 23 March 2016 13:17:59, Mark Brown wrote:
> Currently when selecting value endianness we check the register
> endiannes, not the value endianness.
>
> Reported-by: Alexander Stein
> Signed-off-by: Mark Brown
> ---
Tested-by: Alexander Stein
Thanks and best regards,
Alexander
On Wednesday 23 March 2016 11:39:39, Mark Brown wrote:
> On Wed, Mar 23, 2016 at 12:16:13PM +0100, Alexander Stein wrote:
> > On Wednesday 23 March 2016 10:34:15, Mark Brown wrote:
>
> > > Are you *sure* that this is actually big endian? Are you basing this on
> >
On Wednesday 23 March 2016 11:08:04, Marc Zyngier wrote:
> > Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit
> > strange though:
> >> grep eth3 /proc/interrupts
> >>
> >> 63: 49 0 MSI 134742016 Edge eth3-rx-0
> >> 64: 3 0
On Wednesday 23 March 2016 10:34:15, Mark Brown wrote:
> > I'm currently trying to get PCIe working on LS1021A (little-endian
> > ARM). For link-detection I need access to a syscon perpheral (SCFG)
> > which is attched to CPU as big-endian.
>
> Are you *sure* that this is actually big endian? Are
On Wednesday 23 March 2016 09:48:42, Alexander Stein wrote:
> I'm currently trying to get PCIe working on LS1021A (little-endian ARM). For
> link-detection I need access to a syscon perpheral (SCFG) which is attched to
> CPU as big-endian.
> The corresponding DT part is:
>
n Lian
Tested-by: Alexander Stein
Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit
strange though:
> grep eth3 /proc/interrupts
>
> 63: 49 0 MSI 134742016 Edge eth3-rx-0
> 64: 3 0 MSI 134742017 Edge
Hi,
I'm currently trying to get PCIe working on LS1021A (little-endian ARM). For
link-detection I need access to a syscon perpheral (SCFG) which is attched to
CPU as big-endian.
The corresponding DT part is:
scfg: scfg@157 {
compatible = "fsl,ls1021a-
On Tuesday 08 March 2016 16:22:15, Stephen Boyd wrote:
> Some systems are memory constrained but they need to load very
> large firmwares.
Out of curiousity, about which sizes of memory and firmware are you talking
about?
Regards,
Alexander
Hi,
On Monday 07 March 2016 08:17:36, Moritz Fischer wrote:
> this series deals with most of the checkpatch warnings
> generated for macb. There are two BUG_ON()'s that I didn't touch, yet,
> that were suggested by checkpatch, that I can address in a follow up
> commit if needed.
I think addressi
On Monday 22 February 2016 10:16:20, Colin Ian King wrote:
> On 22/02/16 06:51, Alexander Stein wrote:
> > On Saturday 20 February 2016 22:10:27, Colin King wrote:
> >> From: Colin Ian King
> >>
> >> passing rtl_stats by value is inefficient; the structur
On Saturday 20 February 2016 22:10:27, Colin King wrote:
> From: Colin Ian King
>
> passing rtl_stats by value is inefficient; the structure is over 300
> bytes in size and generally just one field (packet_report_type)
> is being accessed, so the pass by value is a relatively large overhead.
> Th
On Thursday 10 December 2015 14:14:11, Bhuvanchandra DV wrote:
> On 12/10/2015 12:45 PM, Alexander Stein wrote:
> > On Thursday 10 December 2015 11:25:30, Bhuvanchandra DV wrote:
> >> DSPI instances in Vybrid have a different amount of chip selects
> >> and CTARs (Cl
. LS1021A has 6 CS and 4 CTAR
Best regards,
Alexander
--
-
Please note our closure period for Christmas vacation and turn of the year
We are closed from 21st December 2015 to 3rd January 2016
-
Dipl.-Inf. Alexander Stein
SYS TEC electronic GmbH
alexander.st...@systec-electronic.com
Legal and Com
atchdog timer is running aftyer booting,
^
typo
Best regards,
Alexander
--
Dipl.-Inf. Alexander Stein
SYS TEC electronic GmbH
alexander.st...@systec-electronic.com
Legal and Commercial Address:
Am Windrad 2
08468 Heinsdorfergrund
Ge
Hi Mikko,
On Thursday 15 October 2015 07:55:40, Mikko Rapeli wrote:
> Users of kernel header files would be happier if they did not contain
> kernel specific parts and would contain #include statements for all
> other header files that they depend on, and in general would compile.
>
> For each he
Otherwise 4294967295 (MBit/s) (-1) will be printed when there is no link.
Documentation/ABI/testing/sysfs-class-net does not state if this shall be
signed or unsigned.
Also remove the now unused variable fmt_udec.
Signed-off-by: Alexander Stein
---
Changes in v2:
* Switch the format specifier
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