Re: [PATCH] MAINTAINERS: fpga: hand off maintainership to Moritz

On Tue, Jun 18, 2019 at 2:17 AM Greg Kroah-Hartman wrote: > > On Sun, Jun 16, 2019 at 10:11:13PM -0500, Alan Tull wrote: > > I'm moving on to a new position and stepping down as FPGA subsystem > > maintainer. Moritz has graciously agreed to take over the > > maintain

Re: [PATCH] MAINTAINERS: fpga: hand off maintainership to Moritz

On Sun, Jun 16, 2019 at 10:35 PM Moritz Fischer wrote: Hi Moritz, > > Hi Alan, > > On Sun, Jun 16, 2019 at 10:11:13PM -0500, Alan Tull wrote: > > I'm moving on to a new position and stepping down as FPGA subsystem > > maintainer. Moritz has graciously agreed to tak

[PATCH] MAINTAINERS: fpga: hand off maintainership to Moritz

I'm moving on to a new position and stepping down as FPGA subsystem maintainer. Moritz has graciously agreed to take over the maintainership. Signed-off-by: Alan Tull --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 80e2bfa049d7..4487309

Re: [PATCH v3 16/16] fpga: dfl: fme: add performance reporting support

formance counters, 'clock', 'cache', 'iommu' and 'fabric', user > could read the performance counter via exposed sysfs interfaces. > Please refer to sysfs doc for more details. > > Signed-off-by: Luwei Kang > Signed-off-by: Xu Yilun > Signe

[PATCH 0/1] one fix for FPGA

Hi Greg, Please take this FPGA fix. It have been reviewed on the mailing list and applies cleanly on current linux-next and char-misc-testing. Thanks, Alan Moritz Fischer (1): fpga: zynqmp-fpga: Correctly handle error pointer drivers/fpga/zynqmp-fpga.c | 4 ++-- 1 file changed, 2 insertions

[PATCH 1/1] fpga: zynqmp-fpga: Correctly handle error pointer

Note: This does not handle the EPROBE_DEFER value in a special manner. Fixes commit c09f7471127e ("fpga manager: Adding FPGA Manager support for Xilinx zynqmp") Reported-by: Dan Carpenter Signed-off-by: Moritz Fischer Acked-by: Alan Tull --- drivers/fpga/zynqmp-fpga.c | 4 ++--

Re: [PATCH v2 05/18] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces.

On Thu, May 16, 2019 at 11:27 PM Wu Hao wrote: > > On Thu, May 16, 2019 at 12:53:00PM -0500, Alan Tull wrote: > > On Thu, May 16, 2019 at 12:36 PM Alan Tull wrote: > > > > > > On Mon, Apr 29, 2019 at 4:12 AM Wu Hao wrote: > > > > Hi Hao, > > >

Re: [PATCH v2 05/18] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces.

On Thu, May 16, 2019 at 12:36 PM Alan Tull wrote: > > On Mon, Apr 29, 2019 at 4:12 AM Wu Hao wrote: Hi Hao, Most of this patchset looks ready to go upstream or nearly so with pretty straightforward changes . Patches 17 and 18 need minor changes and please change the scnprintf in the

Re: [PATCH v2 05/18] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces.

by: Wu Hao Acked-by: Alan Tull Thanks, Alan

Re: [PATCH v2 04/18] fpga: dfl: fme: support 512bit data width PR

sion 2 > hardware doesn't support 32bit PR. > > Signed-off-by: Ananda Ravuri > Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull > --- > v2: check AVX512 support using cpu_feature_enabled() > fix other comments from Scott Wood > --- &g

Re: [PATCH v2 18/18] fpga: dfl: fme: add performance reporting support

On Mon, Apr 29, 2019 at 4:13 AM Wu Hao wrote: Hi Hao, > > This patch adds support for performance reporting private feature > for FPGA Management Engine (FME). Actually it supports 4 categories > performance counters, 'clock', 'cache', 'iommu' and 'fabric', user > could read the performance coun

[PATCH 2/4] fpga: dfl: afu: Pass the correct device to dma_mapping_error()

Acked-by: Alan Tull --- drivers/fpga/dfl-afu-dma-region.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl-afu-dma-region.c index 0bbc7142f1dc..f7d268f45df0 100644 --- a/drivers/fpga/dfl-afu-dma-region.c +++ b/drivers/fpga/dfl

[PATCH 1/4] fpga: stratix10-soc: fix use-after-free on s10_init()

ga manager driver") Signed-off-by: Wen Yang Cc: Alan Tull Cc: Moritz Fischer Cc: Nicolas Saenz Julienne Cc: linux-f...@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Moritz Fischer Reviewed-by: Nicolas Saenz Julienne Acked-by: Alan Tull --- drivers/fpga/stratix10-soc.c | 6

[PATCH 0/4] patches for FPGA

Hi Greg, Please take these four fpga fixes patches. They have been reviewed on the mailing list and apply cleanly on current linux-next and char-misc-testing. Thanks, Alan Chengguang Xu (1): fpga: dfl: expand minor range when registering chrdev region Scott Wood (2): fpga: dfl: afu: Pass t

[PATCH 4/4] fpga: dfl: expand minor range when registering chrdev region

From: Chengguang Xu Actually, total amount of available minor number for a single major is MINORMASK + 1. So expand minor range when registering chrdev region. Signed-off-by: Chengguang Xu Acked-by: Wu Hao Acked-by: Alan Tull --- drivers/fpga/dfl.c | 6 +++--- 1 file changed, 3 insertions

[PATCH 3/4] fpga: dfl: Add lockdep classes for pdata->lock

0a177 R09: 7ffe4cae0e40 [ 409.969984] R10: 7ffe4cae0160 R11: 0202 R12: 7ffe4cae0df0 [ 409.977115] R13: b680 R14: R15: 7ffe4cae0f60 Signed-off-by: Scott Wood Acked-by: Wu Hao Acked-by: Alan Tull --- drivers/fpga/dfl.c | 16 +++- 1

Re: [PATCH v2 17/18] fpga: dfl: fme: add global error reporting support

interfaces to > report different error detected by the hardware, and allow > user to clear errors or inject error for testing purpose. > > Signed-off-by: Luwei Kang > Signed-off-by: Ananda Ravuri > Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull > -

Re: [PATCH v2 12/18] fpga: dfl: afu: add error reporting support.

> > Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull Thanks! Alan > --- > v2: add more error code description for error clear sysfs in doc. > return -EINVAL instead of -EBUSY when input error code doesn't > match in error clear sysfs.

Re: [PATCH v2 02/18] fpga: dfl: fme: remove copy_to_user() in ioctl for PR

ioctl. > > > > Signed-off-by: Xu Yilun > > Signed-off-by: Wu Hao > Acked-by: Moritz Fischer Acked-by: Alan Tull Alan > > --- > > v2: clean up code split from patch 2 in v1 patchset. > > --- > > drivers/fpga/dfl-fme-pr.c | 3 --- > > 1 file

Re: [PATCH v2] fpga: zynqmp-fpga: Correctly handle error pointer

_ops_state() > error: 'eemi_ops' dereferencing possible ERR_PTR() > > Note: This does not handle the EPROBE_DEFER value in a > special manner. > > Fixes commit c09f7471127e ("fpga manager: Adding FPGA Manager support for > Xilinx zynqmp") > Reported-by: Da

Re: [PATCH] fpga: zynqmp-fpga: Correctly handle error pointer

On Tue, May 7, 2019 at 12:03 PM Moritz Fischer wrote: Hi Moritz, > > Fixes the following static checker error: > > drivers/fpga/zynqmp-fpga.c:50 zynqmp_fpga_ops_write() > error: 'eemi_ops' dereferencing possible ERR_PTR() > > Note: This does not handle the EPROBE_DEFER value in a > special

Re: [PATCH v2 15/18] fpga: dfl: fme: add thermal management support

On Mon, Apr 29, 2019 at 4:13 AM Wu Hao wrote: + The hwmon people > > This patch adds support to thermal management private feature for DFL > FPGA Management Engine (FME). This private feature driver registers > a hwmon for thermal/temperature monitoring (hwmon temp1_input). > If hardware automat

Re: [PATCH v2 16/18] fpga: dfl: fme: add power management support

On Mon, Apr 29, 2019 at 4:13 AM Wu Hao wrote: + hwmon folks > > This patch adds support for power management private feature under > FPGA Management Engine (FME). This private feature driver registers > a hwmon for power (power1_input), thresholds information, e.g. > (power1_cap / crit) and also

[PATCH 1/2] ARM: dts: socfpga: add ltc2497 on arria10 devkit

Add the two ltc2497 devices that are on the SoCFPGA Arria10 Socdk board at addresses 0x14 and 0x16. Signed-off-by: Alan Tull --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 19 +++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b

[PATCH 2/2] ARM: socfpga_defconfig: enable LTC2497

Enable the LTC2497 driver to support the two LTC2497's that are on the SoCFPGA Arria10 Devkit. Signed-off-by: Alan Tull --- arch/arm/configs/socfpga_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig

Re: [PATCH 15/17] fpga: dfl: fme: add power management support

On Thu, Apr 11, 2019 at 10:06 PM Wu Hao wrote: > > On Thu, Apr 11, 2019 at 03:07:35PM -0500, Alan Tull wrote: > > On Sun, Mar 24, 2019 at 10:24 PM Wu Hao wrote: > > > > Hi Hao, > > > > > > > > This patch adds support for power management private

Re: [PATCH] fpga: dfl: afu: Pass the correct device to dma_mapping_error()

gt; > - if (dma_mapping_error(&pdata->dev->dev, region->iova)) { > > > + if (dma_mapping_error(dfl_fpga_pdata_to_parent(pdata), > > > region->iova)) { > > > dev_err(&pdata->dev->dev, "failed to map for dma\n"); > > > ret = -EFAULT; > > > goto unpin_pages; > > > -- > > > 1.8.3.1 > > Acked-by: Moritz Fischer Acked-by: Alan Tull > > Thanks > Moritz Alan

Re: [PATCH 09/17] fpga: dfl: add id_table for dfl private feature driver

multiple dfl private features. > > > > Signed-off-by: Xu Yilun > > Signed-off-by: Wu Hao > Acked-by: Moritz Fischer Acked-by: Alan Tull Thanks, Alan

Re: [PATCH 10/17] fpga: dfl: afu: export __port_enable/disable function.

and reset port for error clearing. > > > > Signed-off-by: Xu Yilun > > Signed-off-by: Wu Hao > Acked-by: Moritz Fischer Acked-by: Alan Tull Thanks, Alan

Re: [PATCH 12/17] fpga: dfl: afu: add STP (SignalTap) support

t > > to allow userspace applications to mmap related mmio region and > > provide STP service. > > > > Signed-off-by: Xu Yilun > > Signed-off-by: Wu Hao > Acked-by: Moritz Fischer Acked-by: Alan Tull Thanks, Alan

Re: [PATCH 15/17] fpga: dfl: fme: add power management support

On Sun, Mar 24, 2019 at 10:24 PM Wu Hao wrote: Hi Hao, > > This patch adds support for power management private feature under > FPGA Management Engine (FME), sysfs interfaces are introduced for > different power management functions, users could use these sysfs > interface to get current number

Re: Device Description for FPGA Components on x86 system

On Wed, Apr 10, 2019 at 7:50 AM Federico Vaga wrote: Hi Federico, I wish I could point you to a complete solution, but there is a lot of work to be done in this area. Most of what is in the kernel is a low level in-kernel API [4]. As you correctly state, the hardest part of this is doing the e

Re: [PATCH 16/17] fpga: dfl: fme: add global error reporting support

On Sun, Mar 24, 2019 at 10:24 PM Wu Hao wrote: Hi Hao, > > This patch adds support for global error reporting for FPGA > Management Engine (FME), it introduces sysfs interfaces to > report different error detected by the hardware, and allow > user to clear errors or inject error for testing purp

Re: [PATCH 13/17] fpga: dfl: fme: add capability sysfs interfaces

gned-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull Thanks, Alan > --- > Documentation/ABI/testing/sysfs-platform-dfl-fme | 23 > drivers/fpga/dfl-fme-main.c | 48 > > 2 files changed, 71 insertions(+) >

Re: [PATCH 11/17] fpga: dfl: afu: add error reporting support.

On Sun, Mar 24, 2019 at 10:24 PM Wu Hao wrote: Hi Hao, > > Error reporting is one important private feature, it reports error > detected on port and accelerated function unit (AFU). It introduces > several sysfs interfaces to allow userspace to check and clear > errors detected by hardware. > >

Re: [PATCH v4 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

On Mon, Apr 8, 2019 at 11:51 AM Moritz Fischer wrote: > > Hi Michal, > > On Mon, Apr 08, 2019 at 04:36:15PM +0200, Michal Simek wrote: > > On 08. 04. 19 16:17, Alan Tull wrote: > > > On Mon, Apr 8, 2019 at 7:39 AM Nava kishore Manne > > > wrote: > > &

Re: [PATCH v4 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

mment. > In which kernel version i can expect this driver changes?? Patch 2/3 and 3/3 are dependent on 1/3 which isn't a drivers/fpga thing, it's drivers/firmware. Alan > > > Regards, > Navakishore. > > > -Original Message- > > From: Alan Tull [mailt

Re: [PATCHv1] fpga: mgr: add FPGA configuration log

On Wed, Apr 3, 2019 at 3:08 PM Moritz Fischer wrote: > > On Wed, Apr 03, 2019 at 01:37:51PM -0500, Alan Tull wrote: > > > > > > it's state, not status for most fpga manager drivers. It should > > > return 'operating' if everything went well. &g

Re: [PATCHv1] fpga: mgr: add FPGA configuration log

On Wed, Apr 3, 2019 at 1:05 PM Alan Tull wrote: > > On Wed, Apr 3, 2019 at 11:47 AM Moritz Fischer wrote: > > > > Hi Richard, > > > > On Wed, Apr 03, 2019 at 11:43:26AM -0500, Richard Gong wrote: > > > Hi Moritz, > > > > > > > >

Re: [PATCHv1] fpga: mgr: add FPGA configuration log

On Wed, Apr 3, 2019 at 11:47 AM Moritz Fischer wrote: > > Hi Richard, > > On Wed, Apr 03, 2019 at 11:43:26AM -0500, Richard Gong wrote: > > Hi Moritz, > > > > > > On 4/3/19 9:20 AM, Moritz Fischer wrote: > > > Hi Richard, > > > > > > On Tue, Apr 02, 2019 at 05:25:43PM -0500, richard.g...@linux.int

Re: [PATCHv1] fpga: mgr: add FPGA configuration log

On Wed, Apr 3, 2019 at 9:20 AM Moritz Fischer wrote: > > Hi Richard, > > On Tue, Apr 02, 2019 at 05:25:43PM -0500, richard.g...@linux.intel.com wrote: > > From: Richard Gong > > > > Add a log for user to know FPGA configuration is successful > > > > Signed-off-by: Richard Gong > > --- > > drive

Re: [PATCH v4 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

On Tue, Apr 2, 2019 at 7:32 AM Nava kishore Manne wrote: Hi Nava, Looks good. > > This patch adds FPGA Manager support for the Xilinx > ZynqMP chip. > > Signed-off-by: Nava kishore Manne Acked-by: Alan Tull > --- > Changes for v4: > -Updated the Fpga

Re: [PATCH 08/17] fpga: dfl: afu: add userclock sysfs interfaces.

or later revisions, userclock setting is moved > to a separated private feature, so one revision sysfs interface > is exposed to userspace application for this purpose too. > > Signed-off-by: Ananda Ravuri > Signed-off-by: Russ Weight > Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull

Re: [PATCH v5 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

> create mode 100644 > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > > > > Reviewed-by: Rob Herring Acked-by: Alan Tull

Re: [PATCH 05/17] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support.

ice of given port back to PF, it configures >PF/VF access mode to PF, then adds port platform device back to >re-enable related userspace interfaces on PF. > > Signed-off-by: Zhang Yi Z > Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull

Re: [PATCH 06/17] fpga: dfl: pci: enable SRIOV support.

gt; Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull

Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

On Mon, Mar 25, 2019 at 7:44 PM Wu Hao wrote: > > On Mon, Mar 25, 2019 at 12:50:40PM -0500, Alan Tull wrote: > > On Sun, Mar 24, 2019 at 10:23 PM Wu Hao wrote: > > > > Hi Hao, > > > > Looks good, one question below. > > > > > > > > Curr

Re: [PATCH 07/17] fpga: dfl: afu: add AFU state related sysfs interfaces

y transient APx state, > and manage AFU's LTR (latency tolerance reporting). > > Signed-off-by: Ananda Ravuri > Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull Thanks, Alan

Re: [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR

On Mon, Mar 25, 2019 at 5:58 PM Scott Wood wrote: Hi Scott, > > On Mon, 2019-03-25 at 17:53 -0500, Scott Wood wrote: > > On Mon, 2019-03-25 at 11:07 +0800, Wu Hao wrote: > > > In early partial reconfiguration private feature, it only > > > supports 32bit data width when writing data to hardware

Re: [PATCH 03/17] fpga: dfl: fme: support 512bit data width PR

r test > result. > > Please note now this optimization is only done on revision 2 > of this PR private feature which is only used in integrated > solution that AVX512 is always supported. > > Signed-off-by: Ananda Ravuri > Signed-off-by: Xu Yilun > Signed-off-by: Wu Hao Acked-by: Alan Tull

Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

On Sun, Mar 24, 2019 at 10:23 PM Wu Hao wrote: Hi Hao, Looks good, one question below. > > Current driver checks if input bitstream file size is aligned or > not per PR data width (default 32bits). It requires one additional > step for end user when they generate the bitstream file, padding > e

Re: [PATCH 01/17] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.

by: Wu Hao Acked-by: Alan Tull Thanks, Alan > --- > drivers/fpga/dfl-fme-mgr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c > index 76f3770..b3f7eee 100644 > --- a/drivers/fpga/dfl-fme-m

Re: [PATCH v3 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

On Tue, Feb 12, 2019 at 5:06 AM Moritz Fischer wrote: Hi Nava, > > + mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager", > > + &zynqmp_fpga_ops, priv); Please use the new devm_fpga_mgr_create() > > + if (!mgr) > > + return -ENOMEM; > >

Re: [GIT PULL] of: overlay: validation checks, subsequent fixes for v20 -- correction: v4.20

On Mon, Feb 11, 2019 at 1:13 PM Greg Kroah-Hartman wrote: > > On Mon, Feb 11, 2019 at 12:41:40PM -0600, Alan Tull wrote: > > On Fri, Nov 9, 2018 at 12:58 AM Frank Rowand wrote: > > > > What LTSI's are these patches likely to end up in? Just to be clear, > &g

Re: [GIT PULL] of: overlay: validation checks, subsequent fixes for v20 -- correction: v4.20

On Fri, Nov 9, 2018 at 12:58 AM Frank Rowand wrote: What LTSI's are these patches likely to end up in? Just to be clear, I'm not pushing for any specific answer, I just want to know what to expect. Thanks, Alan > > On 11/8/18 10:56 PM, Frank Rowand wrote: > > Hi Rob, > > > > Please pull the ch

Re: [PATCH] ARM: socfpga: fix base address of SDR controller

On Tue, Jan 29, 2019 at 2:09 PM Simon Goldschmidt wrote: Hi Simon, Thanks for submitting. A couple of things... > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi > index f365003f0..8f6c1a5d6 100644 > --- a/arch/arm/boot/dts/socfpga.dtsi > +++ b/arch/arm/boot/dts/s

[PATCH] fpga: stratix10-soc: fix wrong of_node_put() in init function

tly decreasing the refcount on that node again. This patch removes the unwarranted call to of_node_put(). Fixes: e7eef1d7633a ("fpga: add intel stratix10 soc fpga manager driver") Signed-off-by: Nicolas Saenz Julienne Acked-by: Alan Tull Acked-by: Moritz Fischer [atull: remove unneces

Re: [PATCH 1/3] fpga: stratix10-soc: fix wrong of_node_put() in init function

On Thu, Jan 24, 2019 at 2:46 PM Alan Tull wrote: > > From: Nicolas Saenz Julienne > > After finding a "firmware" dt node stratix10 tries to match it's > compatible string with it. To do so it's calling of_find_matching_node() > which already takes care of de

[PATCH 3/3] fpga: mgr: altera-ps-spi: make array dummy static, shrinks object size

data bss dec hex filename 72812096 0937724a1 drivers/fpga/altera-ps-spi.o (gcc version 8.2.0 x86_64) Signed-off-by: Colin Ian King Acked-by: Alan Tull Acked-by: Moritz Fischer --- drivers/fpga/altera-ps-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH 2/3] fpga: altera_freeze_bridge: remove restriction to socfpga

The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA since it can be used on other platforms such as Stratix10. Signed-off-by: Alan Tull Reviewed-by: Moritz Fischer --- drivers/fpga/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/Kconfig b

[PATCH 0/3] patches for FPGA

ther two can go in whenever is appropriate. Thanks, Alan Alan Tull (1): fpga: altera_freeze_bridge: remove restriction to socfpga Colin Ian King (1): fpga: mgr: altera-ps-spi: make array dummy static, shrinks object size Nicolas Saenz Julienne (1): fpga: stratix10-soc: fix wrong of_nod

[PATCH 1/3] fpga: stratix10-soc: fix wrong of_node_put() in init function

tly decreasing the refcount on that node again. This patch removes the unwarranted call to of_node_put(). Fixes: e7eef1d7633a ("fpga: add intel stratix10 soc fpga manager driver") Signed-off-by: Nicolas Saenz Julienne Acked-by: Alan Tull Acked-by: Moritz Fischer --- drivers/fpga/s

Re: [PATCH] fpga: mgr: altera-ps-spi: make array dummy static, shrinks object size

ec hex filename >73712032 0940324bb drivers/fpga/altera-ps-spi.o > > After: >textdata bss dec hex filename >72812096 0937724a1 drivers/fpga/altera-ps-spi.o > > (gcc version 8.2.0 x86_64) > > Signed-off-by:

Re: [PATCHv1] firmware: intel_stratix10_service: add hardware dependency

On Wed, Jan 23, 2019 at 10:42 AM Dinh Nguyen wrote: > > > > On 1/23/19 10:37 AM, Alan Tull wrote: > > On Wed, Jan 23, 2019 at 10:00 AM Greg KH wrote: > > > > Hi Greg, > > > >> > >> On Wed, Jan 23, 2019 at 09:47:56AM -0600, richard.g...

Re: [PATCHv1] firmware: intel_stratix10_service: add hardware dependency

On Wed, Jan 23, 2019 at 10:00 AM Greg KH wrote: Hi Greg, > > On Wed, Jan 23, 2019 at 09:47:56AM -0600, richard.g...@linux.intel.com wrote: > > From: Richard Gong > > > > Add a Kconfig dependency to ensure Intel Stratix10 service layer driver > > can be built only on the platform that supports i

Re: [PATCH v3] fpga: altera_freeze_bridge: remove restriction to socfpga

On Sat, Jan 19, 2019 at 6:41 PM Moritz Fischer wrote: > > On Tue, Jan 15, 2019 at 6:01 PM Alan Tull wrote: > > > > The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA > > since it can be used on other platforms such as Stratix10. > > > > Sig

[PATCH v3] fpga: altera_freeze_bridge: remove restriction to socfpga

The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA since it can be used on other platforms such as Stratix10. Signed-off-by: Alan Tull --- v2: add depends on HAS_IOMEM v3: put both dependencies on one line --- drivers/fpga/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH v2] fpga: altera_freeze_bridge: remove restriction to socfpga

On Tue, Jan 15, 2019 at 11:47 AM Dinh Nguyen wrote: > > minor nit > > On 1/14/19 4:33 PM, Alan Tull wrote: > > The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA > > since it can be used on other platforms such as Stratix10. > > > > Signed-off

[PATCH v2] fpga: altera_freeze_bridge: remove restriction to socfpga

The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA since it can be used on other platforms such as Stratix10. Signed-off-by: Alan Tull --- drivers/fpga/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index

Re: [PATCH] fpga: altera_freeze_bridge: remove restriction to socfpga

On Fri, Jan 11, 2019 at 12:42 PM Moritz Fischer wrote: Hi Moritz, > > Hi Alan, > > On Thu, Jan 10, 2019 at 3:06 PM Alan Tull wrote: > > > > The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA > > since it can be used on other platforms such as St

[PATCH] fpga: altera_freeze_bridge: remove restriction to socfpga

The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA since it can be used on other platforms such as Stratix10. Signed-off-by: Alan Tull --- drivers/fpga/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index

Re: [PATCH] fpga: stratix10-soc: fix wrong of_node_put() in init function

ot;fpga: add intel stratix10 soc fpga manager driver") > Signed-off-by: Nicolas Saenz Julienne Acked-by: Alan Tull > --- > drivers/fpga/stratix10-soc.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c > i

[PATCH 1/2] fpga: altera-cvp: fix probing for multiple FPGAs on the bus

Signed-off-by: Anatolij Gustschin Acked-by: Alan Tull --- drivers/fpga/altera-cvp.c | 34 -- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 7395085..35c3aa5 100644 --- a/drivers/fpga/alt

[PATCH 2/2] fpga: mgr: altera-ps-spi: enable usage on non-dt platforms

data. This allows driver binding to dynamically added PS-SPI devices (e.g. when added via spi_new_device() after hot-plugging). Signed-off-by: Anatolij Gustschin Acked-by: Alan Tull --- drivers/fpga/altera-ps-spi.c | 40 +++- 1 file changed, 35 insertions(+), 5

[PATCH 0/2] patches for FPGA

Hi Greg, Please take these two fpga fixes patches. They have been reviewed on the mailing list and apply cleanly on current linux-next. Thanks, Alan Anatolij Gustschin (2): fpga: altera-cvp: fix probing for multiple FPGAs on the bus fpga: mgr: altera-ps-spi: enable usage on non-dt platforms

Re: [PATCH 5/5] fpga: dfl-fme-region: Use platform_get_drvdata()

On Mon, Nov 12, 2018 at 12:02 PM Greg Kroah-Hartman wrote: > > On Mon, Nov 12, 2018 at 09:46:53AM -0600, Alan Tull wrote: > > On Sun, Sep 30, 2018 at 10:48 AM Greg Kroah-Hartman > > wrote: > > > > Hi Greg, > > > > > > > > On Wed, Sep 12, 2

[RESEND 1/2] fpga: of-fpga-region: Use platform_set_drvdata

From: Moritz Fischer Use platform_set_drvdata rather than dev_set_drvdata to match the platform_get_drvdata in the _remove() function of the platform driver. Signed-off-by: Moritz Fischer Acked-by: Alan Tull --- drivers/fpga/of-fpga-region.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[RESEND 2/2] fpga: dfl-fme-region: Use platform_get_drvdata()

From: Moritz Fischer Use platform_get_drvdata() in remove() function of the platform driver rather than dev_get_drvdata() to match the platform_set_drvdata in the probe(). Signed-off-by: Moritz Fischer Acked-by: Alan Tull --- drivers/fpga/dfl-fme-region.c | 2 +- 1 file changed, 1 insertion

[RESEND 0/2] fpga fixes for 4.20

Hi Greg, Here's a reposting of the two small fixes for fpga, please take them in. They've been reviewed on the mailing list and apply cleanly on today's char-misc-test. Thanks, Alan Moritz Fischer (2): fpga: of-fpga-region: Use platform_set_drvdata fpga: dfl-fme-region: Use platform_get_drv

Re: [PATCH 4/5] fpga: of-fpga-region: Use platform_set_drvdata

On Sun, Sep 30, 2018 at 10:49 AM Greg Kroah-Hartman wrote: Hi Greg, > > On Wed, Sep 12, 2018 at 09:43:26AM -0500, Alan Tull wrote: > > From: Moritz Fischer > > > > Use platform_set_drvdata rather than dev_set_drvdata > > to match the platform_get_drvdata in the

Re: [PATCH 5/5] fpga: dfl-fme-region: Use platform_get_drvdata()

On Sun, Sep 30, 2018 at 10:48 AM Greg Kroah-Hartman wrote: Hi Greg, > > On Wed, Sep 12, 2018 at 09:43:27AM -0500, Alan Tull wrote: > > From: Moritz Fischer > > > > Use platform_get_drvdata() in remove() function of > > the platform driver rather than dev_

[PATCH 2/4] fpga: dfl: fme: remove set but not used variable 'priv'

ritz Fischer Acked-by: Wu Hao Acked-by: Alan Tull --- drivers/fpga/dfl-fme-pr.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c index 0b84053..fe5a557 100644 --- a/drivers/fpga/dfl-fme-pr.c +++ b/drivers/fpga/dfl-fme-pr.c @@

[PATCH 4/4] zynq-fpga: Only route PR via PCAP when required

. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans Reviewed-by: Moritz Fischer Acked-by: Alan Tull --- drivers/fpga/zynq-fpga.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index bb82efe

[PATCH 1/4] fpga: altera-cvp: fix 'bad IO access' on x86_64

ned-off-by: Anatolij Gustschin Acked-by: Alan Tull --- drivers/fpga/altera-cvp.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 610a155..144fa2a 100644 --- a/drivers/fpga/altera-cvp.c +++ b/drivers/fpga/al

[PATCH 0/4] patches for FPGA

Hi Greg, Please take these four small fpga fixes patches. They have been reviewed on the mailing list and apply cleanly on current linux-next and char-misc-testing. Thanks, Alan Anatolij Gustschin (1): fpga: altera-cvp: fix 'bad IO access' on x86_64 Andreas Puhm (1): fpga: altera-cvp: Fix

[PATCH 3/4] fpga: altera-cvp: Fix registration for CvP incapable devices

eviewed-by: Moritz Fischer Acked-by: Alan Tull --- drivers/fpga/altera-cvp.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c index 144fa2a..7395085 100644 --- a/drivers/fpga/altera-cvp.c +++ b/drivers/fpga/altera-cvp.c @@ -40

Re: [PATCH v2] fpga: altera-cvp: Fix registration for CvP incapable devices

; properly determine if FPGA Manager functionality can be safely > > enabled. > > > > Fixes: 34d1dc17ce97 ("fpga manager: Add Altera CvP driver") > > Signed-off-by: Andreas Puhm > > Signed-off-by: Anatolij Gustschin > > Reviewed-by: Moritz Fischer Acked-

Re: [PATCH v2] zynq-fpga: Only route PR via PCAP when required

the > device is actively being accessed by the driver for programming. > > This allows both PCAP and ICAP interfaces to be used for PR. > > Signed-off-by: Mike Looijmans > Reviewed-by: Moritz Fischer Acked-by: Alan Tull Thanks for submitting! Alan > --- > v2: Move th

Re: [PATCH] fpga: altera-cvp: Fix registration for CvP incapable devices

On Tue, Oct 23, 2018 at 4:26 AM Moritz Fischer wrote: > > Hi Andreas, > > we're getting there :) It seems your mail setup is still a bit > funky though. Did you use git send-email / git format-patch? > > On Tue, Oct 23, 2018 at 09:01:39AM +, Andreas Puhm wrote: > > From bfc602900b016f65bc2f183

Re: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne wrote: Hi Nava, Just some nits, below. > > Add documentation to describe Xilinx ZynqMP fpga driver > bindings. > > Signed-off-by: Nava kishore Manne > --- > Changes for v1: > Created a Seperate(New) DT binding file as >

Re: [PATCH 0/3] Add Bitstream configuration support for ZynqMP

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne wrote: Hi Nava, > > This series of patches are created On top of the > below repo. > //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git > BRANCH: next/drivers. IIUC this is dependent on some patches that aren't released yet. Please make

Re: [PATCH v5 8/8] clk: fixed-rate: Convert into a module platform driver

On Thu, Oct 18, 2018 at 3:24 PM Stephen Boyd wrote: > > Quoting Alan Tull (2018-10-18 12:20:58) > > On Tue, Jul 5, 2016 at 11:45 AM Ricardo Ribalda Delgado > > wrote: > > > > I've stumbled across a of_node_get/put imbalance that happens when the > > fi

Re: [PATCH] clk: fixed-rate: fix of_node_get-put imbalance

On Thu, Oct 18, 2018 at 3:22 PM Stephen Boyd wrote: > > Quoting Alan Tull (2018-10-18 12:54:11) > > When the fixed rate clock is created by devicetree, > > of_clk_add_provider is called. Add a call to > > of_clk_del_provider in the remove function to balance > >

[PATCH] clk: fixed-rate: fix of_node_get-put imbalance

When the fixed rate clock is created by devicetree, of_clk_add_provider is called. Add a call to of_clk_del_provider in the remove function to balance it out. Signed-off-by: Alan Tull --- drivers/clk/clk-fixed-rate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-fixed

Re: [PATCH v5 8/8] clk: fixed-rate: Convert into a module platform driver

On Tue, Jul 5, 2016 at 11:45 AM Ricardo Ribalda Delgado wrote: I've stumbled across a of_node_get/put imbalance that happens when the fixed rate clock is added and deleted using device tree. The cause is that this driver calls of_clk_add_provider() when probed, but doesn't call of_clk_del_provid

Re: [PATCH v4 01/18] of: overlay: add tests to validate kfrees from overlay removal

On Mon, Oct 15, 2018 at 9:39 PM wrote: Hi Frank, > > From: Frank Rowand > > Add checks: > - attempted kfree due to refcount reaching zero before overlay > is removed > - properties linked to an overlay node when the node is removed > - node refcount > one during node removal in a chan

Re: [PATCH v2] of: overlay: user space synchronization

On Mon, Oct 15, 2018 at 7:28 PM wrote: Hi Frank, Thanks for all your work on this! > From: Frank Rowand > > When an overlay is applied or removed, the live devicetree visible in > /proc/device-tree/, aka /sys/firmware/devicetree/base/, reflects the > changes. There is no method for user space

Re: [PATCH] of: overlay: user space synchronization

On Mon, Oct 15, 2018 at 7:04 PM Frank Rowand wrote: > > On 10/15/18 13:38, Alan Tull wrote: > > On Mon, Oct 15, 2018 at 1:09 PM Frank Rowand wrote: > >> > >> On 10/15/18 01:24, Geert Uytterhoeven wrote: > >>> > >>> Please say explicitly that

[PATCH 4/4] docs: fpga: document programming fpgas using regions

Clarify the intention that interfaces and upper layers use regions rather than managers directly. Rearrange API documentation to better group the API functions used to create FPGA mgr/bridge/regions and the API used for programming FPGAs. Signed-off-by: Alan Tull Suggested-by: Federico Vaga

[PATCH 3/4] fpga: add devm_fpga_region_create

Add devm_fpga_region_create() which is the managed version of fpga_region_create(). Change current region drivers to use devm_fpga_region_create(). Signed-off-by: Alan Tull Suggested-by: Federico Vaga Acked-by: Moritz Fischer --- Documentation/driver-api/fpga/fpga-region.rst | 3 ++ drivers

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