Hi, Doug
I have two cards which are easy to get "Timeout sending command":
one is ADATA uhs-1 SDR50, another is Kingston uhs-1 SDR104.
After merge three patches:
--
* mmc: dw_mmc: Don't start commands while busy
https://patchwork.kernel.org/patch/5858221/
* mmc: dw_mmc: Make sure we only adjust
a
data transfer again if we got DRTO and EBE interrupt.
After this patch, all mmc_test cases can pass on RK3288-Pink2 board.
Signed-off-by: Addy Ke
---
Changes in v2:
- DRTO and EBE are both set, should not send abort command too,
suggested by Doug Anderson.
drivers/mmc/host/dw_mmc.c | 10
resume test.
Reviewed-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- add this capability for all 4 slots, suggested by Doug Anderson.
drivers/mmc/host/dw_mmc-rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c
b/drivers/mmc/host
Hi, Javier and Alim
These days are Spring Festival holiday.
Sorry for late reply.
On 2015/2/15 19:41, Javier Martinez Canillas wrote:
> Hello Addy,
>
> On Sat, Feb 14, 2015 at 7:17 AM, Addy Ke wrote:
>> patch 1: This patch can fix bug that controller is still data busy after
&g
Hi, Alim
Sorry for late reply.
On 2015/2/16 07:28, Alim Akhtar wrote:
> Hi Addy,
>
> On Sat, Feb 14, 2015 at 11:47 AM, Addy Ke wrote:
>> As show in mmc_power_up(), in MMC_POWER_UP state, the voltage isn't
>> stable and we may get 'data busy' which can
We should wait until unbusy before the next request.
But this does't need if the command is CMD13, which can access
SD Status register regardless of data busy.
Signed-off-by: Addy Ke
---
Changes in v4:
- CMD13 doesn't need wait until unbusy.
drivers/mmc/host/dw_mmc.c | 4
1 fi
we will get 'Timeout sending command', and then system will
be blocked. To avoid this, we need reset mmc controller.
Signed-off-by: Addy Ke
Changes in v4:
- Retry to wait and reset all blocks until data unbusy.
I have a sd card, which need retry 2 times to change to unbusy state.
--
e
patch3: This patch fix bug that there is data busy before sdio send CMD53.
But This patch is necessary for sd and mmc too.
Addy Ke (3):
mmc: dw_mmc: update clock after host reach a stable voltage
mmc: dw_mmc: fix bug that cause 'Timeout sending command'
mmc: dw_mmc:
As show in mmc_power_up(), in MMC_POWER_UP state, the voltage isn't
stable and we may get 'data busy' which can't be cleaned by resetting
all blocks. So we should not send command to update clock in this state.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 3 ++
We should wait for data busy here in non-volt-switch state.
This may happend when sdio sends CMD53.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index f0d9da5..23507c9 100644
we will get 'Timeout sending command', and then system will
be blocked. To avoid this, we need reset mmc controller.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/d
e
patch3: This patch fix bug that there is data busy before sdio send CMD53.
But This patch is necessary for sd and mmc too.
Addy Ke (3):
mmc: dw_mmc: update clock after host reach a stable voltage
mmc: dw_mmc: fix bug that cause 'Timeout sending command'
mmc: dw_mmc:
As show in mmc_power_up(), in MMC_POWER_UP state, the voltage isn't
stable and we may get 'data busy' which can't be cleaned by resetting
all blocks. So we should not send command to update clock in this state.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 3 ++
On 2015/2/12 21:59, Alim Akhtar wrote:
> On Thu, Feb 12, 2015 at 4:40 PM, Andrzej Hajda wrote:
>> On 02/12/2015 03:28 AM, addy ke wrote:
>>> Hi Andrzej and Alim
>>>
>>> On 2015/2/12 07:20, Alim Akhtar wrote:
>>>> Hi Andrzej,
>>>>
resume test.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc-rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c
b/drivers/mmc/host/dw_mmc-rockchip.c
index e2a726a..e5f57b5 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc
will be in busy state. This should not happend when mmc controller
>>>>> send command to update card clocks. If this happends, mci_send_cmd will
>>>>> be failed and we will get 'Timeout sending command', and then system will
>>>>> be blocked.
On 2015/2/9 15:04, Jaehoon Chung wrote:
> On 02/09/2015 03:56 PM, Addy wrote:
>>
>>
>> On 2015.02.09 12:51, Ulf Hansson wrote:
>>> On 5 February 2015 at 12:13, Addy Ke wrote:
>>>> Because of some uncertain factors, such as worse card or worse hard
We should wait for data busy here in non-volt-switch state.
This may happend when sdio sends CMD53.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b0b57e3..b40080d 100644
Addy Ke (2):
mmc: dw_mmc: fix bug that cause 'Timeout sending command'
mmc: dw_mmc: Don't start command while data busy
drivers/mmc/host/dw_mmc.c | 35 +++
1 file changed, 35 insertions(+)
--
Changes in v2:
- add new patch to handle data
we will get 'Timeout sending command', and then system will
be blocked. To avoid this, we need reset mmc controller.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/driver
Signed-off-by: Addy Ke
---
Changes in v2:
- fix some typo
Documentation/devicetree/bindings/mmc/mmc.txt | 1 +
drivers/mmc/core/host.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt
b/Documentation/devicetree
we will get 'Timeout sending command', and then system will
be blocked. To avoid this, we need reset mmc controller.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc.c b/driver
Signed-off-by: Addy Ke
---
Documentation/devicetree/bindings/mmc/mmc.txt | 11 +++
drivers/mmc/core/host.c | 2 ++
2 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt
b/Documentation/devicetree/bindings/mmc/mmc.txt
index
a
data transfer again if we got DRTO and EBE interrupt.
After this patch, all mmc_test cases can pass on RK3288-Pink2 board.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc
We need to take the card pointer in execute_tuning() for mmc_send_status(),
but mmc->card is NULL in tuning state. So we need change the first parameter
of execute_tuning() to card pointer(struct mmc_card * card).
Signed-off-by: Addy Ke
---
drivers/mmc/core/core.c | 2 +-
drivers/
This patch based on Alex's patch:
https://patchwork.kernel.org/patch/5516411/
Signed-off-by: Addy Ke
---
drivers/mmc/core/mmc_ops.h | 1 -
drivers/mmc/host/dw_mmc.c | 48 --
include/linux/mmc/card.h | 2 ++
3 files changed, 44 insertions(
Addy Ke (2):
mmc: core: use card pointer as the first parameter of execute_tuning()
mmc: dw_mmc: wait until card ready if tuning fails
drivers/mmc/core/core.c | 2 +-
drivers/mmc/core/mmc_ops.h| 1 -
drivers/mmc/host/dw_mmc.c | 51
.
We don't know why we have this problem, but we need it to fix this problem now.
And I will post a follow up change when we find the root cause.
Signed-off-by: Addy Ke
---
Changes in v2:
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dto_start_monitor func.
- use "
.
We don't know why we have this problem, but we need it to fix this problem now.
And I will post a follow up change when we find the root cause.
Signed-off-by: Addy Ke
---
Changes in v2:
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dto_start_monitor func.
- use "
-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium project
Changes in v3:
- merged the patch that Doug submitted to chromium to projectchange bindins
see: https://chromium-review.googlesource.com/#/c/232774/
Changes in
. see:
https://chromium-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium project
Changes in v3:
- merged the patch that Doug submitted to chromium to projectchange bindins
see: https://chromium-review.googlesource.com
mmit dfac17:
idx = active = thrd->req_runnig = 0 -->
descdone = thrd->req[0] = NULL -->
list_add_tail(&descdone->rqd, &pl330->req_done); -->
got NULL pointer!!!
Signed-off-by: Addy Ke
---
drivers/dma/pl330.c | 6 ++
1 file changed, 6 insertions(+)
On 2014/12/8 10:59, Addy Ke wrote:
> high_ns calculated from the low division of CLKDIV register is the sum
> of actual measured high_ns and rise_ns. The rise time which related to
> external pull-up resistor can be up to the maximum rise time in I2C spec.
>
> In my test, if e
for signals from the device tree.
This allows us to more accurately calculate timings. see:
https://chromium-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium
Changes in v3:
- merged the patch that Doug submitted to
team
was based on this freequency point.
Signed-off-by: Addy Ke
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index acb6a2f..9c35a1d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arc
ollow up change when we find the root cause.
Signed-off-by: Addy Ke
---
Changes in v2:
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dto_start_monitor func.
- use "broken-dto" for new quirk and change Subject for it.
Changes in v3:
- Remove dts for brok
for signals from the device tree.
This allows us to more accurately calculate timings. see:
https://chromium-review.googlesource.com/#/c/232774/
Signed-off-by: Addy Ke
---
Changes in v2:
- merged the patch that Doug submitted to chromium
Documentation/devicetree/bindings/i2c/i2c-rk3x.txt | 10
Hi,
On 2014/11/27 06:46, Doug Anderson wrote:
> Hi,
>
> On Tue, Nov 25, 2014 at 12:10 AM, Addy Ke wrote:
>> This patch add a new quirk to add a s/w timer to notify the driver
>> to terminate current transfer and report a data timeout to the core,
>> if DTO interru
that host should get DRTO and DTO interrupt.
But we really don't get any data-related interrupt in RK3X SoCs.
And driver can't get data transfer state, it can do nothing but wait for.
Signed-off-by: Addy Ke
---
- fix some typo.
- remove extra timeout value (250ms).
- remove dw_mci_dt
Hi, Jaehoon
On 2014/11/19 13:56, addy ke wrote:
> Hi Jaehoon
>
> On 2014/11/19 09:22, Jaehoon Chung Wrote:
>> Hi, Addy.
>>
>> On 11/18/2014 09:32 AM, Addy wrote:
>>>
>>> On 2014年11月14日 21:18, Jaehoon Chung wrote:
>>>> Hi, Addy.
>>&g
interrupts
>> come,
>> and interrupt handle function(dw_mci_interrupt) will not be called. So we
>> need a
>> timer to handle this case.
>>
>> So I think SDMMC_INT_DATA_OVER is not suitable for this case, and we need a
>> new
>> quirk.
>>
&
From: Addy
This patch add a new quirk to notify the driver to teminate
current transfer and report a data timeout to the core,
if data over interrupt does NOT come within the given time.
dw_mmc call mmc_request_done func to finish transfer depends on
data over interrupt. If data over interrupt d
On 2014/11/13 02:04, Doug Anderson wrote:
> Ulf,
>
> On Tue, Nov 11, 2014 at 12:52 AM, Ulf Hansson wrote:
>> On 11 November 2014 05:02, Addy Ke wrote:
>>> SD2.0 cards need vqmmc and vmmc to be the same.
>>
>> No, that's not correct.
>>
>
)
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b4c3044..a8b70b5 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1163,8
actual measured high_ns is about 3900ns, which is less than 4000ns
(the minimum high_ns in I2C spec).
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 58 +++
1 file changed, 37 insertions(+), 21 deletions(-)
diff --git a/drivers/i2c/busses/i2c
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 on Rockchip SoCs.This patch add sdio_id0 for the
number of slot0 in the SDIO interrupt registers.
Signed-off-by: Addy Ke
---
Changes in v2:
- rebase on http://git.linaro.org/git/people/ulf.hansson/mmc.git, next branch
Hi, Jaehoo
On 2014/11/3 16:59, Jaehoon Chung wrote:
> Hi, Addy.
>
> On 11/03/2014 10:20 AM, Addy Ke wrote:
>> The bit of sdio interrupt is 16 in designware implementation,
>> but it is 24 on Rockchip SoCs.This patch add sdio_id0 for the
>> number of slot0 in t
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 on Rockchip SoCs.This patch add sdio_id0 for the
number of slot0 in the SDIO interrupt registers.
Signed-off-by: Addy Ke
---
Changes in v2:
- rebase on http://git.linaro.org/git/people/ulf.hansson/mmc.git, next branch
On 2014/10/31 18:43, Heiko Stübner wrote:
> Am Freitag, 31. Oktober 2014, 11:50:09 schrieb Addy Ke:
>> The bit of sdio interrupt is 16 in designware implementation,
>> but it is 24 in RK3288. This patch add sdio_id0 for the number
>> of slot0 in the SDIO interrupt registers
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 in RK3288. This patch add sdio_id0 for the number
of slot0 in the SDIO interrupt registers, which can be set in
platform DT table, such as:
- rockchip,sdio-interrupt-slot0 = <8>;
Signed-off-by: Addy Ke
---
Changes
On 2014/10/30 19:17, Jaehoon Chung wrote:
> On 10/30/2014 08:11 PM, Ulf Hansson wrote:
>> On 30 October 2014 11:50, Addy Ke wrote:
>>> The bit of sdio interrupt is 16 in designware implementation,
>>> but it is 24 in RK3288. This patch add sdio_id0 for the numb
o my patch is based on kernel-3.18.
I will send patch v2 for this.
Would you please give me a git url for it?
Thank you.
>
> Best Regards,
> Jaehoon Chung
>
> On 10/30/2014 07:50 PM, Addy Ke wrote:
>> The bit of sdio interrupt is 16 in designware implementation,
>> b
The bit of sdio interrupt is 16 in designware implementation,
but it is 24 in RK3288. This patch add sdio_id0 for the number
of slot0 in the SDIO interrupt registers, which can be set in
platform DT table, such as:
- rockchip,sdio-interrupt-slot0 = <8>;
Signed-off-by: Addy Ke
---
drive
Hi, Doug,
On 2014/10/30 12:49, Doug Anderson wrote:
> Addy,
>
> On Wed, Oct 29, 2014 at 9:41 PM, Doug Anderson wrote:
>> You can avoid a lot of "if" tests if you just add a new "sdio->id"
>
> Whoops, I mean "slot->sdio_id"
>
To use "slot->sdio_id", I think the subject must be changed.
So I wi
This patch add a quirk: DW_MCI_QUIRK_SDIO_INT_24BIT.
The bit of sdio interrupt is 16 in designware implementation, but
is 24 in RK3288. To support RK3288 mmc controller, we need add
a quirk for it.
Signed-off-by: Addy Ke
---
drivers/mmc/host/dw_mmc.c | 32
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 153269b..87bc16f 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -418,8 +418,10
On 2014/10/16 17:34, Mark Brown wrote:
> On Thu, Oct 16, 2014 at 05:16:02PM +0800, addy ke wrote:
>> On 2014/10/15 21:04, Mark Brown wrote:
>>> On Wed, Oct 15, 2014 at 07:25:49PM +0800, Addy Ke wrote:
>
>>>> + if (WARN_ON(rs->speed > MAX_SCLK_OUT))
&
_current_transfer(rs->master);
+ }
spin_unlock_irqrestore(&rs->lock, flags);
}
Sorry for my mistake, I have not put these changes to this patch.
Do I need send patch v2 or a new patch to fix this issure?
On 2014/10/15 21:05, Mark Brown wrote:
> On Wed, Oct 15, 2014 at 07:26:18PM +0800, Addy Ke wrote:
&
hi, Mark
On 2014/10/15 21:04, Mark Brown wrote:
> On Wed, Oct 15, 2014 at 07:25:49PM +0800, Addy Ke wrote:
>
>> +if (WARN_ON(rs->speed > MAX_SCLK_OUT))
>> +rs->speed = MAX_SCLK_OUT;
>> +
>> +/* the minimum divsor is 2 */
&
In rx mode, dma must be prepared before spi is enabled.
But in tx and tr mode, spi must be enabled first.
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 34 +++---
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b
Patch 1: fix bug that case spi can't go as fast as slave request
Patch 2: fix bug that cause spi transfer timed out in DMA duplex mode
Tested on rk3288-pinky-version2 board.
Addy Ke (2):
spi/rockchip: fix bug that case spi can't go as fast as slave request
spi/rockchip: fix bug
Because the minimum divisor in rk3x's spi controller is 2,
if spi_clk is less than 2 * sclk_out, we can't get the right divisor.
So we must set spi_clk again to match slave request.
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 12
1 file changed, 12 insertion
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- remove Fast-mode plus and HS-mode
- use new formulas suggested by Doug
Changes in V3:
- use new formulas (sep 30) suggested by Doug
Changes in V4:
- fix some wrong style
- WARN_ONCE if min_low_div
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- remove Fast-mode plus and HS-mode
- use new formulas suggested by Doug
Changes in V3:
- use new formulas (sep 30) suggested by Doug
Changes in V4:
- fix some wrong style
- WARN_ONCE if min_low_div
Tested-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- remove Fast-mode plus and HS-mode
- use new formulas suggested by Doug
Changes in V3:
- use new formulas (sep 30) suggested by Doug
Changes in V3:
- fix some wrong style
- WARN_ONCE if min_low_div > max_low_div
drivers/
measured i2c SCL waveforms in fast-mode by oscilloscope
on rk3288-pinky board. the LOW period of the scl clock is 1.3us.
It is so critical that we must adjust LOW division to increase
the LOW period of the scl clock.
Thanks Doug for the suggestion about division formulas.
Signed-off-by: Addy Ke
Hi Doug
On 2014/9/29 12:39, Doug Anderson wrote:
> Addy,
>
> On Sat, Sep 27, 2014 at 12:11 AM, Addy Ke wrote:
>> From: Addy
>>
>> As show in I2C specification:
>> - Standard-mode: the minimum HIGH period of the scl clock is 4.0us
>> the
From: Addy
As show in I2C specification:
- Standard-mode: the minimum HIGH period of the scl clock is 4.0us
the minimum LOW period of the scl clock is 4.7us
- Fast-mode: the minimum HIGH period of the scl clock is 0.6us
the minimum LOW period of the scl clock is 1.3u
On 2014/9/26 10:08, Doug Anderson wrote:
> Addy,
>
> On Thu, Sep 25, 2014 at 6:40 PM, addy ke wrote:
>> Hi, Doug
>>
>> On 2014/9/26 5:52, Doug Anderson wrote:
>>> Addy,
>>>
>>> On Wed, Sep 24, 2014 at 9:36 PM, Doug Anderson
>>&
Hi, Doug
On 2014/9/26 5:52, Doug Anderson wrote:
> Addy,
>
> On Wed, Sep 24, 2014 at 9:36 PM, Doug Anderson wrote:
>> Addy,
>>
>> On Wed, Sep 24, 2014 at 6:56 PM, addy ke wrote:
>>> In my measurement,all paramter but "Data hold time" are match the
In my test on RK3288-pinky board, if spi is enabled, it will begin to
read data from slave regardless of whether the DMA is ready. So we
need prepare DMA before spi is enable.
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 15 +++
1 file changed, 7 insertions(+), 8
Hi, Doug
On 2014/9/25 1:13, Doug Anderson wrote:
> Addy,
>
> On Wed, Sep 24, 2014 at 1:23 AM, addy ke wrote:
>>
>>
>> On 2014/9/24 12:10, Doug Anderson wrote:
>>> Addy,
>>>
>>> On Tue, Sep 23, 2014 at 6:55 PM, Addy Ke wrote:
>>>&
On 2014/9/24 12:10, Doug Anderson wrote:
> Addy,
>
> On Tue, Sep 23, 2014 at 6:55 PM, Addy Ke wrote:
>> As show in I2C specification:
>> - Standard-mode:
>> the minimum HIGH period of the scl clock is 4.0us
>> the minimum LOW period of the scl clock
estion about division formula.
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 79 +++
1 file changed, 72 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 93cfc83..49d67b7 100644
--- a/d
Add public list
On 2014/9/17 23:17, Doug Anderson wrote:
> Addy,
>
> On Tue, Sep 16, 2014 at 6:30 PM, addy...@rock-chips.com
> wrote:
>> hi, all
>
> Any reason why you didn't add some public lists? It seems like this
> is a perfect discussion for linux-i2c.
>
>
>> According to i2c-bus specif
)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b
> Addy,
>
> On Thu, Sep 4, 2014 at 7:32 PM, Addy Ke wrote:
>> I2C_CLKDIV register descripted in the previous version of
>> RK3x chip manual is incorrect. Plus 1 is required.
>>
>> The correct formula:
>> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
>&g
)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..76b6604 100644
--- a/drivers/i2c
> Addy,
>
> On Fri, Aug 22, 2014 at 11:00 AM, Addy Ke wrote:
>> In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
>> in one chunk, so the size of data to be write/read to/from TXDATAx/RXDATAx
>> must be less than or equal 32 bytes at a time.
&
-by: Addy Ke
Acked-by: Max Schwarz
---
Changes in v2:
- Use cleaner syntax as suggested by Sergei.
- Update commit message as suggested by Wolfram.
Changes in v3:
- fix typo: maste --> master and double spaces after 'len'
drivers/i2c/busses/i2c-rk3x.c | 4
Changes in v4:
- re
In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
in one chunk, so the size of data to be write/read to/from TXDATAx/RXDATAx
must be less than or equal 32 bytes at a time.
Tested on rk3288-pinky board, elan receive 158 bytes data.
Acked-by: Max Schwarz
Signed-off-by: Addy
In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
in one chunk, so the size of data to be write/read to/from TXDATAx/RXDATAx
must be less than or equal 32 bytes at a time.
Tested on rk3288-pinky board, elan receive 158 bytes data.
Acked-by: Max Schwarz
Signed-off-by: Addy
In rk3x SOC, the I2C controller can receive/transmit up to 32 bytes data
in one transaction, so the size of data to be write/read to/from
TXDATAx/RXDATAx must be less than or equal 32 bytes at a time.
Test on pinky board, elan receive 158 bytes data.
Signed-off-by: Addy Ke
---
drivers/i2c
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index cb8fd6f..4ef3fd3 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -679,7 +679,7
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Reviewed-by: Doug Anderson
Signed-off-by: Addy Ke
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Signed-off-by: Addy Ke
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
- add "cd" and &q
To support HS200 and UHS-1, we need add a big hunk of code,
as shown in the following patches. So a separate file for
rockchip SOCs is suitable.
Signed-off-by: Addy Ke
---
Changes in v2:
- Kconfig: depend on ARCH_ROCKCHIP, suggested by Bartlomiej Zolnierkiewicz
- Kconfig: depend on OF, suggested
This patch requires that <https://patchwork.kernel.org/patch/4701721/>
land in order to compile.
Signed-off-by: Addy Ke
---
Changes in v2:
- repost patch to match what's in Heiko's "wip/v3.18-next/dts" tree
for the other dwmmc controllers
- add "cd" and &q
To support HS200 and UHS-1, we need add a big hunk of code,
as shown in the following patches. So a separate file for
rockchip SOCs is suitable.
Signed-off-by: Addy Ke
---
drivers/mmc/host/Kconfig | 9 +++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/dw_mmc-pltfm.c
Signed-off-by: Addy Ke
---
arch/arm/boot/dts/rk3288.dtsi | 76 +++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 7a9173d..a440869 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm
> Addy,
>
> On Wed, Aug 13, 2014 at 6:57 PM, Addy wrote:
>
>> I think maybe it is suitable as follows:
>> mmc0 = &sdmmc
>> mmc1 = &sdio0
>> mmc2 = &sdio1
>> mmc3 = &emmc
>
> Right, except the only ones that have landed in Heiko's tree are sdmmc
> and emmc, so we can't do sdio0 and sdio1 yet. Y
erson
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 72fb287..1e3bcfa 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -511,8 +
If slave holds scl, I2C_IPD[7] will be set 1 by controller
for debugging. Driver must ignore it.
[5.752391] rk3x-i2c ff16.i2c: unexpected irq in WRITE: 0x80
[5.939027] rk3x-i2c ff16.i2c: timeout, ipd: 0x80, state: 4
Signed-off-by: Addy Ke
---
drivers/i2c/busses/i2c-rk3x.c | 2
This patch focuses on clock setting for RK3288 mmc controller.
In RK3288 mmc controller, CLKDIV register can only be set 0 or 1,
and if DDR 8bit mode, CLKDIV register must be set 1.
Reported-by Doug Anderson
Suggested-by: Jaehoon Chung
Suggested-by: Doug Anderson
Signed-off-by: Addy Ke
From: Addy Ke
Suggested-by: Mark Brown
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index a8866c9..cb8fd6f 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi
From: Addy Ke
Suggested-by: Jonas Gorski
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 09c690c..a8866c9 100644
--- a/drivers/spi/spi-rockchip.c
+++ b
From: Addy Ke
Suggested-by: Mark Brown
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 41 +++--
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 72fb287..8c24708 100644
From: Addy Ke
Suggested-by: Mark Brown
Signed-off-by: Addy Ke
---
drivers/spi/spi-rockchip.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 8c24708..09c690c 100644
--- a/drivers/spi
From: Addy Ke
These patches based on:
- git: kernel/git/broonie/spi.git
- branch: topic/rockchip
- commit: c15369087ae5c7db7f3e3604822eac6ab87429bd
Addy Ke (4):
spi/rockchip: cleanup some coding issues and uncessary output
spi/rockchip: call wait_for_idle() for the transfer to complete
This patch focuses on clock setting for RK3288 mmc controller.
In RK3288 mmc controller, CLKDIV register can only be set 0 or 1,
and if DDR 8bit mode, CLKDIV register must be set 1.
Signed-off-by: Addy Ke
---
changes since v1:
- dw_mci_rk3288_setup_clock: do not call clk_get_rate(), just use
1 - 100 of 109 matches
Mail list logo
