On 4/27/2020 8:41 PM, Abhishek Sahu wrote:
> On 4/21/2020 11:18 AM, Abhishek Sahu wrote:
>> On 4/20/2020 10:14 PM, Logan Gunthorpe wrote:
>>> On 2020-04-20 2:22 a.m., Abhishek Sahu wrote:
>>>> commit 30796e18c299 ("x86/mm: introduce __set_memory_prot()")
&
On 6/14/2019 2:27 AM, Bjorn Helgaas wrote:
> On Thu, Jun 06, 2019 at 02:52:23PM +0530, Abhishek Sahu wrote:
>> * v2:
>>
>> 1. Make the pci device link helper function generic which can be
>>used for other multi-function PCI devices also.
>> 2. Minor ch
0 state if any other function is in D0
state.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Minor changes in commit log
2. used pci_create_device_link() helper function
drivers/pci/quirks.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/pci/qu
link from one
function to another function.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Make the helper function generic which takes supplier class,
class shift and function number also.
2. Minor changes in commit log
drivers/pci/quirks.c
/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf
[2] https://en.wikipedia.org/wiki/VirtualLink
Abhishek Sahu (2):
PCI: Code reorganization for creating device link
PCI: Create device link for NVIDIA GPU
drivers/pci/quirks.c | 79
On 6/3/2019 10:52 PM, Bjorn Helgaas wrote:
> [+cc Rafael, just FYI]
>
> On Mon, Jun 03, 2019 at 01:30:51PM +0530, Abhishek Sahu wrote:
>> On 6/1/2019 2:09 AM, Bjorn Helgaas wrote:
>>> On Fri, May 31, 2019 at 10:31:09AM +0530, Abhishek Sahu wrote:
>>>>
On 6/3/2019 10:45 PM, Bjorn Helgaas wrote:
> [+cc Lukas]
>
> On Fri, May 31, 2019 at 10:31:08AM +0530, Abhishek Sahu wrote:
>> This patch does minor code reorganization. It introduces a helper
>> function which creates device link from the non-VGA controller
>> (con
Thanks Bjorn for your review.
On 6/1/2019 2:09 AM, Bjorn Helgaas wrote:
> [+cc Lukas, author of 07f4f97d7b4b ("vga_switcheroo: Use device link
> for HDA controller")]
>
> On Fri, May 31, 2019 at 10:31:09AM +0530, Abhishek Sahu wrote:
>> NVIDIA Turing GPUs include har
require a similar kind of device
link from USB/Type-C USCI controller to VGA.
Signed-off-by: Abhishek Sahu
---
drivers/pci/quirks.c | 44 +---
1 file changed, 29 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index
runtime PM active if other functions
are still active.
Signed-off-by: Abhishek Sahu
---
drivers/pci/quirks.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index a20f7771a323..afdbc199efc5 100644
--- a/drivers/pci/quirks
link between function 0 and
functions 2 and 3.
[1]
https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf
[2] https://en.wikipedia.org/wiki/VirtualLink
Abhishek Sahu (2):
PCI: Code reorganization for VGA
On 2018-11-04 21:26, Boris Brezillon wrote:
Hi Abhishek,
On Fri, 20 Jul 2018 15:03:48 +0200
Boris Brezillon wrote:
On Fri, 20 Jul 2018 17:46:38 +0530
Abhishek Sahu wrote:
> Hi Boris,
>
> On 2018-07-19 03:13, Boris Brezillon wrote:
> > On Wed, 18 Jul 2018 23:23:50 +0200
&g
On 2018-07-19 03:24, Boris Brezillon wrote:
On Fri, 6 Jul 2018 13:21:59 +0530
Abhishek Sahu wrote:
Driver does not send the commands to NAND device for page
read/write operations in ->cmdfunc(). It just does some
minor variable initialization and rest of the things
are being done in act
hanks,
Miquèl
Abhishek Sahu wrote on Fri, 6 Jul 2018
13:21:56 +0530:
> The NAND base layer calls write_oob() by setting bytes at
> chip->badblockpos with value non 0xFF for updating bad block status.
> The QCOM NAND controller skips the bad block bytes while doing normal
> wr
On 2018-07-19 03:12, Miquel Raynal wrote:
Abhishek,
Miquel Raynal wrote on Wed, 18 Jul 2018
23:41:44 +0200:
Hi Boris,
Boris Brezillon wrote on Wed, 18 Jul
2018
23:36:37 +0200:
> On Wed, 18 Jul 2018 23:15:26 +0200
> Miquel Raynal wrote:
>
> > Hi Abhishek,
> >
> &
QCOM IPQ8074 boards contain NAND flash memory for which
this config needs to be enabled.
Signed-off-by: Abhishek Sahu
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6739fc7..339f3dd 100644
IPQ8064 and IPQ4019 boards contain NAND flash
memory for which these configs need to be enabled.
Signed-off-by: Abhishek Sahu
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index dd2a089
://patchwork.ozlabs.org/patch/920563/
[3]: https://patchwork.ozlabs.org/patch/938631/
Abhishek Sahu (5):
mtd: rawnand: qcom: remove driver specific bad block check function
mtd: rawnand: qcom: remove driver specific block_markbad function
mtd: rawnand: qcom: fix NAND register write errors
mtd: rawnand: qcom
registers should always be done through
command descriptors if BAM_MODE is already enabled.
With full boot chain, bootloader already enables
BAM_MODE so read the NAND_CTRL register value and write
only if BAM_MODE is not set.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/raw
in OOB and accordingly do raw write for updating
BBM bytes in NAND flash or normal write for updating available OOB
bytes.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/raw/qcom_nandc.c | 103 +++---
1 file changed, 40 insertions(+), 63 deletions(-)
diff --gi
Remove the NAND_SKIP_BBTSCAN to use RAM based BBT.
Flash based BBT is not used since bootloaders
doesn't have support for the same.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/raw/qcom_nandc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mtd/nan
y, driver
is storing this status privately and returns the same when status
command comes from helper function after program/erase operation.
Now, for write operations, the status can be returned from main
function itself, so storing status can be removed for program
operat
and return probe
failure for all these chips.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/raw/qcom_nandc.c | 118 ++
1 file changed, 31 insertions(+), 87 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
in
h CW, check the number of 0 in cw_data and usable
oob bytes, The bbm and spare (unused) bytes bit flip won’t
affect the ECC so don’t check the number of bitflips in this area.
Signed-off-by: Abhishek Sahu
---
* Changes from v4:
1. Used for_each_set_bit for determining CW’s whic
On 2018-07-01 23:39, Miquel Raynal wrote:
Hi Abhishek,
Abhishek Sahu wrote on Wed, 20 Jun 2018
12:57:27 +0530:
* v4:
1. Added patch to make other ECC configurations function static.
2. Clubbed the DT update patches.
3. Removed the bad block related patch. Discussion is going on
related
: Abhishek Sahu
On 2018-06-18 17:05, Miquel Raynal wrote:
Hi Abhishek,
Boris, one question for you below :)
>> >> >> So for last CW, the 464 is BBM (i.e 2048th byte) in
>> >> full page.
>> >> >> > >> >> clear_bam_transaction(nandc);
>> >> >> -ret = copy_last_cw(host, page);
>> >> >> -if (ret
/EBADMSG depending upon number of
bitflips and position.
c. Introduce failure condition for operational failure and
check if it detects the same.
[1]: https://patchwork.ozlabs.org/patch/328994/
[2]: https://patchwork.ozlabs.org/patch/509970/
Abhishek Sahu (15):
mtd: rawnand: helper
completed all its DMA
descriptors. It assigns completion callback in last
DMA descriptors of that channel and wait for completion.
Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor
formation")
Cc: sta...@vger.kernel.org
Acked-by: Miquel Raynal
Signed-off-by: Abh
n writes the codeword back.
The reading codeword is unnecessary since user is responsible to
have these bytes cleared to 0xFF.
This patch removes the read part and updates the OOB bytes with
data area padded with OxFF.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3
page read
is used for debug purpose so it won't affect normal flash
operations.
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Major code changes for making separate function for raw_read
2. Changed commit message
* Changes from v2:
NONE
* Changes from v1:
1. Included more d
Currently the driver uses the ECC strength specified in DT.
The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same
kind of board can have different NAND parts so use the ECC
strength from device parameters if it is not specified in DT.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek
in DT. This DT property
can be removed and ecc step size can be assigned in driver with
512 bytes value.
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Clubbed following 2 patches into one
https://patchwork.ozlabs.org/patch/920465/
https://patchwork.ozlabs.org/patch/920467
igned-off-by: Abhishek Sahu
---
Changes from v3:
NEW PATCH
drivers/mtd/nand/raw/nand_base.c | 39 +++
include/linux/mtd/rawnand.h | 9 -
2 files changed, 15 insertions(+), 33 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/
Use the NAND core helper function nand_ecc_choose_conf to tune
the ECC parameters instead of the function locally defined.
Acked-by: Miquel Raynal
Acked-by: Masahiro Yamada
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
NONE
* Changes from v2:
1. Changed commit message
* Changes
: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
NONE
* Changes from v2:
NONE
* Changes from v1:
1. Added more detail in commit message
2. Added comment before each if/else
drivers/mtd/nand/raw/qcom_nandc.c | 18 +++---
1 file changed, 15 insertions(+), 3
also (like TIMEOUT, MPU
errors, etc.), the erased CW detect logic is being applied so fix this
and return EIO for other operational errors.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
NONE
* Changes from v2:
1. Changed commit message slightly
* Changes from v1
function which calls the
required helper functions for the above logic. The drivers can use
this single function instead of calling the 3 helper functions
individually.
CC: Masahiro Yamada
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. call nand_maximize_ecc() 2 times to make code more cl
errors.
Reviewed-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
NONE
* Changes from v2:
NONE
* Changes from v1:
1. Minor code change for return early in case of error
drivers/mtd/nand/raw/qcom_nandc.c | 26 +-
1 file changed, 9 insertions
Currently there is no error checking for raw read. For raw
reads, there won’t be any ECC failure but the operational
failures are possible, so schedule the NAND_FLASH_STATUS read
after each codeword.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Since bad block
Fix value returned by ->read_page_raw() to be the
actual operation status, instead of always 0.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
NONE
* Changes from v2:
1. Changed commit message
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nand
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Minor change in comment
(s
h CW, check the number of 0 in cw_data and usable
oob bytes, The bbm and spare (unused) bytes bit flip won’t
affect the ECC so don’t check the number of bitflips in this area.
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Major changes in erased codeword detection for
raw re
as BAD.
Fixes: c120e75e0e7d ("mtd: nand: use read_oob() instead of cmdfunc() for bad
block check")
Cc:
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/raw/nand_base.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mt
On 2018-06-07 18:23, Miquel Raynal wrote:
Hi Abhishek,
On Mon, 28 May 2018 15:40:52 +0530, Abhishek Sahu
wrote:
On 2018-05-28 12:33, Miquel Raynal wrote:
> Hi Abhishek,
> >> >> /* implements ecc->read_page() */
>> >> static int qcom_nandc_read_
On 2018-06-07 18:13, Miquel Raynal wrote:
Hi Abhishek,
On Mon, 28 May 2018 13:04:45 +0530, Abhishek Sahu
wrote:
On 2018-05-27 19:23, Miquel Raynal wrote:
> Hi Abhishek,
> > On Fri, 25 May 2018 17:51:43 +0530, Abhishek Sahu
> wrote:
> >> This patch does minor code r
On 2018-06-07 18:07, Miquel Raynal wrote:
Hi Abhishek,
On Mon, 28 May 2018 11:16:29 +0530, Abhishek Sahu
wrote:
On 2018-05-26 14:12, Miquel Raynal wrote:
> Hi Abhishek,
> > On Fri, 25 May 2018 17:51:29 +0530, Abhishek Sahu
> wrote:
> >> commit 2c8f8afa7f92 ("mtd:
On 2018-05-30 13:08, Masahiro Yamada wrote:
2018-05-30 15:21 GMT+09:00 Abhishek Sahu :
On 2018-05-30 05:58, Masahiro Yamada wrote:
Hi.
2018-05-30 4:30 GMT+09:00 Boris Brezillon
:
On Sat, 26 May 2018 10:42:47 +0200
Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:29 +0530
On 2018-05-30 05:58, Masahiro Yamada wrote:
Hi.
2018-05-30 4:30 GMT+09:00 Boris Brezillon
:
On Sat, 26 May 2018 10:42:47 +0200
Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:29 +0530, Abhishek Sahu
wrote:
> commit 2c8f8afa7f92 ("mtd: nand: add generic helpers
On 2018-05-28 12:33, Miquel Raynal wrote:
Hi Abhishek,
>> /* implements ecc->read_page() */
>> static int qcom_nandc_read_page(struct mtd_info *mtd, struct >> nand_chip
*chip,
>>uint8_t *buf, int oob_required, int page)
>> @@ -2118,6 +2083,7 @@ static int qcom
On 2018-05-27 19:23, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:43 +0530, Abhishek Sahu
wrote:
This patch does minor code reorganization for raw reads.
Currently the raw read is required for complete page but for
subsequent patches related with erased codeword bit flips
On 2018-05-26 14:28, Miquel Raynal wrote:
Hi Abhishek,
@@ -2141,12 +2127,10 @@ static int qcom_nandc_block_bad(struct
mtd_info *mtd, loff_t ofs)
goto err;
}
- bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);
-
- bad = nandc->data_buffer[bbpos] !=
On 2018-05-26 14:16, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:41 +0530, Abhishek Sahu
wrote:
The QCOM NAND controller layout is such that, the bad block byte
offset for last codeword will come to first byte in spare area.
"is the first spare byte"?
Currentl
On 2018-05-26 14:13, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:34 +0530, Abhishek Sahu
wrote:
Currently the driver uses the ECC strength specified in DT.
The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same
kind of board can have different NAND parts so use the
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:33 +0530, Abhishek Sahu
wrote:
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:31 +0530, Abhishek Sahu
wrote:
If nand-ecc-strength specified in DT, then controller will use
this ECC strength otherwise ECC strength will be calculated
according to chip requirement and available OOB size
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:29 +0530, Abhishek Sahu
wrote:
commit 2c8f8afa7f92 ("mtd: nand: add generic helpers to check,
match, maximize ECC settings") provides generic helpers which
drivers can use for setting up ECC paramete
QCOM NAND controller supports only one step size (512) but
nand-ecc-step-size is required property in DT. This DT property
can be removed and ecc step size can be assigned in driver with
512 value.
Signed-off-by: Abhishek Sahu
---
Currently there is no user in mainline linux kernel for
QPIC
completed all its DMA
descriptors. It assigns completion callback in last
DMA descriptors of that channel and wait for completion.
Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor
formation")
Cc: sta...@vger.kernel.org
Signed-off-by: Abhishek Sahu
---
* Changes fr
errors.
Reviewed-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Minor code change for return early in case of error
drivers/mtd/nand/raw/qcom_nandc.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git
Fix value returned by ->read_page_raw() to be the
actual operation status, instead of always 0.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
this, copy_last_cw function won’t be required.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message and comments slightly
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nandc.c | 66 +++
1 file changed, 25 insertions
specifies which CW reads are required in complete page.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Included more detail in function comment
drivers/mtd/nand/raw/qcom_nandc.c | 197 --
1 file changed, 123 insertions(+), 74
number of 0 in cw_data and usable
oob bytes, The bbm and spare (unused) bytes bit flip won’t
affect the ECC so don’t check the number of bitflips in this area.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Minor change in commit message
2. invalidate p
Currently there is no error checking for raw read. For raw
reads, there won’t be any ECC failure but the operational
failures are possible, so schedule the NAND_FLASH_STATUS read
after each codeword.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Removed the
n writes the codeword back.
The reading codeword is unnecessary since user is responsible to
have these bytes cleared to 0xFF.
This patch removes the read part and updates the OOB bytes with
data area padded with OxFF.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from
: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Added more detail in commit message
2. Added comment before each if/else
drivers/mtd/nand/raw/qcom_nandc.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a
Currently the driver uses the ECC strength specified in DT.
The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same
kind of board can have different NAND parts so use the ECC
strength from device parameters if it is not specified in DT.
Signed-off-by: Abhishek Sahu
---
* Changes from v2
If nand-ecc-strength specified in DT, then controller will use
this ECC strength otherwise ECC strength will be calculated
according to chip requirement and available OOB size.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
NEW PATCH
Documentation/devicetree
also (like TIMEOUT, MPU
errors, etc.), the erased CW detect logic is being applied so fix this
and return EIO for other operational errors.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message slightly
* Changes from v1:
1. Added more detail in
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NEW CHANGE
1. Removed the custom logic and used the
it detects the same.
[1]: https://patchwork.ozlabs.org/patch/328994/
[2]: https://patchwork.ozlabs.org/patch/509970/
Abhishek Sahu (16):
mtd: rawnand: helper function for setting up ECC configuration
mtd: rawnand: denali: use helper function for ecc setup
dt-bindings: qcom_nandc: make nand
function which calls the
required helper functions for the above logic. The drivers can use
this single function instead of calling the 3 helper functions
individually.
CC: Masahiro Yamada
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Renamed function to nand_ecc_choose_conf.
2. Minor
Use the NAND core helper function nand_ecc_choose_conf to tune
the ECC parameters instead of the function locally defined.
CC: Masahiro Yamada
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message
* Changes from v1:
NEW PATCH
drivers/mtd
On 2018-05-22 17:34, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 3 May 2018 17:50:37 +0530, Abhishek Sahu
wrote:
Currently zero is being returned for all raw page read so
fix the same.
What about "Fix value returned by ->read_page_raw() to be the
actual operation status, instead of
On 2018-05-22 15:32, Miquel Raynal wrote:
Hi Abhishek,
Some nitpicking below.
On Thu, 3 May 2018 17:50:36 +0530, Abhishek Sahu
wrote:
QCOM NAND layout protect available OOB data bytes with ECC also so
^controller
when ecc->write_oob (qcom_nandc_write_oob) is being cal
On 2018-05-22 12:46, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 3 May 2018 17:50:34 +0530, Abhishek Sahu
wrote:
parse_read_errors can be called with only oob_buf in which case
data_buf will be NULL. If data_buf is NULL, then don’t
treat this page as completely erased in case of ECC
On 2018-05-22 12:34, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 3 May 2018 17:50:33 +0530, Abhishek Sahu
wrote:
Following is the flow in the HW if controller tries to read erased
page
Nit: ^ missing ':'
Sure. I will fix this.
1. First ECC uncorrectable error will be gene
On 2018-05-21 20:00, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 3 May 2018 17:50:29 +0530, Abhishek Sahu
wrote:
Now, the NAND base layer has helper function for ecc
parameters setup which does the same thing.
Even if this message has a meaning in the series, I would prefer
something more
On 2018-05-21 20:02, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 3 May 2018 17:50:30 +0530, Abhishek Sahu
wrote:
Now, nand-ecc-strength is optional. If specified in DT, then
controller will use this ECC strength otherwise ECC strength will
be calculated according to chip requirement and
On 2018-05-22 12:17, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 3 May 2018 17:50:32 +0530, Abhishek Sahu
wrote:
The BAM has 3 channels - tx, rx and command. command channel
is used for register read/writes, tx channel for data writes
and rx channel for data reads. Currently, the driver
On 2018-05-07 13:58, Boris Brezillon wrote:
On Thu, 3 May 2018 17:50:31 +0530
Abhishek Sahu wrote:
Currently the driver uses the ECC strength specified in DT.
The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same
kind of board can have different NAND parts so use the ECC
strength
On 2018-05-07 13:46, Boris Brezillon wrote:
On Thu, 3 May 2018 17:50:28 +0530
Abhishek Sahu wrote:
commit 2c8f8afa7f92 ("mtd: nand: add generic helpers to check,
match, maximize ECC settings") provides generic helpers which
drivers can use for setting up ECC parameters.
Since same
On 2018-05-08 11:44, Masahiro Yamada wrote:
2018-05-07 16:39 GMT+09:00 Boris Brezillon
:
On Mon, 7 May 2018 12:40:39 +0900
Masahiro Yamada wrote:
2018-05-03 21:20 GMT+09:00 Abhishek Sahu :
> commit 2c8f8afa7f92 ("mtd: nand: add generic helpers to check,
> match, maximize E
On 2018-05-07 09:10, Masahiro Yamada wrote:
2018-05-03 21:20 GMT+09:00 Abhishek Sahu :
commit 2c8f8afa7f92 ("mtd: nand: add generic helpers to check,
match, maximize ECC settings") provides generic helpers which
drivers can use for setting up ECC parameters.
Since same board can have
Now, nand-ecc-strength is optional. If specified in DT, then
controller will use this ECC strength otherwise ECC strength will
be calculated according to chip requirement and available OOB size.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NEW PATCH
Documentation/devicetree/bindings
will generate the callback
when all the descriptors have completed in that channel.
The NAND transfer will be completed only when all required
DMA channels have generated the completion callback.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NONE
1. Removed the custom logic and used the h
errors.
Signed-off-by: Abhishek Sahu
Reviewed-by: Miquel Raynal
---
* Changes from v1:
1. Minor code change for return early in case of error
drivers/mtd/nand/raw/qcom_nandc.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/mtd/nand
Currently zero is being returned for all raw page read so
fix the same.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand
en again writes the codeword back.
The reading codeword is unnecessary since all the other bytes
should be 0xff only.
This patch removes the read part and updates the oob bytes with
all other data bytes as 0xff.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NEW CHANGE
drivers/mtd/
this, copy_last_cw function won’t be required.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nandc.c | 66 +++
1 file changed, 25 insertions(+), 41 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b
specifies which CW reads are required in complete page.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Included more detail in function comment
drivers/mtd/nand/raw/qcom_nandc.c | 197 --
1 file changed, 123 insertions(+), 74 deletions(-)
diff --git a
Currently there is no error checking for raw read. For raw
reads, there won’t be any ECC failure but the operational
failures are possible so schedule the NAND_FLASH_STATUS read
after each codeword.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Removed the code for copy_last_cw
number of 0 in cw_data and usable
oob bytes, The bbm and spare (unused) bytes bit flip won’t
affect the ECC so don’t check the number of bitflips in this area.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Minor change in commit message
2. invalidate pagebuf if databuf or oob_
-by: Abhishek Sahu
---
* Changes from v1:
1. Added more detail in commit message
2. Added comment before each if/else
drivers/mtd/nand/raw/qcom_nandc.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd
Now, the NAND base layer has helper function for ecc
parameters setup which does the same thing.
CC: Masahiro Yamada
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NEW PATCH
drivers/mtd/nand/raw/denali.c | 30 ++
1 file changed, 2 insertions(+), 28
also (like TIMEOUT, MPU
errors, etc.), the erased CW detect logic is being applied so fix this
and return EIO for other operational errors.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Added more detail in commit message
2. Added comment before each if/else
3. Removed redundant check
failure condition for operational failure and
check if it detects the same.
[1]: https://patchwork.ozlabs.org/patch/328994/
[2]: https://patchwork.ozlabs.org/patch/509970/
Abhishek Sahu (14):
mtd: rawnand: helper function for setting up ECC parameters
mtd: rawnand: denali: use helper
Currently the driver uses the ECC strength specified in DT.
The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same
kind of board can have different NAND parts so use the ECC
strength from device parameters if it is not specified in DT.
Signed-off-by: Abhishek Sahu
---
* Changes from v1
param_setup function which calls the
required helper functions for the above logic. The drivers can use
this single function instead of calling the 3 helper functions
individually.
CC: Masahiro Yamada
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NEW PATCH
drivers/mtd/nand/
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