[PATCH v2] sdhci-esdhc-imx: Correct two register accesses

the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell Signed-off-by: Aaron Brice Acked-by: Dong Aisheng --- v1 -> v2: - rename long_val to val drivers/mmc/host/sdhci-esdhc-imx.c |

[PATCH] sdhci-esdhc-imx: Correct two register accesses

the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell Signed-off-by: Aaron Brice --- drivers/mmc/host/sdhci-esdhc-imx.c | 23 ++- 1 file changed, 22 insertions(+), 1

[PATCH] tty: serial: fsl_lpuart: Fix Tx DMA edge case

In the case where head == 0 on the circular buffer, there should be one DMA buffer, not two. The second zero-length buffer would break the lpuart driver, transfer would never complete. Signed-off-by: Aaron Brice --- drivers/tty/serial/fsl_lpuart.c | 3 +-- 1 file changed, 1 insertion(+), 2

[PATCH v3 3/3] spi: fsl-dspi: Add ~50ns delay between cs and sck

Add delay between chip select and clock signals, before clock starts and after clock stops. Signed-off-by: Aaron Brice --- drivers/spi/spi-fsl-dspi.c | 64 +++--- 1 file changed, 60 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b

[PATCH v3 1/3] spi: fsl-dspi: Fix clock rate scale values

possible without going over the desired clock rate. Signed-off-by: Aaron Brice --- drivers/spi/spi-fsl-dspi.c | 37 +++-- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index d1a3924..8213358 100644

[PATCH v3 2/3] devicetree: spi: fsl-dspi: Add cs-sck delays

Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to support delays before and after starting the clock in a transfer. Signed-off-by: Aaron Brice --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 8 1 file changed, 8 insertions(+) diff --git a/Documentation

[PATCH v3 0/3] spi: fsl-dspi (vf610) clock fixes

-coded 50ns delays to device tree properties * Fix for baud rate scale value remainders, reported by Andy Shevchenko Changes since v1: * More detail in commit message for clock rate fix Aaron Brice (3): spi: fsl-dspi: Fix clock rate scale values devicetree: spi: fsl-dspi: Add cs-sck delays

Re: [PATCH v2 2/2] spi: fsl-dspi: Add ~50ns delay between cs and sck

On 03/30/2015 03:13 PM, Stefan Agner wrote: Hi Aaron, Thanks for the fixes! Some comments below: Thanks for the review! On 2015-03-30 19:49, Aaron Brice wrote: Add delay between chip select and clock signals, before clock starts and after clock stops. This 50ns are specifc to the SPI

[PATCH v2 1/2] spi: fsl-dspi: Fix clock rate scale values

possible without going over the desired clock rate. Signed-off-by: Aaron Brice --- drivers/spi/spi-fsl-dspi.c | 35 +-- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index d1a3924..96cac87 100644

[PATCH v2 2/2] spi: fsl-dspi: Add ~50ns delay between cs and sck

Add delay between chip select and clock signals, before clock starts and after clock stops. Signed-off-by: Aaron Brice --- drivers/spi/spi-fsl-dspi.c | 53 -- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b

[PATCH v2 0/2] spi: fsl-dspi (vf610) clock fixes

We were having intermittent problems writing to SRAM chip on SPI bus on vf610 SoM. Added support for CS setup and hold times to meet the SRAM spec. In the process noticed that the baud rate was a little high. Changes since v1: * More detail in commit message for clock rate fix Aaron Brice (2

[PATCH 1/2] spi: fsl-dspi: Fix clock rate scale values

Update baud rate scaling algorithm to get better scaling values. Signed-off-by: Aaron Brice --- drivers/spi/spi-fsl-dspi.c | 35 +-- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index

[PATCH 2/2] spi: fsl-dspi: Add ~50ns delay between cs and sck

Add delay between chip select and clock signals, before clock starts and after clock stops. Signed-off-by: Aaron Brice --- drivers/spi/spi-fsl-dspi.c | 53 -- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b

[PATCH 0/2] spi: fsl-dspi (vf610) clock fixes

We were having intermittent problems writing to SRAM chip on SPI bus on vf610 SoM. Added support for CS setup and hold times to meet the SRAM spec. In the process noticed that the baud rate was a little high. Aaron Brice (2): spi: fsl-dspi: Fix clock rate scale values spi: fsl-dspi: Add

Re: [PATCH 3/7] spi: spi-fsl-dspi: Remove usage of devm_kzalloc

On 01/27/2015 03:57 AM, Bhuvanchandra DV wrote: devm_* API was supposed to be used only in probe function call. Memory is allocated at 'probe' and free automatically at 'remove'. Usage of devm_* functions outside probe sometimes leads to memory leak. Avoid using devm_kzalloc in dspi_setup_transfe