On 2024/2/19 下午3:16, Huacai Chen wrote:
On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
On 2024/2/19 上午10:45, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
register access on ipi sendi
On Sun, Feb 18, 2024 at 09:06:18PM -0800, syzbot wrote:
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:d37e1e4c52bc Add linux-next specific files for 20240216
> git tree: linux-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=171ca65218
> kernel co
On 18/02/2024 16:10, Karel Balej wrote:
> Rob Herring, 2024-02-15T08:20:52-06:00:
>>> .../bindings/mfd/marvell,88pm88x.yaml | 74 +++
>>
>> Filename should match the compatible.
>>
>> In general, drop the 'x' wildcard.
>
> By "in general", do you mean for the drivers code a
On 18/02/2024 21:57, Luca Weiss wrote:
> Follow the updated bindings and use a QCS404-specific compatible for the
> HFPLL on this SoC.
>
> Signed-off-by: Luca Weiss
> ---
> Please note that this patch should only land after the patch for the
> clock driver.
> ---
This patch should go in the next
On 18/02/2024 21:57, Luca Weiss wrote:
> Convert the .txt documentation to .yaml with some adjustments.
>
> * APQ8064/IPQ8064/MSM8960 compatibles are dropped since their HFPLLs are
> a part of GCC so there is no need for a separate compat entry.
> * Change the MSM8974 compatible to follow the up
On Mon, Feb 19, 2024 at 12:18 PM maobibo wrote:
>
>
>
> On 2024/2/19 上午10:45, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
> >>
> >> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> >> register access on ipi sending, and two iocsr
Hello,
syzbot found the following issue on:
HEAD commit:d37e1e4c52bc Add linux-next specific files for 20240216
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=171ca65218
kernel config: https://syzkaller.appspot.com/x/.config?x=4bc446d42a7d56c0
dashbo
On 2024/2/19 上午10:45, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
register access on ipi sending, and two iocsr access on ipi receiving
which is ipi interrupt handler. On VM mode all iocsr
On 2024/2/19 上午10:42, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
The patch adds paravirt interface for guest kernel, function
pv_guest_initi() firstly checks whether system runs on VM mode. If kernel
runs on VM mode, it will call function kvm_para_availabl
On 2024/2/19 上午10:41, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
On LoongArch system, hypercall instruction is supported when system
runs on VM mode. This patch adds dummy function with hypercall
instruction emulation, rather than inject EXCCODE_INE invalid
Huacai,
Thanks for your reviewing, I reply inline.
On 2024/2/19 上午10:39, Huacai Chen wrote:
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
This patch refines ipi handling on LoongArch platform, there are
three changes with this patch.
1. Add generic get_percpu_irq() api, replace
>> +
>> +/**
>> + * vfio_pci_core_range_intersect_range() - Determine overlap between a
>> buffer
>> + * and register offset ranges.
>> + * @buf_start: start offset of the buffer
>> + * @buf_cnt: number of buffer bytes.
>
> You could drop
Thanks Kevin and Yishai for the reviews. Comments inline.
>> +static int nvgrace_gpu_mmap(struct vfio_device *core_vdev,
>> + struct vm_area_struct *vma)
>> +{
>> + struct nvgrace_gpu_pci_core_device *nvdev =
>> + container_of(core_vdev, struct nvgrace_gpu_p
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:20 AM Bibo Mao wrote:
>
> On LoongArch system, ipi hw uses iocsr registers, there is one iocsr
> register access on ipi sending, and two iocsr access on ipi receiving
> which is ipi interrupt handler. On VM mode all iocsr registers
> accessing will cause VM to
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> The patch adds paravirt interface for guest kernel, function
> pv_guest_initi() firstly checks whether system runs on VM mode. If kernel
> runs on VM mode, it will call function kvm_para_available() to detect
> whether current VMM is K
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> On LoongArch system, hypercall instruction is supported when system
> runs on VM mode. This patch adds dummy function with hypercall
> instruction emulation, rather than inject EXCCODE_INE invalid
> instruction exception.
>
> Signed-of
Hi, Bibo,
On Thu, Feb 1, 2024 at 11:19 AM Bibo Mao wrote:
>
> This patch refines ipi handling on LoongArch platform, there are
> three changes with this patch.
> 1. Add generic get_percpu_irq() api, replace some percpu irq functions
> such as get_ipi_irq()/get_pmc_irq()/get_timer_irq() with get_p
QE tested this patch's V2, qemu no longer print error messages
"qemu-system-x86_64: Insufficient written data (0)" after
enable/disable multi queues multi times inside guest. Both "x-svq=on
'' and without it are all test pass.
Tested-by: Lei Yang
On Fri, Feb 16, 2024 at 10:25 PM Jonah Palmer wr
On Sun, 18 Feb 2024 at 22:58, Luca Weiss wrote:
>
> Follow the updated bindings and use a QCS404-specific compatible for the
> HFPLL on this SoC.
>
> Signed-off-by: Luca Weiss
> ---
> Please note that this patch should only land after the patch for the
> clock driver.
> ---
> arch/arm64/boot/dts
On Sat, 17 Feb 2024 16:18:10 +0800 Changbin Du wrote:
> The synchronization here is just to ensure the module init's been freed
> before doing W+X checking. But the commit 1a7b7d922081 ("modules: Use
> vmalloc special flag") moves do_free_init() into a global workqueue
> instead of call_rcu(). So
It doesn't appear that the configuration is for the HFPLL is generic, so
add a qcs404-specific compatible and rename the existing struct to
qcs404.
Keep qcom,hfpll in the driver for compatibility with old dtbs.
Signed-off-by: Luca Weiss
---
drivers/clk/qcom/hfpll.c | 6 --
1 file changed, 4
Convert the .txt documentation to .yaml with some adjustments.
* APQ8064/IPQ8064/MSM8960 compatibles are dropped since their HFPLLs are
a part of GCC so there is no need for a separate compat entry.
* Change the MSM8974 compatible to follow the updated naming schema.
Theis compatible is not us
Follow the updated bindings and use a QCS404-specific compatible for the
HFPLL on this SoC.
Signed-off-by: Luca Weiss
---
Please note that this patch should only land after the patch for the
clock driver.
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Finally touch the hfpll doc and convert it to yaml, and do some related
changes along the way.
Signed-off-by: Luca Weiss
---
Changes in v2:
- Drop APQ8064/IPQ8064/MSM8960 compatibles (Dmitry)
- Update example to MSM8974 since IPQ8064 is dropped
- Clean up dt binding description (Krzysztof)
- Remo
Rob Herring, 2024-02-15T08:20:52-06:00:
> > .../bindings/mfd/marvell,88pm88x.yaml | 74 +++
>
> Filename should match the compatible.
>
> In general, drop the 'x' wildcard.
By "in general", do you mean for the drivers code also?
As I have mentioned in the commit message fo
On 16/02/2024 5:01, ank...@nvidia.com wrote:
From: Ankit Agrawal
NVIDIA's upcoming Grace Hopper Superchip provides a PCI-like device
for the on-chip GPU that is the logical OS representation of the
internal proprietary chip-to-chip cache coherent interconnect.
The device is peculiar compared t
On Wed, 2024-01-31 at 18:02 -0500, Jeff Layton wrote:
> Have both __locks_insert_block and the deadlock and conflict checking
> functions take a struct file_lock_core pointer instead of a struct
> file_lock one. Also, change posix_locks_deadlock to return bool.
>
> Signed-off-by: Jeff Layton
> --
On 16/02/2024 5:01, ank...@nvidia.com wrote:
From: Ankit Agrawal
range_intersect_range determines an overlap between two ranges. If an
overlap, the helper function returns the overlapping offset and size.
The VFIO PCI variant driver emulates the PCI config space BAR offset
registers. These off
On 16/02/2024 5:01, ank...@nvidia.com wrote:
From: Ankit Agrawal
do_io_rw() is used to read/write to the device MMIO. The grace hopper
VFIO PCI variant driver require this functionality to read/write to
its memory.
Rename this as vfio_pci_core functions and export as GPL.
Reviewed-by: Kevin T
On 2024/2/16 22:40, Krzysztof Kozlowski wrote:
Make pointer to bus_type a pointer to const for code safety.
Signed-off-by: Krzysztof Kozlowski
---
drivers/iommu/iommu-priv.h | 5 +++--
drivers/iommu/iommu.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Lu Ba
s_end(a, b) { DEV_ST_TRANSITION_##a, b }
+#define TPS(x) tracepoint_string(x)
+
TRACE_EVENT(mhi_gen_tre,
TP_PROTO(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,
---
base-commit: ceeb64f41fe6a1eb9fc56d583983a81f8f3dd058
change-id: 20240218-ftrace_string-7677762aa63c
Best regards,
--
Krishna chaitanya chundru
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