Sdw stream operation APIs can be called once per stream. Move these
operations to dailink ops. The linked series is "soundwire: Remove sdw
stream operations from Intel soundwire dai".
Reviewed-by: Vinod Koul
Changes in v3:
- s/ASOC/ASoC
Pierre-Louis Bossart (3):
ASoC: soc-dai: clarify return
From: Pierre-Louis Bossart
Add trigger functionality to dailink, so far only .startup() and
.shutdown() were implemented at the machine driver level.
The companion patch for this patch is the removal of the trigger
callback at the DAI level in drivers/soundwire/intel.c
Signed-off-by: Pierre-Lou
From: Pierre-Louis Bossart
Previous changes move to use ERR_PTR(-ENOTSUPP), but it's not clear
what implementations can return in case of errors. Explicitly document
that NULL is not a possible return value, only ERR_PTR with a negative
error code is valid.
Fixes: 308811a327c38 ('ASoC: soc-dai:
From: Pierre-Louis Bossart
Add .prepare and .hw_free callback to dailink.
The companion patch for this patch is the removal of stream operations
in the .prepare and .hw_free callbacks at the DAI level in
drivers/soundwire/intel.c
Signed-off-by: Pierre-Louis Bossart
Reviewed-by: Rander Wang
Si
On Sat, Aug 29, 2020 at 11:40:24AM +0200, Krzysztof Kozlowski wrote:
> The PCA95xx GPIO expander requires GPIO controller properties to operate
> properly.
>
> Signed-off-by: Krzysztof Kozlowski
Applied, thanks.
On Fri, Aug 28, 2020 at 06:47:40PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects pin configuration groups to end with 'grp'
> suffix, otherwise dtbs_check complain with a warning like:
>
> ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysz
In some cases, for UDP GSO, UDPv4 and UDPv6 need to be handled
separately, for example, checksum offload, so add new GSO type
SKB_GSO_UDPV6_L4 for UDPv6, and the old SKB_GSO_UDP_L4 stands
for UDPv4.
Signed-off-by: Huazhong Tan
---
drivers/net/bonding/bond_main.c | 4 +++-
There are two updates relates to UDP GSO.
#1 adds a new GSO type for UDPv6
#2 adds check for UDP GSO when csum is disable in netdev_fix_features().
Changes since RFC V2:
- modifies the timing of setting UDP GSO type when doing UDP GRO in #1.
Changes since RFC V1:
- updates NETIF_F_GSO_LAST sugges
When CSUM is not available, UDP GSO should be disable as well.
Signed-off-by: Huazhong Tan
---
net/core/dev.c | 12
1 file changed, 12 insertions(+)
diff --git a/net/core/dev.c b/net/core/dev.c
index d42c9ea..0c78306 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -9402,6 +9402
On Fri, Aug 28, 2020 at 06:47:37PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects pin configuration groups to end with 'grp'
> suffix. This fixes dtbs_check warnings like:
>
> pinctrl@3033: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz',
> 'usdhc1grp200mhz', 'usdhc1grpgpio',
On Fri, Aug 28, 2020 at 06:47:39PM +0200, Krzysztof Kozlowski wrote:
> The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent
> allows to probe the bd718x7 clock driver fixing boot errors:
>
> bd718xx-clk bd71847-clk.1.auto: No parent clk found
> bd718xx-clk: probe of bd718
Introduce tracepoints for tasklets just like softirq does. In this case,
we can calculate tasklet latency and know what tasklet run.
Signed-off-by: Muchun Song
---
include/trace/events/irq.h | 44 ++
kernel/softirq.c | 2 ++
2 files changed, 46 inse
On Fri, Aug 28, 2020 at 09:20:35PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects NAND controller to be named
> "nand-controller", otherwise dtbs_check complain with a warning like:
>
> arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dt.yaml: gpmi-nand@8000c000:
> $nodename:0:
Send your reply to: fkinney...@tampabay.rr.com
Greetings
This notification memo has been sent to you three times without a response from
you and this will be the last time and I do hope you receive it.
This inquiry is about an account holder, who died and has no successor over his
fund with the
Hi Palmer,
On Sat, Sep 5, 2020 at 9:14 AM Anup Patel wrote:
>
> On Sat, Sep 5, 2020 at 6:47 AM Palmer Dabbelt
> wrote:
> >
> > On Fri, 04 Sep 2020 09:57:09 PDT (-0700), Christoph Hellwig wrote:
> > > On Fri, Sep 04, 2020 at 10:13:18PM +0530, Anup Patel wrote:
> > >> I respectfully disagree. IMH
Lappy, which does not use bridge, boots clean... but lock leakage
pretty darn quickly inspires lockdep to craps its drawers.
[ 209.00] BUG: MAX_LOCKDEP_CHAIN_HLOCKS too low!
[ 209.001113] turning off the locking correctness validator.
[ 209.001114] CPU: 2 PID: 3773 Comm: Socket Thread Taint
[ 22.004225] r8169 :03:00.0 eth0: Link is Up - 1Gbps/Full - flow control
off
[ 22.004450] br0: port 1(eth0) entered blocking state
[ 22.004473] br0: port 1(eth0) entered forwarding state
[ 22.006411] IPv6: ADDRCONF(NETDEV_CHANGE): br0: link becomes ready
[ 22.024936] ===
On Fri, 4 Sep 2020 10:51:03 +0800 Jing Xiangfeng wrote:
> eni_init_one() misses to call pci_disable_device() in an error path.
> Jump to err_disable to fix it.
>
> Signed-off-by: Jing Xiangfeng
Please make sure you add appropriate fixes tags, here:
Fixes: ede58ef28e10 ("atm: remove deprecated u
On Fri, 2020-09-04 at 16:03 -0700, Eric Biggers wrote:
> On Fri, Sep 04, 2020 at 03:10:15PM -0700, Joe Perches wrote:
> > Reduce the object size of logging messages by removing the
> > separate KERN_LEVEL argument and adding it to the format.
> >
> > Miscellanea:
> >
> > o Rename fscypt_msg to fs
On Fri, 4 Sep 2020 18:57:27 -0700 Xie He wrote:
> On Fri, Sep 4, 2020 at 6:28 PM Xie He wrote:
> >
> > The HDLC device is not actually prepending any header when it is used
> > with this driver. When the PVC device has prepended its header and
> > handed over the skb to the HDLC device, the HDLC d
Hi all,
Today's linux-next merge of the akpm-current tree got a conflict in:
mm/filemap.c
between commit:
76cd61739fd1 ("mm/error_inject: Fix allow_error_inject function signatures.")
from the net-next tree and commit:
2cb138387ead ("mm/filemap: fix storing to a THP shadow entry")
from
On Sat, Sep 5, 2020 at 6:47 AM Palmer Dabbelt wrote:
>
> On Fri, 04 Sep 2020 09:57:09 PDT (-0700), Christoph Hellwig wrote:
> > On Fri, Sep 04, 2020 at 10:13:18PM +0530, Anup Patel wrote:
> >> I respectfully disagree. IMHO, the previous code made the RISC-V
> >> timer driver convoluted (both SBI c
There are two warnings when built with W=1:
fs/open.c:887: warning: Excess function parameter 'opened' description in
'finish_open'
fs/open.c:929: warning: Excess function parameter 'cred' description in
'vfs_open'
As there are two comments for deleted parameters, remove them.
Signed-off-by: X
On Sat, Sep 5, 2020 at 5:26 AM Arnaldo Carvalho de Melo wrote:
>
> We were failing that due to GTK2+ and then for the ZSTD test, which made
> test-all.c, the fast path feature detection file to fail and thus
> trigger building all of the feature tests, slowing down the test.
>
> Eventually the ZST
Hi,
On 9/4/20 8:45 AM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> There's some documentation for gpio-mockup's debugfs interface in the
> driver's source but it's not much. Add proper documentation for this
> testing module.
>
> Signed-off-by: Bartosz Golaszewski
> ---
> .../a
在 2020/9/4 21:26, Willem de Bruijn 写道:
On Fri, Sep 4, 2020 at 3:09 PM Wang Hai wrote:
BPDU_TYPE_TCN is never used after it was introduced.
So better to remove it.
This comment does not cover the patch contents. Otherwise the patch
looks good to me.
Thanks for your review, I will revise this
After we Stop and later Start a VM that uses Accelerated Networking (NIC
SR-IOV), currently the VF vmbus device's Instance GUID can change, so after
vmbus_bus_resume() -> vmbus_request_offers(), vmbus_onoffer() can not find
the original vmbus channel of the VF, and hence we can't complete()
vmbus_c
From: Boqun Feng Sent: Tuesday, September 1, 2020 8:01 PM
>
> Hyper-V always use 4k page size (HV_HYP_PAGE_SIZE), so when
> communicating with Hyper-V, a guest should always use HV_HYP_PAGE_SIZE
> as the unit for page related data. For storvsc, the data is
> vmbus_packet_mpb_array. And since in s
Hyper-V doesn't trap and emulate the accesses to the MSI/MSI-X registers,
and we must use hv_compose_msi_msg() to ask Hyper-V to create the IOMMU
Interrupt Remapping Table Entries. This is not an issue for a lot of
PCI device drivers (e.g. NVMe driver, Mellanox NIC drivers), which
destroy and re-cr
mlx5_suspend()/resume() keep the network interface, so during hibernation
netvsc_unregister_vf() and netvsc_register_vf() are not called, and hence
netvsc_resume() should call netvsc_vf_changed() to switch the data path
back to the VF after hibernation. Similarly, netvsc_suspend() should
not call n
> From: Dinghao Liu
> Sent: Wednesday, August 26, 2020 7:34 PM
> To: dinghao@zju.edu.cn; k...@umn.edu
> Cc: Kirsher, Jeffrey T ; David S. Miller
> ; Jakub Kicinski ; Alexei
> Starovoitov ; Daniel Borkmann ;
> Jesper Dangaard Brouer ; John Fastabend
> ; intel-wired-...@lists.osuosl.org;
> net..
config GENERIC_IOMAP is disabled on arm64, so pci_iounmap() does
nothing, when we using pci_iomap/pci_iounmap(), it will lead to
memory leak. Implements pci_iounmap() for arm64 to fix this leak.
Fixes: 09a5723983e3 ("arm64: Use include/asm-generic/io.h")
Signed-off-by: Yang Yingliang
---
arch/ar
On Fri, Sep 04, 2020 at 10:18:30PM +, Kelley, Sean V wrote:
> Hi Bjorn,
>
> Quick question below...
>
> On Wed, 2020-09-02 at 14:55 -0700, Sean V Kelley wrote:
> > Hi Bjorn,
> >
> > On Wed, 2020-09-02 at 14:00 -0500, Bjorn Helgaas wrote:
> > > On Wed, Aug 12, 2020 at 09:46:53AM -0700, Sean V
The metric_event_delete() missed to free expr->metric_events and it
should free an expr when metric_refs allocation failed.
Cc: Kajol Jain
Cc: John Garry
Cc: Ian Rogers
Fixes: 4ea2896715e67 ("perf metric: Collect referenced metrics in struct
metric_expr")
Signed-off-by: Namhyung Kim
---
tool
I found some memory leaks while reading the metric code. Some are
real and others only occur in the error path. When it failed during
metric or event parsing, it should release all resources properly.
Cc: Kajol Jain
Cc: John Garry
Cc: Ian Rogers
Fixes: b18f3e365019d ("perf stat: Support JSON
Hi all,
Commit
4c31ead75f41 ("printk: ringbuffer: support dataless records")
is missing a Signed-off-by from its committer.
--
Cheers,
Stephen Rothwell
pgp3_FYrKyMH8.pgp
Description: OpenPGP digital signature
CC_NO_CLANG should be set according to the value of CC after overridden.
I have linked /usr/bin/cc to /usr/bin/clang and I built perf with a gcc
cross-compiler:
$ ARCH=arm64 CROSS_COMPILE=aarch64-calvin-linux-gnu- make -C \
../linux/tools/perf/ O=$(pwd)
It worked well. But when I tri
When the amount of data stored in the location corresponding to
iov_iter *from is less then 4, some data seems to go uninitialized.
Updating this condition accordingly, makes sense both intuitively and
logically as well, since the other check for extreme condition done is if
len > HCI_MAX_FRAME_S
Hi Arnaldo,
On Sat, Sep 5, 2020 at 1:28 AM Arnaldo Carvalho de Melo wrote:
> Humm, I assume all those fixes were for csets in a single Linux version,
> right? Otherwise I think it'd be better to have a fix per Fixes tag, so
> that they would go to the kernel sources where those bugs were fixed.
On Fri, Sep 4, 2020 at 6:28 PM Xie He wrote:
>
> The HDLC device is not actually prepending any header when it is used
> with this driver. When the PVC device has prepended its header and
> handed over the skb to the HDLC device, the HDLC device just hands it
> over to the hardware driver for tran
On Fri, Aug 28, 2020 at 03:18:50PM +0800, peng@nxp.com wrote:
> From: Peng Fan
>
> According to RM, Page 574, Chapter 5.2.6.4.3 Peripheral clock slice,
> "IP clock slices must be stopped to change the clock source.".
>
> So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
>
> Signed-o
On Wed, Aug 26, 2020 at 10:42:49PM +0200, Andreas Kemnade wrote:
> This adds a device tree for the Tolino Shine 2 HD Ebook reader.
>
> It is equipped with an i.MX6SL SoC. Except for backlight (via an EC) and
> the EPD, drivers are available and therefore things are defined in the
> dts.
>
> Andre
Hello,
syzbot found the following issue on:
HEAD commit:f75aef39 Linux 5.9-rc3
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=130c72f590
kernel config: https://syzkaller.appspot.com/x/.config?x=3c5f6ce8d5b68299
dashboard link: https://syzkaller.appspot
On Wed, Aug 26, 2020 at 03:14:07PM +0800, peng@nxp.com wrote:
> From: Peng Fan
>
> According to RM, for peripheral clock slice,
> "IP clock slices must be stopped to change the clock source.".
>
> So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
>
> Signed-off-by: Peng Fan
Applie
Because of system-specific EFI firmware limitations, EFI volatile
variables may not be capable of holding the required contents of
the Machine Owner Key (MOK) certificate store when the certificate
list grows above some size. Therefore, an EFI boot loader may pass
the MOK certs via a EFI configurat
Because of system-specific EFI firmware limitations, EFI volatile
variables may not be capable of holding the required contents of
the Machine Owner Key (MOK) certificate store when the certificate
list grows above some size. Therefore, an EFI boot loader may pass
the MOK certs via a EFI configurat
Move the loading of certs from the UEFI MokListRT into a separate
routine to facilitate additional MokList functionality.
There is no visible functional change as a result of this patch.
Although the UEFI dbx certs are now loaded before the MokList certs,
they are loaded onto different key rings.
Because of system-specific EFI firmware limitations, EFI volatile
variables may not be capable of holding the required contents of
the Machine Owner Key (MOK) certificate store when the certificate
list grows above some size. Therefore, an EFI boot loader may pass
the MOK certs via a EFI configurat
On 8/26/20 7:55 AM, Mimi Zohar wrote:
Hi Lenny,
On Tue, 2020-08-25 at 23:44 -0400, Lenny Szubowicz wrote:
Because of system-specific EFI firmware limitations,
EFI volatile variables may not be capable of holding the
required contents of the Machine Owner Key (MOK) certificate
store. Therefore,
Thank you for your email, Jakub!
On Fri, Sep 4, 2020 at 3:14 PM Jakub Kicinski wrote:
>
> Since this is a tunnel protocol on top of HDLC interfaces, and
> hdlc_setup_dev() sets dev->hard_header_len = 16; should we actually
> set the needed_headroom to 10 + 16 = 26? I'm not clear on where/if
> hdl
Guenter Roeck 於 2020年9月5日 週六 上午3:41寫道：
>
> On 9/3/20 9:21 AM, ChiYuan Huang wrote:
> > Guenter Roeck 於 2020年9月3日 週四 上午12:57寫道：
> >>
> >> On Wed, Sep 02, 2020 at 11:35:33PM +0800, cy_huang wrote:
> >>> From: ChiYuan Huang
> >>>
> >>> Fix: If vbus event is before cc_event trigger, hard_reset_count
On 9/4/20 6:16 PM, Souptick Joarder wrote:
Hi Andrew,
On Wed, Sep 2, 2020 at 3:00 AM John Hubbard wrote:
On 9/1/20 2:21 PM, Souptick Joarder wrote:
First, when memory allocation for sg_list_unaligned failed, there
is a bug of calling put_pages() as we haven't pinned any pages.
Second, if ge
Only prompt the unknown/invalid appraisal option if secureboot is enabled and
if the current appraisal state is different from the original one.
Signed-off-by: Bruno Meneguele
---
Changelog:
v3:
- fix sb_state conditional (Mimi)
v2:
- update commit message (Mimi)
- work with a temporary var inst
On Fri, Sep 04, 2020 at 05:07:08PM -0400, Mimi Zohar wrote:
> Hi Bruno,
>
> > + bool sb_state = arch_ima_get_secureboot();
> > + int appraisal_state = ima_appraise;
> >
> > if (strncmp(str, "off", 3) == 0)
> > - ima_appraise = 0;
> > + appraisal_state = 0;
> > els
On Fri, 04 Sep 2020 09:57:09 PDT (-0700), Christoph Hellwig wrote:
On Fri, Sep 04, 2020 at 10:13:18PM +0530, Anup Patel wrote:
I respectfully disagree. IMHO, the previous code made the RISC-V
timer driver convoluted (both SBI call and CLINT in one place) and
mandated CLINT for NoMMU kernel. In f
Hi Andrew,
On Wed, Sep 2, 2020 at 3:00 AM John Hubbard wrote:
>
> On 9/1/20 2:21 PM, Souptick Joarder wrote:
> > First, when memory allocation for sg_list_unaligned failed, there
> > is a bug of calling put_pages() as we haven't pinned any pages.
> >
> > Second, if get_user_pages_fast() failed we
On Fri, Sep 4, 2020 at 12:09 AM Matthew Wilcox wrote:
>
> On Thu, Sep 03, 2020 at 12:42:44PM +0530, Souptick Joarder wrote:
> > We can use is_valid_gup_flags() inside ->
> > get_user_pages_locked(),
> > get_user_pages_unlocked(),
> > pin_user_pages_locked() as well.
> >
> > Are you planning to add
Hi Linus,
Please pull.
Thx,
-Vineet
--->
The following changes since commit 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5:
Linux 5.9-rc1 (2020-08-16 13:04:57 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ tags/arc-5.9
On 9/2/20 3:55 AM, Andy Shevchenko wrote:
On Wed, Aug 26, 2020 at 6:45 AM Lenny Szubowicz wrote:
Move the loading of certs from the UEFI MokListRT into a separate
routine to facilitate additional MokList functionality.
There is no visible functional change as a result of this patch.
Although
On 9/4/20 5:23 PM, Moritz Fischer wrote:
Hi Russ,
On Fri, Sep 04, 2020 at 04:52:54PM -0700, Russ Weight wrote:
Create the Intel Security Manager class driver. The security
manager provides interfaces to manage secure updates for the
FPGA and BMC images that are stored in FLASH. The driver can
Hi Xu,
On Wed, Aug 19, 2020 at 03:45:21PM +0800, Xu Yilun wrote:
> This patch adds support for the Nios handshake private feature on Intel
> PAC (Programmable Acceleration Card) N3000.
>
> The Nios is the embedded processor on the FPGA card. This private feature
> provides a handshake interface t
On Thu, Sep 3, 2020 at 8:34 PM Andrea Arcangeli wrote:
>
> Hello,
>
> On Mon, Aug 17, 2020 at 03:11:16PM -0700, Lokesh Gidra wrote:
> > There has been an emphasis that Android is probably the only user for
> > the restriction of userfaults from kernel-space and that it wouldn’t
> > be useful anywh
Hi Xu,
On Wed, Aug 19, 2020 at 03:45:20PM +0800, Xu Yilun wrote:
> A new bus type "dfl" is introduced for private features which are not
> initialized by DFL feature drivers (dfl-fme & dfl-afu drivers). So these
> private features could be handled by separate driver modules.
>
> DFL feature drive
From: Boqun Feng Sent: Tuesday, September 1, 2020 8:01 PM
>
> When communicating with Hyper-V, HV_HYP_PAGE_SIZE should be used since
> that's the page size used by Hyper-V and Hyper-V expects all
> page-related data using the unit of HY_HYP_PAGE_SIZE, for example, the
> "pfn" in hv_page_buffer is
Hi Russ,
On Fri, Sep 04, 2020 at 04:52:54PM -0700, Russ Weight wrote:
> Create the Intel Security Manager class driver. The security
> manager provides interfaces to manage secure updates for the
> FPGA and BMC images that are stored in FLASH. The driver can
> also be used to update root entry has
From: Boqun Feng Sent: Tuesday, September 1, 2020 8:01 PM
>
> This patch introduces two types of GPADL: HV_GPADL_{BUFFER, RING}. The
> types of GPADL are purely the concept in the guest, IOW the hypervisor
> treat them as the same.
>
> The reason of introducing the types of GPADL is to support g
The per-cpu cached vmalloc'ed stacks are currently freed in the
CPU hotplug teardown path by the free_vm_stack_cache() callback,
which invokes vfree(), which may result in purging the list of
lazily freed vmap areas.
Purging all of the lazily freed vmap areas can take a long time
when the list of
On Sat, 5 Sep 2020 02:09:24 +0300 Grygorii Strashko wrote:
> The TI J721E (CPSW9g) ALE version is similar, in general, to Sitara AM3/4/5
> CPSW ALE, but has more extended functions and different ALE VLAN entry
> format.
>
> This patch adds support for for multi port TI J721E (CPSW9g) ALE variant.
On Sat, 5 Sep 2020 02:09:23 +0300 Grygorii Strashko wrote:
> The ALE VLAN entries are too much differ between different TI CPSW ALE
> versions. So, handling them using flags, defines and get/set functions
> became over-complicated.
>
> This patch introduces tables to describe the ALE VLAN entries
On 20-09-03 13:25:48, Paul Cercueil wrote:
> Use the newly introduced pm_ptr() macro, and mark the suspend/resume
> functions __maybe_unused. These functions can then be moved outside the
> CONFIG_PM_SUSPEND block, and the compiler can then process them and
> detect build failures independently of
On 9/4/20 5:01 PM, Randy Dunlap wrote:
On 9/4/20 4:52 PM, Russ Weight wrote:
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 97c0a6cc2ba7..0f0bed68e618 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -244,4 +244,15 @@ config IFPGA_SEC_MGR
region and for
From: Boqun Feng Sent: Tuesday, September 1, 2020 8:01 PM
>
> Pure function movement, no functional changes. The move is made, because
> in a later change, __vmbus_open() will rely on some static functions
> afterwards, so we sperate the move and the modification of
s/sperate/separate/
> __vmbu
On 20-09-03 13:25:40, Paul Cercueil wrote:
> Use the newly introduced pm_ptr() macro, and mark the suspend/resume
> functions __maybe_unused. These functions can then be moved outside the
> CONFIG_PM_SUSPEND block, and the compiler can then process them and
> detect build failures independently of
On 9/4/20 4:52 PM, Russ Weight wrote:
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 97c0a6cc2ba7..0f0bed68e618 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -244,4 +244,15 @@ config IFPGA_SEC_MGR
> region and for the BMC. Select this option to en
On 9/4/20 4:52 PM, Russ Weight wrote:
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 88f64fbf55e3..97c0a6cc2ba7 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -235,4 +235,13 @@ config FPGA_MGR_ZYNQMP_FPGA
> to configure the programmable logic(PL) t
Extend the MAX10 BMC Security Engine driver to provide a
handler to expose the flash update count for the FPGA user
image.
Signed-off-by: Russ Weight
Reviewed-by: Wu Hao
---
drivers/fpga/intel-m10-bmc-secure.c | 32 +
1 file changed, 32 insertions(+)
diff --git a/dr
Extend the Intel Security Manager class driver to include
an optional update/hw_errinfo sysfs node that can be used
to retrieve 64 bits of device specific error information
following a secure update failure.
The underlying driver must provide a get_hw_errinfo() callback
function to enable this fea
Extend the MAX10 BMC Security Engine driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight
Rev
Extend the Intel Security Manager class driver to include
an update/remaining_size sysfs node that can be read to
determine how much data remains to be transferred to the
secure update engine. This file can be used to monitor
progress during the "writing" phase of an update.
Signed-off-by: Russ We
Create the Intel Security Manager class driver. The security
manager provides interfaces to manage secure updates for the
FPGA and BMC images that are stored in FLASH. The driver can
also be used to update root entry hashes and to cancel code
signing keys.
This patch creates the class driver and p
Extend the MAX10 BMC Security Engine driver to provide a
handler to expose the canceled code signing key (CSK) bit
vectors. These use the standard bitmap list format
(e.g. 1,2-6,9).
Signed-off-by: Russ Weight
Reviewed-by: Wu Hao
---
drivers/fpga/intel-m10-bmc-secure.c | 60 +
Extend the Intel Security Manager class driver to include
an update/cancel sysfs file that can be written to request
that an update be canceled. The write may return EBUSY if
the update has progressed to the point that it cannot be
canceled by software or ENODEV if there is no update in
progress.
Extend the FPGA Intel Security Manager class driver to
include an update/filename sysfs node that can be used
to initiate a security update. The filename of a secure
update file (BMC image, FPGA image, Root Entry Hash image,
or Code Signing Key cancellation image) can be written to
this sysfs entr
Extend the Intel Security Manager class driver to
include an update/status sysfs node that can be polled
and read to monitor the progress of an ongoing secure
update. Sysfs_notify() is used to signal transitions
between different phases of the update process.
Signed-off-by: Russ Weight
Reviewed-b
Extend Intel Security Manager class driver to include
an update/error sysfs node that can be read for error
information when a secure update fails.
Signed-off-by: Russ Weight
Reviewed-by: Wu Hao
---
.../ABI/testing/sysfs-class-ifpga-sec-mgr | 17 ++
drivers/fpga/ifpga-sec-mgr.c
Extend the MAX10 BMC Security Engine driver to include
the functions that enable secure updates of BMC images,
FPGA images, etc.
Signed-off-by: Russ Weight
Reviewed-by: Wu Hao
---
drivers/fpga/intel-m10-bmc-secure.c | 272 +++-
include/linux/mfd/intel-m10-bmc.h | 101 +
These patches depend on the patchset: "add regmap-spi-avmm & Intel
Max10 BMC chip support" which is currently under review.
--
This patchset introduces the Intel Security Manager class driver
for managing secure updates on Intel FPGA Ca
Create a platform driver that can be invoked as a sub
driver for the Intel MAX10 BMC in order to support
secure updates. This sub-driver will invoke an
instance of the Intel FPGA Security Manager class driver
in order to expose sysfs interfaces for managing and
monitoring secure updates to FPGA and
Add DT node for Main NAVSS CPTS module.
Signed-off-by: Grygorii Strashko
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index cc4ff380a7bc..822c
Hi All,
arm64: dts: ti: k3-j7200: add dma and mcu cpsw nodes
This series adds DT nodes for TI J7200 SoC
- INTR/INTA, Ringacc and UDMA nodes for Main and MCU NAVSS, which are compatible
with J721E Soc, to enable DMA support
- MCU CPSW2g DT nodes to enable networking
This series depends on:
- [
The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.
Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).
Signed-off-by: Grygorii Strashko
---
.../dts/ti/k3-j7200-commo
From: Peter Ujfalusi
Add the intr, inta, ringacc and udmap nodes for main and mcu NAVSS.
Signed-off-by: Peter Ujfalusi
Signed-off-by: Grygorii Strashko
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 61 +++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 44 +
Add DT node for The TI j7200 MCU SoC Gigabit Ethernet two ports Switch
subsystem (MCU CPSW NUSS).
Signed-off-by: Grygorii Strashko
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 74 +++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup
The following commit has been merged into the x86/cleanups branch of tip:
Commit-ID: 93921baa3f6ff77e57d7e772165aa7bd709b5387
Gitweb:
https://git.kernel.org/tip/93921baa3f6ff77e57d7e772165aa7bd709b5387
Author:Colin Ian King
AuthorDate:Mon, 10 Aug 2020 08:55:08 +01:00
Commi
Update ibmvfc.h structs to use the preferred __packed and __aligned()
attribute macros defined in include/linux/compiler_attributes.h in place
of __attribute__().
Signed-off-by: Tyrel Datwyler
---
drivers/scsi/ibmvscsi/ibmvfc.h | 56 +-
1 file changed, 28 inserti
VIOS partitions with SLI-4 enabled Emulex adapters will be capable of
driving IO in parallel through mulitple work queues or channels, and
with new hyperviosr firmware that supports multiple interrupt sources
an ibmvfc NPIV single initiator can be modified to exploit end to end
channelization in a
On 2020-09-04, Petr Mladek wrote:
>>> I am currently playing with support for all three timestamps based
>>> on https://lore.kernel.org/lkml/20200814101933.574326...@linutronix.de/
>>>
>>> And I got the following idea:
>>>
>>> 1. Storing side:
>>>
>>>Create one more ring/array for storing the
According to the MPC750 Users Manual, the SITV value in Thermal
Management Register 3 is 13 bits long. The present code calculates the
SITV value as 60 * 500 cycles. This would overflow to give 10 us on
a 500 MHz CPU rather than the intended 60 us. (But according to the
Microprocessor Datasheet, th
This patch series fixes various bugs in the Thermal Assist Unit driver.
It was tested on 266 MHz and 292 MHz PowerBook G3 laptops.
Finn Thain (5):
powerpc/tau: Use appropriate temperature sample interval
powerpc/tau: Convert from timer to workqueue
powerpc/tau: Remove duplicated set_thresho
The commentary at the call site seems to disagree with the code. The
conditional prevents calling set_thresholds() via the exception handler,
which appears to crash. Perhaps that's because it immediately triggers
another TAU exception. Anyway, calling set_thresholds() from TAUupdate()
is redundant
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