On Thu, Apr 30, 2020 at 01:18:07PM -0700, Bjorn Andersson wrote:
> On Wed 29 Apr 23:30 PDT 2020, Manivannan Sadhasivam wrote:
>
> > From: Venkata Narendra Kumar Gutta
> >
> > Add support for the Inter-Processor Communication Controller (IPCC)
> > driver that coordinates the interrupts (inbound &
On Thu 30-04-20 13:20:10, Shakeel Butt wrote:
> On Thu, Apr 30, 2020 at 12:29 PM Johannes Weiner wrote:
> >
> > On Thu, Apr 30, 2020 at 11:27:12AM -0700, Shakeel Butt wrote:
> > > Lowering memory.max can trigger an oom-kill if the reclaim does not
> > > succeed. However if oom-killer does not find
On Thu 30-04-20 11:27:12, Shakeel Butt wrote:
> Lowering memory.max can trigger an oom-kill if the reclaim does not
> succeed. However if oom-killer does not find a process for killing, it
> dumps a lot of warnings.
It shouldn't dump much more than the regular OOM report AFAICS. Sure
there is "Out
Hi Bin,
On Sat, May 2, 2020 at 1:05 PM Bin Meng wrote:
> On Sat, May 2, 2020 at 6:09 PM Geert Uytterhoeven
> wrote:
> > On Sat, May 2, 2020 at 6:27 AM Bin Meng wrote:
> > > From: Bin Meng
> > >
> > > Drop CONFIG_MTD_M25P80 that was removed in
> > > commit b35b9a10362d ("mtd: spi-nor: Move m25
On Sat, May 2, 2020 at 1:06 PM Bin Meng wrote:
> From: Bin Meng
>
> CONFIG_MTD_M25P80 was removed and replaced by CONFIG_MTD_SPI_NOR in
> commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
>
> Signed-off-by: Bin Meng
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
On 5/1/20 11:03 PM, Ian Rogers wrote:
> This is expected in expr.y and metrics use floating point values such as
> x86 broadwell IFetch_Line_Utilization.
>
> Fixes: 26226a97724d (perf expr: Move expr lexer to flex)
> Signed-off-by: Ian Rogers
> ---
> tools/perf/util/expr.l | 14 +++---
On 5/1/20 11:03 PM, Ian Rogers wrote:
> Current expression allows 2 escaped '-,=' characters. However, some
> metrics require more, for example Haswell DRAM_BW_Use.
>
> Fixes: 26226a97724d (perf expr: Move expr lexer to flex)
> Signed-off-by: Ian Rogers
> ---
> tools/perf/util/expr.l | 2 +-
>
On Sun, 2020-05-03 at 16:39 +0100, Jonathan Cameron wrote:
> [External]
>
> On Mon, 27 Apr 2020 16:10:57 +0300
> Alexandru Ardelean wrote:
>
> > The final intent is to localize all buffer ops into the
> > industrialio-buffer.c file, to be able to add support for multiple buffers
> > per IIO devi
On Sun, 2020-05-03 at 13:51 +0100, Jonathan Cameron wrote:
> On Wed, 29 Apr 2020 18:17:39 +0300
> Alexandru Ardelean wrote:
>
> > From: Lars-Peter Clausen
> >
> > Let the core handle the buffer scan mask management including allocation
> > and channel selection. Having this handled in a central
From: Ben Chuang
Need to clear some bits in a vendor-defined register after reboot from
Windows 10.
Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support")
Reported-by: Grzegorz Kowal
Signed-off-by: Ben Chuang
---
drivers/mmc/host/sdhci-pci-gli.c | 5 +
1 file chang
On 30. 04. 20, 13:34, Gregory CLEMENT wrote:
> For at least some modems like the TELIT LE910, skipping SOF makes
> transfers blocking indefinitely after a short amount of data
> transferred.
>
> Given the small improvement provided by skipping the SOF (just one
> byte on about 100 bytes), it seems
On 30. 04. 20, 13:34, Gregory CLEMENT wrote:
> Use appropriate print helpers for debug messages.
>
> Signed-off-by: Gregory CLEMENT
> ---
> drivers/tty/n_gsm.c | 18 +-
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
Maxime Ripard 於 2020年4月29日 週三 上午12:21寫道：
>
> Hi,
>
> On Mon, Apr 27, 2020 at 03:23:42PM +0800, Jian-Hong Pan wrote:
> > Hi Maxime,
> >
> > Thanks for your V2 patch series! I'm testing it.
> >
> > This patch series is applied upon mainline kernel 5.7-rc2 cleanly and built.
> > System can boot into
so that the driver can load by matching the device tree
if compiled as module.
Cc: sta...@vger.kernel.org # v5.3+
Fixes: 90b86fcc47b4 ("DRM: Add KMS driver for the Ingenic JZ47xx SoCs")
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 1 +
1 file changed, 1 inserti
On Sat, May 2, 2020 at 2:03 AM Konrad Dybcio wrote:
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/thermal/qcom/tsens-v0_1.c | 142 +-
> drivers/thermal/qcom/tsens.c | 3 +
> drivers/thermal/qcom/tsens.h | 2 +-
> 3 files changed, 145 insertions(+), 2
This patch adds schema for primary CPU PLL found on few Qualcomm
platforms.
Signed-off-by: Sivaprakash Murugesan
---
.../devicetree/bindings/clock/qcom,a53pll.txt | 22
.../devicetree/bindings/clock/qcom,a53pll.yaml | 40 ++
2 files changed, 40 insertion
Paolo,
On 5/3/20 12:19 AM, Paolo Bonzini wrote:
On 02/05/20 11:24, Suravee Suthikulpanit wrote:
The questions to answer are: what is causing the re-entrancy? and why
is dropping the second EOI update safe?
The answer to the latter could well be "because we've already processed
it", but the
On 30. 04. 20, 13:34, Gregory CLEMENT wrote:
> Warn the upper layer when n_gms is ready to receive data
> again. Without this the associated virtual tty remain blocked
s/remain/&s/
> indefinitely.
>
> Fixes: 96fd7ce58ffb ("TTY: create drivers/tty and move the tty core files
> there")
This look
On Sun, 2020-05-03 at 12:37 +0100, Jonathan Cameron wrote:
> [External]
>
> On Wed, 29 Apr 2020 10:21:29 +0300
> Alexandru Ardelean wrote:
>
> > From: Dragos Bogdan
> >
> > If the serial interface is used, the 8-bit address should be latched using
> > the rising edge of the WR/FSYNC signal.
>
On Sat, May 2, 2020 at 2:03 AM Konrad Dybcio wrote:
>
> Signed-off-by: Konrad Dybcio
Reviewed-by: Amit Kucheria
> ---
> Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
The paranoidal pointer check in IRQ handler looks very strange - it
really protects us only against bogus drivers which request IRQ line
with null pointer dev_id. However, the code fragment is incorrect
because the dev pointer is used before the actual check which leads
to undefined behavior. Remov
On Mon, May 4, 2020 at 9:24 AM Zong Li wrote:
>
> Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> Currently, these two variables are put in bss section, there is a
> potential risk that secondary harts get the uninitialized value before
> main hart finishing the bss clearin
Hi Robert,
On 20-04-30 18:11, Robert Foss wrote:
> Hey Marco,
>
> On Thu, 30 Apr 2020 at 14:07, Marco Felsch wrote:
> >
> > On 20-04-30 13:20, Sakari Ailus wrote:
> > > On Thu, Apr 30, 2020 at 12:11:57PM +0200, Marco Felsch wrote:
> > > > On 20-04-30 12:59, Sakari Ailus wrote:
> > > > > Hi Marco
Add dt-bindings for ipq6018 mailbox driver
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/mailbox/
add dt-binding for ipq6018 apss clock controller
Signed-off-by: Sivaprakash Murugesan
---
include/dt-bindings/clock/qcom,apss-ipq.h | 12
1 file changed, 12 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
diff --git a/include/dt-bindings/clock/qcom,apss-
add support for apps pll and apcs clock.
Signed-off-by: Sivaprakash Murugesan
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 1aa8d
Qualcomm APCS global block provides a bunch of generic properties which
are required in a device tree. Add YAML schema for these properties.
Signed-off-by: Sivaprakash Murugesan
---
[V4]
* Addressed Rob's review comments
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 88
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL.
Add support for the apss pll found on ipq based devices which can
support CPU frequencies above 1Ghz.
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 8
drivers/clk/qcom/Makefile | 1 +
dr
The CPU on Qualcomm ipq platform is clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.
Add support for the mux and enable block which feeds the CPU on ipq
based devices.
Signed-off-by: Sivaprakash Murugesan
---
[V4]
* Addressed review comments
drivers/clk/qc
Add dt-binding for apss pll found on QCOM IPQ platforms
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/clock/qcom,ipq-apsspll.yaml | 49 ++
1 file changed, 49 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
di
The Qualcomm ipq6018 has apcs block, add compatible for the same.
Also, the apcs provides a clock controller functionality similar
to msm8916 but the clock driver is different.
Create a child platform device based on the apcs compatible for the
clock controller functionality.
Signed-off-by: Sivap
The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO,
these are connected to a clock mux and enable block.
This patch series adds support for these clocks and inturn enables clocks
required for CPU freq.
[V4]
* Re-written PLL found on IPQ platforms as a separate driver
* A
On 28-04-20, 16:13, Sanjay R Mehta wrote:
> From: Sanjay R Mehta
>
> Expose data about the configuration and operation of the
> PTDMA through debugfs entries: device name, capabilities,
> configuration, statistics.
>
> Signed-off-by: Sanjay R Mehta
> ---
> drivers/dma/ptdma/Makefile|
On Thu, Apr 30, 2020 at 12:36:09PM -0700, Bjorn Andersson wrote:
> On Wed 29 Apr 23:30 PDT 2020, Manivannan Sadhasivam wrote:
>
> > Add devicetree YAML binding for Qualcomm Inter-Processor Communication
> > Controller (IPCC) block.
> >
> > Signed-off-by: Manivannan Sadhasivam
> > ---
> > .../bi
On 4/21/2020 2:29 AM, Rob Herring wrote:
On Tue, Apr 14, 2020 at 08:25:15AM +0530, Sivaprakash Murugesan wrote:
Qualcomm APCS global block provides a bunch of generic properties which
are required in a device tree. Add YAML schema for these properties.
Signed-off-by: Sivaprakash Murugesan
--
On 28-04-20, 16:13, Sanjay R Mehta wrote:
> +static void pt_do_cmd_complete(unsigned long data)
> +{
> + struct pt_tasklet_data *tdata = (struct pt_tasklet_data *)data;
> + struct pt_cmd *cmd = tdata->cmd;
> + struct pt_cmd_queue *cmd_q = &cmd->pt->cmd_q;
> + u32 tail;
> +
> +
Hi Rob,
On 4/21/2020 2:31 AM, Rob Herring wrote:
On Tue, Apr 14, 2020 at 08:25:16AM +0530, Sivaprakash Murugesan wrote:
This patch adds schema for primary CPU PLL found on few Qualcomm
platforms.
Signed-off-by: Sivaprakash Murugesan
---
[V3]
* Fixed dt binding error in "$id" field.
.../d
Hi Stephen,
On 4/22/2020 2:34 PM, Stephen Boyd wrote:
Quoting Sivaprakash Murugesan (2020-04-13 19:55:19)
The CPU on Qualcomm's IPQ platform devices are clocked primarily by a
PLL and xo which are connected to a mux and enable block, This patch adds
The comma should be a period? Don't write "T
> … Thus add a call of the function
> “nfp_nsp_close” for the completion of the exception handling.
I suggest to mention also the addition of a jump target because of
a Linux coding style concern.
…
> +++ b/drivers/net/ethernet/netronome/nfp/abm/main.c
…
> @@ -300,12 +297,16 @@ nfp_abm_vnic_set_
On 28-04-20, 16:13, Sanjay R Mehta wrote:
> From: Sanjay R Mehta
>
> This driver add support for AMD PTDMA controller. This device
> performs high-bandwidth memory to memory and IO copy operation.
> Device commands are managed via a circular queue of 'descriptors',
> each of which specifies sour
Hello David, & All
This review and mail is more for pointing out the downsides of UTs. I
am not demanding any changes, these comments can be seen as 'nit's.
On Wed, 2020-04-29 at 12:15 +0800, David Gow wrote:
> On Tue, Apr 14, 2020 at 7:46 PM Vaittinen, Matti
> wrote:
> > Hello Stephen & All,
>
On Sat, 2020-05-02 at 19:25 +0100, Jonathan Cameron wrote:
> On Tue, 28 Apr 2020 12:31:28 +0300
> Alexandru Ardelean wrote:
>
> > This change cleans up the driver's probe function to use only devm_
> > function variants. This also gets rid of the remove function and moves the
> > clock & regulato
On 4/30/20 7:35 PM, Wolfram Sang wrote:
On Thu, Apr 30, 2020 at 05:43:21PM +0200, Alain Volmat wrote:
In case of the I2C client exposes the flag I2C_CLIENT_HOST_NOTIFY,
pm_runtime_get_sync is called in order to always keep active the
adapter. However later on, pm_runtime_put_sync is never called
On Mon, May 4, 2020 at 12:04 PM Atish Patra wrote:
>
> This patch removes the unused functions set_kernel_text_rw/ro.
> Currently, it is not being invoked from anywhere and no other architecture
> (except arm) uses this code. Even in ARM, these functions are not invoked
> from anywhere currently.
On Sun, May 03, 2020 at 10:04:47PM -0700, Ira Weiny wrote:
> Grepping for 'asm/highmem.h' and investigations don't reveal any issues...
> But
> you do have me worried. That said 0-day has been crunching on multiple
> versions of this series without issues such as this (save the mips issue
> abo
Hi Vinod,
> -Original Message-
> From: Vinod Koul [mailto:vk...@kernel.org]
> Sent: Monday, May 4, 2020 10:46 AM
> To: Rafał Hibner
> Cc: Appana Durga Kedareswara Rao ; Radhey Shyam
> Pandey ; Harini Katakam ; Dan
> Williams ; Michal Simek ; open
> list:DMA GENERIC OFFLOAD ENGINE SUBSYSTE
On 28-04-20, 18:10, Alan Mikhak wrote:
> From: Alan Mikhak
>
> Modify dw_edma_device_transfer() to also support the semantics of dma
> device transfer for additional use cases involving pcitest utility as a
> local initiator.
>
> For its original use case, dw-edma supported the semantics of dma
From: Ira Weiny
Continue the kmap clean up with 2 follow on patches
These apply after the kmap cleanup V2 series:
https://lore.kernel.org/lkml/20200504010912.982044-1-ira.we...@intel.com/
Ira Weiny (2):
kmap: Remove kmap_atomic_to_page()
parisc/kmap: Remove duplicate kmap code
arch/csky/
From: Ira Weiny
parisc reimplements the kmap calls except to flush it's dcache. This is
arguably an abuse of kmap but regardless it is messy and confusing.
Remove the duplicate code and have parisc define
ARCH_HAS_FLUSH_ON_KUNMAP for a kunmap_flush_on_unmap() architecture
specific call to flush
From: Ira Weiny
kmap_atomic_to_page() has no callers and is only defined on 1 arch and
declared on another. Remove it.
Suggested-by: Al Viro
Signed-off-by: Ira Weiny
---
arch/csky/include/asm/highmem.h | 1 -
arch/csky/mm/highmem.c | 13 -
arch/nds32/include/asm/highm
Hi,
On 4/24/2020 10:16 PM, Douglas Anderson wrote:
Our switch statement doesn't have entries for CPU_CLUSTER_PM_ENTER,
CPU_CLUSTER_PM_ENTER_FAILED, and CPU_CLUSTER_PM_EXIT and doesn't have
a default. This means that we'll try to do a flush in those cases but
we won't necessarily be the last CPU
From: Leon Romanovsky
Changelog:
v3: Rebased on latest rdma-nex, which includes HCA set capability patch
and LAG code and this is why new patch from Maor was added.
v2: https://lore.kernel.org/linux-rdma/20200413133703.932731-1-l...@kernel.org
Dropped patch "RDMA/cm: Set flow label of recv_wc
On 02-05-20, 15:00, Rafał Hibner wrote:
> Hello Vinod,
>
> On 02.05.2020 14:32, Vinod Koul wrote:
> > Would it not be better to use list_del_init() where we delete it rather
> > than do the init here?
> >
>
> It is not a problem of list element itself not being initialized.
> The problem is that
On Sat, 2 May 2020 at 12:17, Greg Kroah-Hartman
wrote:
>
> This is the start of the stable review cycle for the 4.14.178 release.
> There are 117 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Re
On Sat, 2 May 2020 at 12:18, Greg Kroah-Hartman
wrote:
>
> This is the start of the stable review cycle for the 4.19.120 release.
> There are 47 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Res
On 01-05-20, 00:22, Ansuel Smith wrote:
> Binding in Documentation is still "operating-points-v2-kryo-cpu".
> Restore the old binding to fix the compatibility problem.
>
> Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")
> Signed-off-by: Ansuel Smith
> ---
> drivers/cpufre
Hello Christophe,
On Sat, May 02, 2020 at 01:59:49PM +0200, Christophe JAILLET wrote:
> Fix a cut'n'paste error in a warning message. This should be
> 'cpu-idle-state-residency-ns' to match the property searched in the
> previous 'of_property_read_u32_array()'
>
> Fixes: 9c7b185ab2fe ("powernv/cp
On 02-05-20, 20:15, Cristian Ciocaltea wrote:
> When the kernel is built with lockdep support and the owl-dma driver is
> used, the following message is shown:
>
> [2.496939] INFO: trying to register non-static key.
> [2.501889] the code is fine but needs lockdep annotation.
> [2.50735
On Mon, May 04, 2020 at 02:35:09AM +0100, Al Viro wrote:
> On Sun, May 03, 2020 at 06:09:01PM -0700, ira.we...@intel.com wrote:
> > From: Ira Weiny
> >
> > The kmap infrastructure has been copied almost verbatim to every
> > architecture.
> > This series consolidates obvious duplicated code by d
On 30-04-20, 09:32, Saravana Kannan wrote:
> You are missing the point. This is not about aggregation. This is
> about OPP voting for bandwidth on a path when the vote can/should be
> 0.
>
> I'll give another example. Say one of the interconnect paths needs to
> be voted only when a particular use
Hi Cristian,
On 02-05-20, 20:35, Cristian Ciocaltea wrote:
> On Sat, May 02, 2020 at 05:53:33PM +0530, Vinod Koul wrote:
> > Hi Cristian,
> >
> > On 29-04-20, 18:28, Cristian Ciocaltea wrote:
> > > When the kernel is built with lockdep support and the owl-dma driver is
> > > used, the following m
On 5/4/20 12:29 AM, Jason Baron wrote:
>
>
> On 5/3/20 6:24 AM, Roman Penyaev wrote:
>> On 2020-05-02 00:09, Jason Baron wrote:
>>> On 5/1/20 5:02 PM, Roman Penyaev wrote:
Hi Jason,
That is indeed a nice catch.
Seems we need smp_rmb() pair between list_empty_careful(&rp->rd
please ignore it, i send it by accident.
On Mon, May 04, 2020 at 06:33:18AM +0200, Oleksij Rempel wrote:
> changes v3:
> - rename port_mode to master_slave
> - move validation code to net/ethtool/linkmodes.c
> - add UNSUPPORTED state and avoid sending unsupported fields
> - more formatting and n
changes v3:
- rename port_mode to master_slave
- move validation code to net/ethtool/linkmodes.c
- add UNSUPPORTED state and avoid sending unsupported fields
- more formatting and naming fixes
- tja11xx: support only force mode
- tja11xx: mark state as unsupported
changes v3:
- provide separate
On 5/3/20 6:24 AM, Roman Penyaev wrote:
> On 2020-05-02 00:09, Jason Baron wrote:
>> On 5/1/20 5:02 PM, Roman Penyaev wrote:
>>> Hi Jason,
>>>
>>> That is indeed a nice catch.
>>> Seems we need smp_rmb() pair between list_empty_careful(&rp->rdllist) and
>>> READ_ONCE(ep->ovflist) for ep_events_a
Move out the initialization function to l1d_flush_init_once()
so that it can be reused for subsequent patches. The side-effect
of this patch is that the memory allocated for l1d flush pages
is no longer freed up and the memory allocated once is shared
amongst callers.
l1d_flush_sw/hw() are now abs
Implement a mechanism to selectively flush the L1D cache. The goal is to
allow tasks that are paranoid due to the recent snoop assisted data sampling
vulnerabilites, to flush their L1D on being switched out. This protects
their data from being snooped or leaked via side channels after the task
has
Add documentation of l1d flushing, explain the need for the
feature and how it can be used.
Signed-off-by: Balbir Singh
Reviewed-by: Kees Cook
---
Documentation/admin-guide/hw-vuln/index.rst | 1 +
.../admin-guide/hw-vuln/l1d_flush.rst | 40 +++
2 files changed, 41 in
cond_ibpb() has the necessary bits required to track the
previous mm in switch_mm_irqs_off(). This can be reused for
other use cases like L1D flushing (on context switch out).
Suggested-by: Thomas Gleixner
Signed-off-by: Balbir Singh
---
arch/x86/include/asm/tlbflush.h | 2 +-
arch/x86/mm/tlb.
Refactor the existing assembly bits into smaller helper functions
and also abstract L1D_FLUSH into a helper function. Use these
functions in kvm for L1D flushing.
Reviewed-by: Kees Cook
Signed-off-by: Balbir Singh
---
arch/x86/include/asm/cacheflush.h | 3 ++
arch/x86/kernel/l1d_flush.c
Split out the allocation and free routines to be used in a follow
up set of patches (to reuse for L1D flushing).
Signed-off-by: Balbir Singh
Reviewed-by: Kees Cook
---
arch/x86/include/asm/cacheflush.h | 3 +++
arch/x86/kernel/Makefile | 1 +
arch/x86/kernel/l1d_flush.c | 36 ++
Provide a mechanism to flush the L1D cache on context switch. The goal
is to allow tasks that are paranoid due to the recent snoop assisted data
sampling vulnerabilites, to flush their L1D on being switched out.
This protects their data from being snooped or leaked via side channels
after the task
On 28-04-2020 15:29, Thierry Reding wrote:
@@ -2042,6 +2044,19 @@ static int tegra_xudc_gadget_stop(struct usb_gadget
*gadget)
return 0;
}
+static int tegra_xudc_gadget_vbus_draw(struct usb_gadget *gadget,
+ unsigned int m_a)
+{
+
This patch removes the unused functions set_kernel_text_rw/ro.
Currently, it is not being invoked from anywhere and no other architecture
(except arm) uses this code. Even in ARM, these functions are not invoked
from anywhere currently.
Fixes: d27c3c90817e ("riscv: add STRICT_KERNEL_RWX support")
This adds tests which will validate architecture page table helpers and
other accessors in their compliance with expected generic MM semantics.
This will help various architectures in validating changes to existing
page table helpers or addition of new ones.
This test covers basic page table entry
This just defines mm_p4d_folded() to check whether P4D page table level is
folded at runtime.
Cc: Thomas Gleixner
Cc: Andrew Morton
Cc: Ingo Molnar
Cc: x...@kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Kirill A. Shutemov
Signed-off-by: Anshuman Khandual
---
arch/x86/include/as
This adds a test validation for architecture exported page table helpers.
Patch adds basic transformation tests at various levels of the page table.
This test was originally suggested by Catalin during arm64 THP migration
RFC discussion earlier. Going forward it can include more specific tests
wit
On Fri, May 01, 2020 at 06:12:07PM +0200, Dietmar Eggemann wrote:
> On 30/04/2020 15:10, Pavan Kondeti wrote:
> > On Mon, Apr 27, 2020 at 10:37:08AM +0200, Dietmar Eggemann wrote:
> >> From: Luca Abeni
>
> [...]
>
> >> @@ -1653,10 +1654,19 @@ select_task_rq_dl(struct task_struct *p, int cpu,
>
On 5/3/20 12:23 AM, Dongyang Zhan wrote:
> Hi,
>
> I am a security researcher, my name is Dongyang Zhan. I found a potential bug.
>
> I hope you can help me to confirm it.
>
> Thank you.
>
> Possible memory leak in Linux 4.10.17. The function unxz() in
It would be more helpful if you could foc
Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
Currently, these two variables are put in bss section, there is a
potential risk that secondary harts get the uninitialized value before
main hart finishing the bss clearing. In this case, all secondary
harts would pass the waiti
Hi all,
Today's linux-next merge of the devicetree tree got a conflict in:
Documentation/devicetree/bindings/display/panel/panel-common.yaml
between commit:
92e513fb0798 ("dt-bindings: display: grammar fixes in panel/")
from the drm tree and commit:
3d21a4609335 ("dt-bindings: Remove ca
Prior to 1d27732f411d ("net: dsa: setup and teardown ports"), we would
not treat failures to set-up an user port as fatal, but after this
commit we would, which is a regression for some systems where interfaces
may be declared in the Device Tree, but the underlying hardware may not
be present (plug
Hi all,
After merging the keys tree, today's linux-next build (x86_64
allmodconfig) produced these warnings:
scripts/Makefile.lib:8: 'always' is deprecated. Please use 'always-y' instead
scripts/Makefile.lib:12: 'hostprogs-y' and 'hostprogs-m' are deprecated. Please
use 'hostprogs' instead
Intr
After commit f0b231101c94 ("mm/SLUB: delay giving back empty slubs to
IRQ enabled regions"), when the free_slab() is invoked with the IRQ
disabled, the empty slubs are moved to a per-CPU list and will be
freed after IRQ enabled later. But in the current codes, there is
a check to see if there reall
Hi all,
On Mon, 4 May 2020 13:25:29 +1000 Stephen Rothwell
wrote:
>
> Due to further changes in Linus' tree over the weekend, this fixup is
> not linger needed.
"no longer" (Monday's ...)
--
Cheers,
Stephen Rothwell
pgpQJB6x10RtY.pgp
Description: OpenPGP digital signature
Hi all,
On Mon, 2 Mar 2020 11:37:37 +1100 Stephen Rothwell
wrote:
>
> After merging the keys tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> fs/io_uring.c: In function 'io_splice_punt':
> fs/io_uring.c:2473:6: error: too few arguments to function 'get_pipe_info'
Hi all,
Today's linux-next merge of the keys tree got conflicts in:
samples/Kconfig
samples/Makefile
between commit:
3ba9c29d1877 ("samples: watchdog: use 'userprogs' syntax")
from the kbuild tree and commit:
631ec151fd96 ("Add sample notification program")
from the keys tree.
I fix
As debug information gets larger and larger, it helps significantly save
the size of vmlinux images to compress the information in the debug
information sections. Note: this debug info is typically split off from
the final compressed kernel image, which is why vmlinux is what's used
in conjunction
2020년 5월 1일 (금) 오후 11:06, Eric W. Biederman 님이 작성:
>
> js1...@gmail.com writes:
>
> > From: Joonsoo Kim
> >
> > Until now, PageHighMem() is used for two different cases. One is to check
> > if there is a direct mapping for this page or not. The other is to check
> > the zone of this page, that is,
On Wed, Apr 29, 2020 at 06:36:50AM -0700, Matthew Wilcox wrote:
> @@ -886,7 +906,7 @@ static int __add_to_page_cache_locked(struct page *page,
> /* Leave page->index set: truncation relies upon it */
> if (!huge)
> mem_cgroup_cancel_charge(page, memcg, false);
> - put_
2020년 5월 1일 (금) 오후 9:34, Christoph Hellwig 님이 작성:
>
> On Fri, May 01, 2020 at 09:15:30PM +0900, Joonsoo Kim wrote:
> > I think that PageHighMemZone() is long and complicated enough to have
> > a macro.
>
> It is. But then again it also shouldn't really be used by anything
> but MM internals.
I'm
2020년 5월 1일 (금) 오후 9:30, Christoph Hellwig 님이 작성:
>
> On Wed, Apr 29, 2020 at 12:26:40PM +0900, js1...@gmail.com wrote:
> > From: Joonsoo Kim
> >
> > Until now, PageHighMem() is used for two different cases. One is to check
> > if there is a direct mapping for this page or not. The other is to che
2020년 5월 1일 (금) 오후 9:26, Christoph Hellwig 님이 작성:
>
> On Wed, Apr 29, 2020 at 12:26:39PM +0900, js1...@gmail.com wrote:
> > From: Joonsoo Kim
> >
> > Until now, PageHighMem() is used for two different cases. One is to check
> > if there is a direct mapping for this page or not. The other is to che
2020년 5월 1일 (금) 오후 9:24, Christoph Hellwig 님이 작성:
>
> On Wed, Apr 29, 2020 at 12:26:38PM +0900, js1...@gmail.com wrote:
> > From: Joonsoo Kim
> >
> > Until now, PageHighMem() is used for two different cases. One is to check
> > if there is a direct mapping for this page or not. The other is to che
syzbot suspects this bug was fixed by commit:
commit 4b793acdca0050739b99ace6a8b9e7f717f57c6b
Author: Taehee Yoo
Date: Fri Feb 28 18:01:46 2020 +
hsr: use netdev_err() instead of WARN_ONCE()
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=130746ffe0
start commit: ea
2020년 5월 1일 (금) 오후 9:22, Christoph Hellwig 님이 작성:
>
> On Wed, Apr 29, 2020 at 12:26:37PM +0900, js1...@gmail.com wrote:
> > index 6598001..be759a6 100644
> > --- a/kernel/power/snapshot.c
> > +++ b/kernel/power/snapshot.c
> > @@ -1227,7 +1227,7 @@ static struct page *saveable_highmem_page(struct zo
On 5/1/20 7:22 PM, Eric Biggers wrote:
On Tue, Apr 07, 2020 at 04:03:18PM -0400, Waiman Long wrote:
For kvmalloc'ed data object that contains sensitive information like
cryptographic key, we need to make sure that the buffer is always
cleared before freeing it. Using memset() alone for buffer cl
On Sat, May 02, 2020 at 11:16:30PM +, Christopher Lameter wrote:
> On Fri, 1 May 2020, Rafael Aquini wrote:
>
> > Sometimes it is desirable to override SLUB's debug facilities
> > default behavior upon stumbling on a cache or object error
> > and just stop the execution in order to grab a core
On Fri, May 01, 2020 at 07:17:24PM -0400, Qian Cai wrote:
>
>
> > On May 1, 2020, at 5:54 PM, Rafael Aquini wrote:
> >
> > It seems like a good idea which also would required "adding things"
> > elsewhere, but doesn't look mutually exclusive with the approach here.
>
> Also, what’s so special
On Sun, May 03, 2020 at 08:58:58PM -0400, Joel Fernandes wrote:
> On Sun, May 03, 2020 at 05:20:32PM -0700, Paul E. McKenney wrote:
> > On Sun, May 03, 2020 at 07:42:50PM -0400, Joel Fernandes wrote:
> > > On Fri, May 01, 2020 at 02:37:53PM -0700, Paul E. McKenney wrote:
> > > [...]
> > > > > @@ -2
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