Hi Dmitry,
In commit
3a349763cf11 ("Input: synaptics-rmi4 - write config register values to the
right offset")
Fixes tag
Fixes: ff8f83708b3e (Input: synaptics-rmi4 - add support for 2D
has these problem(s):
- Subject has leading but no trailing parentheses
Please do not split Fixes ta
Commit d901b2760dc6 ("lib/scatterlist: Provide a DMA page iterator")
added the sg DMA iterator but a leftover remained in the sg_page_iter
documentation as you cannot get the page dma address (only the page
itself), fix it.
Cc: Jason Gunthorpe
Signed-off-by: Gal Pressman
Reviewed-by: Mukesh Ojha
In usX2Y_In04_init(), a new urb is firstly created through usb_alloc_urb()
and saved to 'usX2Y->In04urb'. Then, a buffer is allocated through
kmalloc() and saved to 'usX2Y->In04Buf'. After the urb is initialized, a
sanity check is performed for the endpoint in the urb by invoking
usb_urb_ep_type_ch
Ping...
> -Original Message-
> From: Mukesh Ojha [mailto:mo...@codeaurora.org]
> Sent: Monday, April 1, 2019 4:02 PM
> To: Anson Huang ; dmitry.torok...@gmail.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengutronix.de;
> feste...@gmail.com; linux-in...@vger.kernel.org; linux
This series fix some bugs and add some features in stmmac driver.
5 patches are for common stmmac or dwmac4:
1. update rx tail pointer to fix rx dma hang issue.
2. change condition for mdc clock to fix csr_clk
Ping...
> -Original Message-
> From: Mukesh Ojha [mailto:mo...@codeaurora.org]
> Sent: Monday, April 1, 2019 3:47 PM
> To: Anson Huang ; t...@linutronix.de;
> ja...@lakedaemon.net; marc.zyng...@arm.com; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.co
Ping...
> -Original Message-
> From: Mukesh Ojha [mailto:mo...@codeaurora.org]
> Sent: Monday, April 1, 2019 4:01 PM
> To: Anson Huang ; thierry.red...@gmail.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengutronix.de;
> feste...@gmail.com; linux-...@vger.kernel.org; linux-ar
On Fri, 26 Apr 2019 05:16:24 +0200,
Fuqian Huang wrote:
>
> Pointers should be printed with %p or %px rather than
> cast to long type and printed with %lx.
> Drop the address printing.
>
> Signed-off-by: Fuqian Huang
Applied now. Thanks.
Takashi
> arch/arm/mach-rockchip/platsmp.c | 12 ++--
> arch/arm/mach-rockchip/pm.c | 2 ++
* Would a commit subject variant be nicer?
* I dare to present a reminder for a recurring development topic.
How do you think about to adjust the exception handling in these function
implementati
Ping...
> -Original Message-
> From: Anson Huang
> Sent: Monday, April 1, 2019 1:15 PM
> To: jassisinghb...@gmail.com; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> Cc: dl-lin
On 28/04/2019 2.40, Tobin C. Harding wrote:
Currently error return from kobject_init_and_add() is not followed by a
call to kobject_put(). This means there is a memory leak.
Add call to kobject_put() in error path of kobject_init_and_add().
Signed-off-by: Tobin C. Harding
Reviewed-by: Pe
On Fri, Apr 26, 2019 at 07:41:09AM -0700, Dave Hansen wrote:
> On 4/25/19 2:45 PM, Mike Rapoport wrote:
> > The idea behind the prevention is that if we fault in pages in the
> > execution path, we can compare target address against the kernel symbol
> > table. So if we're in a function, we allow
On Thu, Apr 25, 2019 at 05:30:13PM -0700, Andy Lutomirski wrote:
> On Thu, Apr 25, 2019 at 2:46 PM Mike Rapoport wrote:
> >
> > Hi,
> >
> > Address space isolation has been used to protect the kernel from the
> > userspace and userspace programs from each other since the invention of the
> > virtu
On Fri, Apr 26, 2019 at 09:42:23AM +0200, Peter Zijlstra wrote:
> On Fri, Apr 26, 2019 at 12:45:52AM +0300, Mike Rapoport wrote:
> > If a system call runs in isolated context, it's accesses to kernel code and
> > data will be verified by SCI susbsytem.
> >
> > Signed-off-by: Mike Rapoport
> > ---
On Fri, Apr 26, 2019 at 09:49:56AM +0200, Peter Zijlstra wrote:
> On Fri, Apr 26, 2019 at 12:45:49AM +0300, Mike Rapoport wrote:
> > The initial SCI implementation allows access to any kernel data, but it
> > limits access to the code in the following way:
> > * calls and jumps to known code symbol
Set init_needed flag only when successfully getting dquot,
so that we can skip unnecessary subsequent operation.
Signed-off-by: Chengguang Xu
---
fs/quota/dquot.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c
index fc20e06c56ba..8d4c
On Fri, Apr 26, 2019 at 01:30:53PM -0400, Jeff Layton wrote:
> > I _probably_ would take allocation out of the loop (e.g. make it
> > __getname(), called unconditionally) and turned it into the
> > d_path.c-style read_seqbegin_or_lock()/need_seqretry()/done_seqretry()
> > loop, so that the first p
Using dev_get_drvdata directly.
Cc: Vinod Koul
Cc: dmaeng...@vger.kernel.org
Signed-off-by: Kefeng Wang
---
drivers/dma/bcm-sba-raid.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/dma/bcm-sba-raid.c b/drivers/dma/bcm-sba-raid.c
index 72878ac5c78d..fa81d0177765 1
Using dev_get_drvdata directly.
Cc: Vinod Koul
Cc: dmaeng...@vger.kernel.org
Signed-off-by: Kefeng Wang
---
drivers/dma/nbpfaxi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/nbpfaxi.c b/drivers/dma/nbpfaxi.c
index a67b292190f4..594409a6e975 100644
--- a/d
Currently we parse user data byte after byte which leads to
overcomplicating of parsing algorithm. There are no performance
critical users of bitmap_parse_user(), and so we can duplicate
user data to kernel buffer and simply call bitmap_parselist().
This rework lets us unify and simplify bitmap_par
The test is derived from bitmap_parselist()
Signed-off-by: Yury Norov
---
lib/test_bitmap.c | 102 +-
1 file changed, 101 insertions(+), 1 deletion(-)
diff --git a/lib/test_bitmap.c b/lib/test_bitmap.c
index d3a501f2a81a..99ad6c35d038 100644
--- a/lib
bitmap_parse() is ineffective and full of opaque variables and opencoded
parts. It leads to hard understanding of it. This rework includes:
- remove bitmap_shift_left() call from the cycle. Now it makes the
complexity of the algorithm as O(nbits^2). In the suggested approach
the input string
New design of inner bitmap_parse() allows to avoid
calculating the size of a null-terminated string.
Signed-off-by: Yury Norov
---
include/linux/cpumask.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 21755471b1c3..
On top of next-20190418.
Similarly to recently revisited bitmap_parselist() [1],
bitmap_parse() is ineffective and overcomplicated. This
series reworks it, aligns its interface with bitmap_parselist()
and makes usage simpler.
The series also adds a test for the function and fixes usage of it
in
Introduce BITS_TO_U64, BITS_TO_U32 and BITS_TO_BYTES as they are handy
in the following changes (BITS_TO_U32 specifically). Sync tools/
version of the macros with the kernel implementation.
Signed-off-by: Yury Norov
---
include/linux/bitops.h | 3 +++
tools/include/linux/bitops.h | 9 +
Hi, Shawn
As patch 1/2 is an independent patch to improve the
imx_scu_irq_group_enable() API, so I sent out V2 independently with some commit
message improved, please help review, thanks.
Hi, Guenter
I addressed your comments in V2 patch series, please help review,
thanks.
Anson
New function works like strchrnul() with a length limited strings.
Signed-off-by: Yury Norov
---
include/linux/string.h | 3 +++
lib/string.c | 20
2 files changed, 23 insertions(+)
diff --git a/include/linux/string.h b/include/linux/string.h
index 4deb11f7976b..
i.MX system controller watchdog can support pretimeout IRQ
via general SCU MU IRQ, it depends on IMX_SCU and driver MUST
be probed after SCU IPC ready, then enable corresponding SCU
IRQ group and register SCU IRQ notifier, when watchdog pretimeout
IRQ fires, SCU MU IRQ will be handled and watchdog
i.MX system controller watchdog now depends on SCU driver, so it
needs to be subnode of SCU node in DT, binding doc is moved to
fsl,scu.txt as well.
Signed-off-by: Anson Huang
---
New patch.
---
.../bindings/watchdog/fsl-imx-sc-wdt.txt | 24 --
1 file changed, 24 de
i.MX system controller watchdog has pretimeout function which
depends on i.MX SCU driver, so it should be a subnode of SCU.
Signed-off-by: Anson Huang
---
New patch.
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch
i.MX system controller watchdog has pretimeout function which
depends on i.MX SCU driver, so watchdog DT node needs to be
subnode of SCU, this patch adds i.MX system controller watchdog
binding to SCU binding doc.
Signed-off-by: Anson Huang
---
New patch.
---
.../devicetree/bindings/arm/freescal
On 2019/4/22 2:48, Julian Anastasov wrote:
>
> Hello,
>
> On Thu, 18 Apr 2019, linmiaohe wrote:
>
>> From: Jie Liu
>>
>> If we set sysctl_wmem_max or sysctl_rmem_max larger than INT_MAX, the
>> send/receive buffer of sock will be an negative value. Same as when
>> the val is larger tha
The imx_scu_irq_group_enable() is normally called during module driver
probe phase to enable SCU group irq, if SCU IPC is NOT ready, below
dump will show out:
[0.933001] Hardware name: Freescale i.MX8QXP MEK (DT)
[0.938129] pstate: 6005 (nZCv daif -PAN -UAO)
[0.942907] pc : imx_scu
wait_for_completion_timeout() returns unsigned long (0 on timeout or
remaining jiffies) not int - so rather than introducing an additional
variable simply wrap the completion into an if().
Signed-off-by: Nicholas Mc Guire
---
Problem located with experimental API conformance checking cocci scrip
While the endiannes is being handled correctly sparse was unhappy with
the missing annotation as be16_to_cpu() expects a __be16.
Signed-off-by: Nicholas Mc Guire
---
Problem reported by sparse
As far as I understand sparse here the __force is actually the only
solution possible to inform spar
On 2019年04月27日 16:58, Borislav Petkov wrote:
On Fri, Apr 26, 2019 at 11:18:48AM +0800, Zhao, Yakui wrote:
It seems that it is seldom used in kernel although the explicit register
variable is supported by GCC and makes the code look simpler. And it seems
that the explicit register variable is
Hi Vinod,
Thanks your comments.
Please see my comments inline.
Best Regards,
Peng
>-Original Message-
>From: Vinod Koul
>Sent: 2019年4月26日 19:51
>To: Peng Ma
>Cc: dan.j.willi...@intel.com; Leo Li ;
>dmaeng...@vger.kernel.org; linux-kernel@vger.kernel.org
>Subject: [EXT] Re: [PATCH] dmae
On 4/11/19 1:28 AM, Paul Walmsley wrote:
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra :
https://github.com/riscv/r
Hi, Stephen
For this patch series, I think patch [1/2] can be picked up directly,
for patch[2/2], it can be fixed from driver level, it means drivers should make
sure the composite clock is gated before changing parent/rate, so no need to do
any change to composite-7ulp clk driver or cor
On Sat, Apr 27, 2019 at 09:28:09PM +0200, Greg Kroah-Hartman wrote:
> On Sat, Apr 27, 2019 at 06:13:30PM +1000, Tobin C. Harding wrote:
> > (Note at bottom on reasons for 'To' list 'Cc' list)
> >
> > Hi,
> >
> > kobject_init_and_add() seems to be routinely misused. A failed call to this
> > func
On Sun, Apr 28, 2019 at 03:00:29AM +0900, Mark Brown wrote:
On Sat, Apr 27, 2019 at 12:31:22PM -0500, Gustavo A. R. Silva wrote:
On 4/27/19 12:14 PM, Mark Brown wrote:
> Are we *realy* going to enable -Wimplicit-fallthrough in stable kernels
> and both backport all the fixes and add new fixes
On Fri, 12 Apr 2019 at 16:09, Paolo Bonzini wrote:
>
> On 12/04/19 09:55, WANG Chao wrote:
> > guest xcr0 could leak into host when MCE happens in guest mode. Because
> > do_machine_check() could schedule out at a few places.
> >
> > For example:
> >
> > kvm_load_guest_xcr0
> > ...
> > kvm_x86_ops
Deepa Dinamani wrote:
> I tried to replicate the failure on qemu.
> I do not see the failure with N=32.
> Does it work for N < 32?
Depends on number of cores you have; I have 4 cores, 8 threads
with HT; so I needed to have a lot of load on the machine to get
it to fail (it takes about 1 minute).
There is currently some confusion on how to wind back
kobject_init_and_add() during the error paths in code that uses this
function.
Add documentation to kobject_add() and kobject_del() to help clarify the
usage.
Signed-off-by: Tobin C. Harding
---
The assumption is that this is the correct usa
The cpu-map DT entry in ARM can describe the CPU topology in much better
way compared to other existing approaches. RISC-V can easily adopt this
binding to represent its own CPU topology. Thus, both cpu-map DT
binding and topology parsing code can be moved to a common location so
that RISC-V or any
cpu-map binding can be used to described cpu topology for both
RISC-V & ARM. It makes more sense to move the binding to document
to a common place.
The relevant discussion can be found here.
https://lkml.org/lkml/2018/11/6/19
Signed-off-by: Atish Patra
Reviewed-by: Sudeep Holla
Reviewed-by: Rob
Both RISC-V & ARM64 are using cpu-map device tree to describe
their cpu topology. It's better to move the relevant code to
a common place instead of duplicate code.
Signed-off-by: Atish Patra
Tested-by: Jeffrey Hugo
---
arch/arm64/include/asm/topology.h | 23 ---
arch/arm64/kernel/topology.c
Currently, ARM32 and ARM64 uses different data structures to represent
their cpu toplogies. Since, we are moving the ARM64 topology to common
code to be used by other architectures, we can reuse that for ARM32 as
well.
Take this opprtunity to remove the redundant functions from ARM32 and
reuse the
Currently, there are no topology defined for RISC-V.
Parse the cpu-map node from device tree and setup the
cpu topology.
CPU topology after applying the patch.
$cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-3
$cat /sys/devices/system/cpu/cpu3/topology/core_siblings_list
0-3
$cat /
From: Sudeep Holla
The current ARM DT topology description provides the operating system
with a topological view of the system that is based on leaf nodes
representing either cores or threads (in an SMT system) and a
hierarchical set of cluster nodes that creates a hierarchical topology
view of h
Function kobject_init_and_add() is currently misused in a number of
places in the kernel. On error return kobject_put() must be called but
is at times not.
Make the function documentation more explicit about calling
kobject_put() in the error path.
Signed-off-by: Tobin C. Harding
---
lib/kobje
Currently error return from kobject_init_and_add() is not followed by a
call to kobject_put(). This means there is a memory leak.
Add call to kobject_put() in error path of kobject_init_and_add().
Signed-off-by: Tobin C. Harding
---
mm/slub.c | 4 +++-
1 file changed, 3 insertions(+), 1 deleti
On Sat, Apr 27, 2019 at 09:28:09PM +0200, Greg Kroah-Hartman wrote:
> On Sat, Apr 27, 2019 at 06:13:30PM +1000, Tobin C. Harding wrote:
> > (Note at bottom on reasons for 'To' list 'Cc' list)
> >
> > Hi,
> >
> > kobject_init_and_add() seems to be routinely misused. A failed call to this
> > func
I tried to replicate the failure on qemu.
I do not see the failure with N=32.
Does it work for N < 32?
Does any other signal work?
Are there any other architectures that fail?
Could you help me figure out how to run just the one test that is failing?
-Deepa
Hi Linus,
Please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git for-linus
to receive updates for the input subsystem. Just a couple of fixups for
Synaptics RMI4 driver and allowing snvs_pwrkey to be selected on more
boards.
Changelog:
-
Jacky Bai (1):
Thanks, man!
On 14:44 Sat 27 Apr , Greg KH wrote:
I'm announcing the release of the 5.0.10 kernel.
All users of the 5.0 kernel series must upgrade.
The updated 5.0.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-5.0.y
and can be b
Add the capability to configure LDPC mode via the ioctl
XSDFEC_ADD_LDPC_CODE_PARAMS.
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 333 +++
include/uapi/misc/xilinx_sdfec.h | 119 +++
Add char device interface per DT node present and support
file operations:
- open(),
- close(),
- unlocked_ioctl(),
- compat_ioctl().
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 78 +++
Add SD-FEC driver documentation.
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
Documentation/misc-devices/index.rst| 1 +
Documentation/misc-devices/xilinx_sdfec.rst | 291
2 files changed, 292 insertions(+)
create mode 100644 Documentatio
Stores configuration based on parameters from the DT
node and values from the SD-FEC core plus reads
the default state from the SD-FEC core. To obtain
values from the core register read, write capabilities
have been added plus related register map details.
Tested-by: Dragan Cvetic
Signed-off-by:
Support monitoring and detecting the SD-FEC error events
through IRQ and poll file operation.
The SD-FEC device can detect one-error or multi-error events.
An error triggers an interrupt which creates and run the ONE_SHOT
IRQ thread.
The ONE_SHOT IRQ thread detects type of error and pass that
info
Implements an platform driver that matches with xlnx,
sd-fec-1.1 device tree node and registers as a character
device, including:
- SD-FEC driver binds to sdfec DT node.
- creates and initialise an initial driver dev structure.
- add the driver in Linux build and Kconfig.
Tested-by: Dragan Cvetic
mode
Add the capability to configure and retrieve turbo mode
via the ioctls XSDFEC_SET_TURBO and XSDFEC_GET_TURBO.
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 77
include/uap
Add the Soft Decision Forward Error Correction (SDFEC) Engine
bindings which is available for the Zynq UltraScale+ RFSoC
FPGA's.
Signed-off-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
---
.../devicetree/bindings/misc/xlnx,sd-fec.txt | 58 ++
1 file changed, 58 inser
This patchset is adding the full Soft Decision Forward Error
Correction (SD-FEC) driver implementation, driver DT binding and
driver documentation.
Forward Error Correction (FEC) codes such as Low Density Parity
Check (LDPC) and turbo codes provide a means to control errors in
data transmissions o
- Add capability to get SD-FEC config data using ioctl
XSDFEC_GET_CONFIG.
- Add capability to set SD-FEC data order using ioctl
SDFEC_SET_ORDER.
- Add capability to set SD-FEC bypass option using ioctl
XSDFEC_SET_BYPASS.
- Add capability to set SD-FEC active state using ioctl
XSDFEC_IS_ACTIVE.
support
Add maintainer entry for Xilinx SD-FEC driver support.
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
MAINTAINERS | 12
1 file changed, 12 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b8d72ee..14e9335 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
SD-FEC statistic data are:
- count of data interface errors (isr_err_count)
- count of Correctable ECC errors (cecc_count)
- count of Uncorrectable ECC errors (uecc_count)
Add support:
1. clear stats ioctl callback which clears collected
statistic data,
2. get stats ioctl callback which reads a co
Add the support for Linux Clock Control Framework (CCF).
Registers and enables clocks with the Clock Control
Framework (CCF), to prevent shared clocks from been
disabled.
Tested-by: Dragan Cvetic
Signed-off-by: Derek Kiernan
Signed-off-by: Dragan Cvetic
---
drivers/misc/xilinx_sdfec.c | 154 ++
On Fri, Apr 19, 2019 at 02:45:16AM +0200, Borislav Petkov wrote:
> On Fri, Apr 19, 2019 at 08:35:36AM +0800, PanBian wrote:
> > Yes, I see that. Because the loop start with (--i), there is no put
> > operation for the device that fails to create. So, I think we cannot
> > rule out the possibility o
On Fri, Apr 26, 2019 at 03:02:08PM -0400, Joel Savitz wrote:
> In the mainline kernel, there is no quick mechanism to get the virtual
> memory size of the current process from userspace.
>
> Despite the current state of affairs, this information is available to the
> user through several means, on
On Sat, Apr 27, 2019 at 6:24 AM Jonathan Cameron
wrote:
>
> On Sat, 27 Apr 2019 14:21:12 +0100
> Jonathan Cameron wrote:
>
> > On Wed, 24 Apr 2019 17:29:32 -0700
> > Gwendal Grignou wrote:
> >
> > > Add a IIO driver that reports the angle between the lid and the base for
> > > ChromeOS convertib
On Thu, Apr 25, 2019 at 06:50:55PM +0200, Oleg Nesterov wrote:
> With this patch rcu_sync has a single state variable and the transition rules
> become really simple:
>
> GP_IDLE - owned by the first rcu_sync_enter() which moves it to
>
> GP_ENTER - owned by rcu-callback which move
On Sat, Apr 27, 2019 at 5:06 PM Lukasz Majewski wrote:
> > 27.04.2019 в 00:46:53 +0200 Lukasz Majewski написал:
> > (I am wondering whether such trucation is undefined behaviour in C
>
> According to [1] - Chapter 6.3.1.3 - Point 3 it is
> implementation-defined.
The kernel relies on the sane beh
On 04/23/2019 01:48 PM, Vignesh Raghavendra wrote:
> Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
> IP is pretty simple and provides direct memory mapped access to
> connected Flash devices.
>
> Add basic support for the IP without DMA. Second chipSelect is not
> suppo
On Tue, Apr 23, 2019 at 3:37 PM Neil Armstrong wrote:
>
> For the PWM controller in the Meson G12A SoC, the EE domain and AO domain
> have different clock sources. This patch tries to describe them in the
> DT compatible data. The two AO PWM controller has different clock source,
> but the first A
On Tue, Apr 23, 2019 at 3:37 PM Neil Armstrong wrote:
>
> Update the doc to explicitly support Meson G12A Family.
> The 2 first (A & B) AO PWM uses different clock source than the last 2
> (C & D) AO PWM modules, thus we need to differentiate them.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: M
Hi Neil,
On Tue, Apr 23, 2019 at 11:16 AM Neil Armstrong wrote:
>
> This patch adds basic support for :
> - Amlogic G12B, which is very similar to G12A
> - The HardKernel Odroid-N2 based on the S922X SoC
>
> The Amlogic G12B SoC is very similar with the G12A SoC, sharing
> most of the features an
On Tue, Apr 23, 2019 at 11:16 AM Neil Armstrong wrote:
>
> Add compatible for the Amlogic G12B (S922X) SoC based Odroid-N2 SBC
> from HardKernel.
nit-pick: their website mentions "Copyright 2018 Hardkernel co., Ltd. "
> Signed-off-by: Neil Armstrong
> Reviewed-by: Rob Herring
Reviewed-by: Marti
On Tue, Apr 23, 2019 at 11:16 AM Neil Armstrong wrote:
>
> Add compatible for the Amlogic G12B SoC, sharing most of the
> features and architecture with the G12A SoC.
>
> Signed-off-by: Neil Armstrong
> Reviewed-by: Rob Herring
Reviewed-by: Martin Blumenstingl
On Tue, Apr 23, 2019 at 11:15 AM Neil Armstrong wrote:
>
> This patch support for the specific Amlogic G12B clocks.
>
> G12B clock driver is very close, the main differences are :
> - the clock tree is duplicated for the both clusters, and the
> SYS_PLL are swapped between the clusters
> - G12A
On Tue, Apr 23, 2019 at 11:15 AM Neil Armstrong wrote:
>
> This patch adds the specific Amlogic G12B clock driver compatible.
>
> G12B clock driver is very close, the main differences are :
> - the clock tree is duplicated for the both clusters, and the
> SYS_PLL are swapped between the clusters
Am 23.04.19 um 16:47 schrieb Madhumitha Prabakaran:
> Remove unnecessary variable from the function and make a corresponding
> change w.r.t the variable. In addition to that align the parameters in
> the parentheses to maintain Linux kernel coding style
>
> Issue suggested by Coccinelle.
>
> Signed
On Tue, Apr 23, 2019 at 11:03 AM Jerome Brunet wrote:
>
> This remove all the code related to phase settings. Using the Rx phase
> for tuning has not been reliable. We had several issues over the past
> months, on both v2 and v3 mmc chips After discussing the issue matter
> with Amlogic, They sugg
On Tue, Apr 23, 2019 at 11:03 AM Jerome Brunet wrote:
>
> Use signal resampling tuning for the UHS and HS200 modes.
> Instead of trying to get the *best* resampling setting with complex
> window calculation, we just stop on the first working setting.
>
> If the tuning setting later proves unstable
On Tue, Apr 23, 2019 at 11:03 AM Jerome Brunet wrote:
>
> Activating DDR in the Amlogic mmc controller, among other things, will
> divide the output clock by 2. So by activating it with clock on, we are
> creating a glitch on the output.
>
> Instead, let's deal with DDR when the clock output is of
On Sat, Apr 27, 2019 at 02:13:02PM -0500, f...@fredlawl.com wrote:
> Hotplug useses custom ctrl_*() dev_*() printk wrappers for logging
> messages. To make hotplug conform to pci logging, replace uses of these
> wrappers with pci_*() printk wrappers. In addition, replace any
> printk() calls with p
Hi Jerome,
On Tue, Apr 23, 2019 at 11:03 AM Jerome Brunet wrote:
>
> At the moment, all our attempts to enable HS400 on Amlogic chipsets have
> been unsuccessful or unreliable. Until we can figure out how to enable this
> mode safely and reliably, let's force it off.
last year I have seen issues
On 19-04-25 08:53:33, Stephen Boyd wrote:
> Caution: EXT Email
>
> Quoting Abel Vesa (2019-04-24 00:13:48)
> >
> > Can you please be more specific and point out exactly which one isn't ?
>
> Is this a question for me?
>
Nevermind. I'll send another version in the following days.
> >
> > >
> >
Am 27.04.19 um 18:07 schrieb Vatsala Narang:
> Modify return statement and remove the respective assignment.
>
> Issue found by Coccinelle.
>
> Signed-off-by: Vatsala Narang
Acked-by: Stefan Wahren
On Tue, Apr 23, 2019 at 11:02 AM Jerome Brunet wrote:
>
> There is no reason for another device to request the MMC irq. It should
> only be used the MMC device, so remove IRQ_SHARED and replace by
> IRQ_ONESHOT as we don't the irq to fire again until the irq thread is
> done
>
> Signed-off-by: Jer
On Tue, Apr 23, 2019 at 11:02 AM Jerome Brunet wrote:
>
> This is merely a clean up. It makes sense to only ack raised irqs
> instead of acking everything all the time.
>
> Signed-off-by: Jerome Brunet
based on reading (and understanding) the code and a test on my Khadas
VIM this seems fine so:
A
Hi Linus,
On Tue, Apr 23, 2019 at 1:13 PM Linus Walleij wrote:
>
> On Thu, Apr 18, 2019 at 2:48 PM Guillaume La Roque
> wrote:
>
> > The purpose of this patchset is to add drive-strength support in meson
> > pinconf
> > driver. This is a new feature that was added on the g12a. It is critical
>
Hi Guillaume,
On Thu, Apr 18, 2019 at 2:48 PM Guillaume La Roque
wrote:
>
> drive-strength-uA is a new feature needed for G12A SoC.
> the default DS setting after boot is usually 500uA and it is not enough for
> many functions. We need to be able to set the drive strength to reliably
> enable thi
Add support to power and output level control for the analog high power
output drivers HPOUT and HPCOM.
Signed-off-by: Saravanan Sekar
---
sound/soc/codecs/tlv320aic3x.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
inde
On Sat, Apr 27, 2019 at 06:13:30PM +1000, Tobin C. Harding wrote:
> (Note at bottom on reasons for 'To' list 'Cc' list)
>
> Hi,
>
> kobject_init_and_add() seems to be routinely misused. A failed call to this
> function requires a call to kobject_put() otherwise we leak memory.
>
> Examples meml
Hi Guillaume,
On Thu, Apr 18, 2019 at 2:48 PM Guillaume La Roque
wrote:
>
> Add optional drive-strength-uA property
>
> Signed-off-by: Guillaume La Roque
> ---
> Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation
On Thu, Apr 18, 2019 at 2:48 PM Guillaume La Roque
wrote:
>
> This property allow drive-strength parameter in uA instead of mA.
>
> Signed-off-by: Guillaume La Roque
personally I'm happy with this if the DT maintainers give their ACK.
based on that:
Acked-by: Martin Blumenstingl
From: Frederick Lawler
Now that all uses for the ctrl_*() printk wrappers are removed from
files and replaces with pci_*() or pr_*() printk wrappers, remove the
unused macro definitions. In addition to that, remove the MY_NAME macro.
Signed-off-by: Frederick Lawler
---
drivers/pci/hotplug/pcie
From: Frederick Lawler
Replace remaining instances of dev_*() printk wrappers with pci_*()
printk wrappers. No functional change intended.
Signed-off-by: Frederick Lawler
---
drivers/pci/pcie/aer.c| 13 ++---
drivers/pci/pcie/aer_inject.c | 4 ++--
drivers/pci/pcie/dpc.c
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