On Tue, 2018-02-06 at 08:44 +0100, Oleksandr Natalenko wrote:
> Hi, Paolo.
>
> I can confirm that this patch fixes cfdisk hang for me. I've also tried
> to trigger the issue Mike has encountered, but with no luck (maybe, I
> wasn't insistent enough, just was doing dd on usb-storage device in the
On Mon, Feb 5, 2018 at 11:26 PM, Ingo Molnar wrote:
>
> * Dan Williams wrote:
>
>> From: Andi Kleen
>>
>> At entry userspace may have populated registers with values that could
>> be useful in a speculative execution attack. Clear them to minimize the
>> kernel's attack surface.
>>
>> [djbw: int
Hi Dan,
On 02/04/18 15:05 -0800, Dan Williams wrote:
> Filesystem-DAX is incompatible with 'longterm' page pinning. Without
> page cache indirection a DAX mapping maps filesystem blocks directly.
> This means that the filesystem must not modify a file's block map while
> any page in a mapping is p
Hi, Paolo.
I can confirm that this patch fixes cfdisk hang for me. I've also tried
to trigger the issue Mike has encountered, but with no luck (maybe, I
wasn't insistent enough, just was doing dd on usb-storage device in the
VM).
So, with regard to cfdisk hang on usb-storage:
Tested-by: Ole
On 05/02/18 11:11, Mathieu Poirier wrote:
> On 2 February 2018 at 03:19, Juri Lelli wrote:
> > Hi Mathieu,
> >
> > On 01/02/18 09:51, Mathieu Poirier wrote:
> >> Introducing function partition_sched_domains_locked() by taking
> >> the mutex locking code out of the original function. That way
> >>
Add documentation for sysfs interface of adp8860 series backlight
devices by reading through code and git commits.
Signed-off-by: Aishwarya Pant
Acked-by: Michael Hennerich
---
.../ABI/testing/sysfs-class-backlight-adp8860 | 54 ++
1 file changed, 54 insertions(+)
crea
2018-01-18 18:28 GMT+08:00 Arnd Bergmann :
> On Mon, Jan 15, 2018 at 6:53 AM, Greentime Hu wrote:
>> From: Greentime Hu
>>
>> This patch adds VDSO support. The VDSO code is currently used for
>> sys_rt_sigreturn() and optimised gettimeofday() (using the SoC timer
>> counter).
>>
>> Signed-off-by
Add documentation for sysfs interface of adp5520/adp5501 analog devices
backlight driver by reading code and looking through git commit logs.
Signed-off-by: Aishwarya Pant
Acked-by: Michael Hennerich
---
.../ABI/testing/sysfs-class-backlight-adp5520 | 31 ++
1 file chan
Add documentation for sysfs interfaces of Texas Instruments lm3639
backlight + flash led driver chip by looking through git commits and
reading code.
Signed-off-by: Aishwarya Pant
Acked-by: Daniel Thompson
---
Changes in v2:
- Update contact information
Documentation/ABI/testing/sysfs-class-ba
Patchset contains documentation of the sysfs interfaces for the
following five backlight drivers-
1) lm3639
2) adp5520
3) adp8860
It was compiled from data sheets, reading code and git history logs. In v2 of
the patches, documentation for lp8788 and lp855x devices was dropped as the
attributes con
On Mon, Feb 05, 2018 at 12:56:04PM +0100, Linus Walleij wrote:
> On Mon, Feb 5, 2018 at 9:47 AM, Ludovic Desroches
> wrote:
>
> > Use GPIO descriptors instead of relying on the old method.
> >
> > Signed-off-by: Ludovic Desroches
>
> Ah there it is :D
> Reviewed-by: Linus Walleij
>
> PS: why
Use GPIO descriptors instead of relying on the old method.
Signed-off-by: Ludovic Desroches
Acked-by: Nicolas Ferre
Reviewed-by: Linus Walleij
Reviewed-by: Andy Shevchenko
---
Changes
- V2:
- remove of_gpio.h.
- move gpiod declaration to preserve reversed tree style.
- use devm_gpiod_get
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 342
The Tegra194 BPMP only implements 5 channels (4 to BPMP, 1 to CCPLEX),
and they are not placed contiguously in memory. The current channel
management in the BPMP driver does not support this.
Simplify and refactor the channel management such that only one atomic
transmit channel and one receive ch
The Tegra194 power management controller has one additional register
aperture to be specified in the device tree node.
Signed-off-by: Mikko Perttunen
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --
Hello everyone,
this series adds initial support for the NVIDIA Tegra194 "Xavier"
system-on-chip. Initially UART, I2C, SDMMC, as well as the PMIC
are supported, allowing booting to a console.
The changes consist almost completely of the new device trees,
however some fixes are required in the BPM
Add compatibility strings for supported but undocumented Tegra chips
(Tegra114/124/132/210/186/194) and reference boards.
Signed-off-by: Mikko Perttunen
---
Notes:
v2:
- add patch
Documentation/devicetree/bindings/arm/tegra.txt | 16
1 file changed, 16 insertions(+)
d
Add device tree files for the Tegra194 P2972- development board.
The board consists of the P2888 compute module and the P2822 baseboard.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248 +++
The Tegra194 PMC is mostly compatible with Tegra186, including in all
currently supported features. As such, add a new compatibility string
but point to the existing Tegra186 SoC data for now.
Signed-off-by: Mikko Perttunen
---
drivers/soc/tegra/pmc.c | 1 +
1 file changed, 1 insertion(+)
diff
Add the configuration option to enable support for the Tegra194
system-on-chip, and enable it by default in the arm64 defconfig.
Signed-off-by: Mikko Perttunen
---
arch/arm64/configs/defconfig | 1 +
drivers/soc/tegra/Kconfig| 10 ++
2 files changed, 11 insertions(+)
diff --git a/a
* Dan Williams wrote:
> From: Andi Kleen
>
> At entry userspace may have populated registers with values that could
> be useful in a speculative execution attack. Clear them to minimize the
> kernel's attack surface.
>
> [djbw: interleave the clearing with setting up the stack ]
> Cc: Thomas
Hi,
On 06/02/18 09:55, Wen Yang wrote:
> rq->clock_task may be updated between the two calls of
> rq_clock_task() in update_curr_dl(). Calling rq_clock_task() only
> once makes it more accurate and efficient, taking update_curr() as
> reference.
>
> Signed-off-by: Wen Yang
> Reviewed-by: Jiang B
Add documentation for core and hardware specific infiniband interfaces.
The descriptions have been collected from git commit logs, reading
through code and data sheets. Some drivers have incomplete doc and are
annotated with the comment '[to be documented]'.
Signed-off-by: Aishwarya Pant
---
Chan
On 2018/2/6 14:37, Yang Shunyong wrote:
> Loading IORT table from initrd can be used to fix severe firmware
> IORT defects temporarily before platform/BIOS vendor releases an
> upgraded BIOS binary.
>
> Moreover, it is very powerful to debug SMMU node/device probe, MSI
> allocation, stream id tran
* Andi Kleen wrote:
> > - There's various conditional pieces of entry code that run before any
> >RBP-clobbering C function is called. While none of them has an
> > exploitable
> >Spectre 'gadget' at the moment, we'd have to consider this for every
> > future
> >
On 2/5/2018 4:08 PM, Bogdan Purcareata wrote:
> Move the source files out of staging into their final locations:
> -mc.h include file in drivers/staging/fsl-mc/include go to include/linux/fsl
> -source files in drivers/staging/fsl-mc/bus go to drivers/bus/fsl-mc
> -overview.rst, providing an
On Mon, Feb 5, 2018 at 6:39 PM, Joel Fernandes wrote:
> This patch detaches the preemptirq tracepoints from the tracers and
> keeps it separate. With this, several ifdefs are cleaner, and lockdep
> and other users can use the preemptirq tracepoints by registering probes
> onto them. This makes it
On Mon, Feb 05, 2018 at 10:25:54PM -0600, Alan Tull wrote:
> On Mon, Feb 5, 2018 at 7:47 PM, Wu Hao wrote:
> > On Mon, Feb 05, 2018 at 10:36:45AM -0800, Luebbers, Enno wrote:
> >> Hi Hao,
> >>
> >> On Sun, Feb 04, 2018 at 05:37:06PM +0800, Wu Hao wrote:
> >> > On Fri, Feb 02, 2018 at 04:26:26PM -0
From: Huang Ying
It was reported by Sergey Senozhatsky that if THP (Transparent Huge
Page) and frontswap (via zswap) are both enabled, when memory goes low
so that swap is triggered, segfault and memory corruption will occur
in random user space applications as follow,
kernel: urxvt[338]: segfau
On Mon, Feb 5, 2018 at 10:50 PM, Joel Fernandes wrote:
> On Wed, Jan 31, 2018 at 9:50 AM, Rohit Jain wrote:
>>kernel/sched/fair.c | 38 --
>>1 file changed, 28 insertions(+), 10 deletions(-)
>>
>> diff --git a/kernel/sched/fair.c b/kernel
On Wed, Jan 31, 2018 at 9:50 AM, Rohit Jain wrote:
>kernel/sched/fair.c | 38 --
>1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index 26a71eb..ce5ccf8 100644
> --- a/
On Mon, Feb 05, 2018 at 10:25:27PM -0600, Alan Tull wrote:
> On Mon, Feb 5, 2018 at 8:17 PM, Wu Hao wrote:
> > On Mon, Feb 05, 2018 at 11:21:52AM -0600, Alan Tull wrote:
> >> On Sun, Feb 4, 2018 at 4:05 AM, Wu Hao wrote:
> >> > On Sat, Feb 03, 2018 at 11:41:24AM +0100, Moritz Fischer wrote:
> >>
On Tue, Jan 30, 2018 at 11:47 AM, Rohit Jain wrote:
[...]
>>> @@ -6102,7 +6107,8 @@ static int select_idle_core(struct task_struct *p,
>>> struct sched_domain *sd, int
>>>*/
>>> static int select_idle_smt(struct task_struct *p, struct sched_domain
>>> *sd, int target)
>>> {
>>> - int
Loading IORT table from initrd can be used to fix severe firmware
IORT defects temporarily before platform/BIOS vendor releases an
upgraded BIOS binary.
Moreover, it is very powerful to debug SMMU node/device probe, MSI
allocation, stream id translation and IORT table from firmware.
It is also ve
Thanks, I got it.
After referring to arm64 and risc-v, we try to refine our code, such as
removing unneeded checking and refining syscall restart flow. We
hope these modifications can enhance the reliability and readability.
However, the following 2 files which you had acked are included in
this m
Hi Abhishek,
On 2/3/2018 5:07 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 14 ++
>> 2 files changed, 15 insertio
Hi Abhishek,
On 2/3/2018 5:00 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 8
>> 2 files changed, 9 insertions(+)
>>
Hi Abhishek,
On 2/3/2018 4:47 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> Add the common parts for the dk04 boards.
>>
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 147
>
>
>> +
>> + nand_pins: nand_pins {
>> +
Hi Abhishek,
On 2/3/2018 4:25 PM, Abhishek Sahu wrote:
> On 2018-01-29 10:41, Sricharan R wrote:
>> The board has a spi-nand interface on spi0 bus chipselect1.
>>
>> Signed-off-by: Sricharan R
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq4019-ap.
Ram Pai writes:
> On Fri, Feb 02, 2018 at 12:27:27PM +0800, kbuild test robot wrote:
>> Hi Ram,
>>
>> Thank you for the patch! Yet something to improve:
>>
>> [auto build test ERROR on linus/master]
>> [also build test ERROR on v4.15 next-20180201]
>> [if your patch is applied to the wrong git
On Tue, 2018-02-06 at 15:50 +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2018-02-06 at 12:31 +0800, Ryder Lee wrote:
> > On Tue, 2018-02-06 at 15:05 +1100, Benjamin Herrenschmidt wrote:
> > > On Tue, 2018-02-06 at 10:38 +0800, Ryder Lee wrote:
> > > >
> > > > I think the code should look at the
On Mon, Feb 05, 2018 at 10:25:27PM -0600, Alan Tull wrote:
> On Mon, Feb 5, 2018 at 8:17 PM, Wu Hao wrote:
> > On Mon, Feb 05, 2018 at 11:21:52AM -0600, Alan Tull wrote:
> >> On Sun, Feb 4, 2018 at 4:05 AM, Wu Hao wrote:
> >> > On Sat, Feb 03, 2018 at 11:41:24AM +0100, Moritz Fischer wrote:
> >>
On Mon, Feb 5, 2018 at 4:28 PM, Shawn Guo wrote:
> On Sun, Feb 04, 2018 at 11:19:24PM +0530, Jagan Teki wrote:
>> Series adda LVDS panel attributes on panel drivers instead of defining
>> them in dts nodes, and also added new icorem6 engicam boards.
>>
>> Jagan Teki (7):
>> drm/panel: simple: ad
Orange Pi One board has a SY8113B regulator, which is controlled via
GPIO and capable of outputing 1.1V when the PL6 GPIO is set to output 0
or 1.3V when the PL6 GPIO is set to input or output 1, and the output is
the power supply of the ARM cores in H3 SoC.
Add the device tree node of this regula
From: Ondrej Jirman
Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on
Orange Pi PC, then set the power supply of the ARM cores to this
regulator, in order to enable DVFS.
Signed-off-by: Ondrej Jirman
[Icenowy: Enable DVFS in this patch, slight changes and change commit
message]
Si
The ALL-H3-CC has a fixed VDD-CPUX voltage at 1.2V, which is supplied
by a regulator.
Set the CPU's cpu-supply property to the VDD-CPUX regulator.
Signed-off-by: Icenowy Zheng
---
New patch in v2.
arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 4
1 file changed, 4 insertions(+)
dif
On Tue, 2018-02-06 at 12:31 +0800, Ryder Lee wrote:
> On Tue, 2018-02-06 at 15:05 +1100, Benjamin Herrenschmidt wrote:
> > On Tue, 2018-02-06 at 10:38 +0800, Ryder Lee wrote:
> > >
> > > I think the code should look at the bridge address <0x0800 ...> we list
> > > in bindings for resolving interru
Orange Pi Zero board has a SY8113B regulator, which is controlled via
GPIO and capable of outputing 1.1V when the PL6 GPIO is set to output 0
or 1.3V when the PL6 GPIO is set to input or output 1, and the output is
the power supply of the ARM cores in H2+ SoC.
Add the device tree node of this regu
The CPU on Allwinner H3 can do dynamic frequency scaling.
Add a DVFS table based on the one shipped with Allwinner's H3 SDK. The
voltage-frequency relationship seems to be conservative, and Armbian has
another DVFS table which uses lower voltage at a certain frequency.
However, the official one is
The VDD-CPUX voltage of ALL-H3-CC H3 ver should be 1.2V, not the 3.3V
currently defined in the device tree.
Fix the voltage in the device tree.
Fixes: 6ca358645d4d ("ARM: dts: sun8i: h3: Add dts file for Libre Computer
Board ALL-H3-CC H3 ver.")
Signed-off-by: Icenowy Zheng
---
New patch in v2.
From: Ondrej Jirman
Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.
Add support for it in the device tree.
Signed-off-by: Ondrej Jirman
[Icenowy: Change to use r_ccu and change pinmux node name]
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v2:
- Added Ch
From: Ondrej Jirman
H3/H5 SoCs contain an I2C controller optionally available
on the PL0 and PL1 pins. This patch adds pinmux configuration
for this controller.
Signed-off-by: Ondrej Jirman
[Icenowy: change commit message, node name and function name]
Signed-off-by: Icenowy Zheng
Reviewed-by:
From: Ondrej Jirman
SY8106A is an I2C attached single output regulator made by Silergy Corp,
which is used on several Allwinner H3/H5 SBCs to control the power
supply of the ARM cores.
Add a driver for it.
Signed-off-by: Ondrej Jirman
[Icenowy: Change commit message, remove enable/disable code
From: Ondrej Jirman
SY8106A is an I2C-controlled adjustable voltage regulator made by
Silergy Corp.
Add its device tree binding.
Signed-off-by: Ondrej Jirman
[Icenowy: Change commit message and slight fixes]
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Ch
This patchset tries to add DVFS support for Allwinner H3 SoC,
considering two kinds of adjustable regulators used on H3 boards:
SY8106A I2C-controlled regulator and SY8113B regulator (controllable
by GPIO with some special designs on the board), and also taking the
uncontrollable boards into consid
Hi Rob,
On 2/5/2018 11:37 AM, Rob Herring wrote:
> On Mon, Jan 29, 2018 at 10:41:15AM +0530, Sricharan R wrote:
>> Add the compatible for ipq4019.
>> This does not need clocks to do scm calls.
>>
>> Signed-off-by: Sricharan R
>> ---
>> Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3
Hi Viresh,
On 2/6/2018 9:57 AM, Viresh Kumar wrote:
> On 06-02-18, 09:38, Sricharan R wrote:
>> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
>> that has KRAIT processors the voltage/current value of each OPP
>> varies based on the silicon variant in use.
>> operating-points-v2-krai
Hi Bjorn,
Can you please have a look at this patch?
Regards,
Anup
Hi Bjorn,
Can you please have a look at this patch?
Regards,
Anup
Hi Viresh,
On 2/6/2018 9:56 AM, Viresh Kumar wrote:
> On 06-02-18, 09:38, Sricharan R wrote:
>> diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
>> new file mode 100644
>> index 000..5b988d4
>> --- /dev/null
>> +++ b/drivers/cpufreq/qcom-cpufreq.c
>> @@ -0,0 +1,161
On Tue, 2018-02-06 at 15:05 +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2018-02-06 at 10:38 +0800, Ryder Lee wrote:
> >
> > I think the code should look at the bridge address <0x0800 ...> we list
> > in bindings for resolving interrupts in this case, but it seems like it
> > use the 'pdev->defv
On 05-02-18, 11:32, Daniel Lezcano wrote:
> On 05/02/2018 05:17, Viresh Kumar wrote:
> > Right, but I thought the cooling-maps can help us specify different cooling
> > states for different cooling devices for the same trip point. Maybe my
> > understanding of that is incorrect.
Any inputs on this
On 06-02-18, 09:38, Sricharan R wrote:
> In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
> that has KRAIT processors the voltage/current value of each OPP
> varies based on the silicon variant in use.
> operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
> and the
On 06-02-18, 09:38, Sricharan R wrote:
> diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
> new file mode 100644
> index 000..5b988d4
> --- /dev/null
> +++ b/drivers/cpufreq/qcom-cpufreq.c
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c)
On Mon, Feb 5, 2018 at 7:47 PM, Wu Hao wrote:
> On Mon, Feb 05, 2018 at 10:36:45AM -0800, Luebbers, Enno wrote:
>> Hi Hao,
>>
>> On Sun, Feb 04, 2018 at 05:37:06PM +0800, Wu Hao wrote:
>> > On Fri, Feb 02, 2018 at 04:26:26PM -0800, Luebbers, Enno wrote:
>> > > Hi Hao, Alan,
>> > >
>> > > On Fri, F
On Mon, Feb 5, 2018 at 8:17 PM, Wu Hao wrote:
> On Mon, Feb 05, 2018 at 11:21:52AM -0600, Alan Tull wrote:
>> On Sun, Feb 4, 2018 at 4:05 AM, Wu Hao wrote:
>> > On Sat, Feb 03, 2018 at 11:41:24AM +0100, Moritz Fischer wrote:
>> >> Hi Hao,
>> >>
>> >> On Fri, Feb 02, 2018 at 04:26:26PM -0800, Lueb
Hi Paolo,
I applied this to master.today, flipped udev back to bfq and took it
for a spin. Unfortunately, box fairly quickly went boom under load.
[ 454.739975] [ cut here ]
[ 454.739979] list_add corruption. prev->next should be next
(5f99a42a), but was
From: Stephen Boyd
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc:
Signed-off
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +
.../devic
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to th
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
that has KRAIT processors the voltage/current value of each OPP
varies based on the silicon variant in use.
operating-points-v2-krait-cpu specifies the phandle to nvmem efuse cells
and the operating-points-v2 table for each opp. The qcom-
From: Stephen Boyd
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,krait-cc.txt| 22 ++
1
From: Stephen Boyd
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Cc:
[Sricharan: updated to use dev_pm_opp_set_prop_name, NVMEM apis,
new binding]
Signed-off-by: Sricharan R
Signed-off-by: Stephen Boyd
---
drivers/cpufre
From: Stephen Boyd
On some devices (MSM8974 for example), the HFPLLs are
instantiated within the Krait processor subsystem as separate
register regions. Add a driver for these PLLs so that we can
provide HFPLL clocks for use by the system.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/
From: Stephen Boyd
Describe the HFPLLs present on IPQ806X devices.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-ipq806x.c | 82 ++
1 file changed, 82 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
inde
From: Stephen Boyd
Describe the HFPLLs present on MSM8960 and APQ8064 devices.
Acked-by: Rob Herring (bindings)
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/gcc-msm8960.c | 172 +++
include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
2 files changed
From: Stephen Boyd
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc:
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Kconfig
From: Stephen Boyd
The Krait clocks are made up of a series of muxes and a divider
that choose between a fixed rate clock and dedicated HFPLLs for
each CPU. Instead of using mmio accesses to remux parents, the
Krait implementation exposes the remux control via cp15
registers. Support these clocks
From: Stephen Boyd
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd
---
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/clk-hfpll.c | 244 +++
drivers/clk/qcom/
From: Stephen Boyd
Adds bindings document for qcom,hfpll instantiated within
the Krait processor subsystem as separate register region.
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++
1 file changed, 46 i
From: Stephen Boyd
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' regi
From: Stephen Boyd
We want to reuse the logic in clk-mux.c for other clock drivers
that don't use readl as register accessors. Fortunately, there
really isn't much to the mux code besides the table indirection
and quirk flags if you assume any bit shifting and masking has
been done already. Pull
[v6]
* Adrressed comments from Viresh for patch #14 in v5 [5]
* Introduced a new binding operating-points-v2-krait-cpu
as per discussion with Rob
* Added Review tags
[v5]
* Addressed comments from Rob for bindings
* Addressed comments from Viresh to use dev_pm_opp_set_prop_name, acco
On 2018년 02월 05일 23:22, Sylwester Nawrocki wrote:
> The sclk_ioclk_i2s1_bclk clock is not currently handled by any driver
> and disabling this clock by the clk core prevents proper operation
> of the I2S1 block. CLK_IGNORE_UNUSED flag is added as a temporary fix.
>
> Signed-off-by: Sylwester Nawro
Hi Sylwester,
On 2018년 02월 05일 23:22, Sylwester Nawrocki wrote:
> CLK_SET_RATE_PARENT flag is added to definitions of clocks on a path
> starting from CLK_SCLK_I2S1 up to AUD_PLL in order to allow setting
> required audio root clock frequency for the I2S1 block. This is now
> only done for the I2S
On Tue, 2018-02-06 at 10:38 +0800, Ryder Lee wrote:
>
> I think the code should look at the bridge address <0x0800 ...> we list
> in bindings for resolving interrupts in this case, but it seems like it
> use the 'pdev->defvn << 8' which is not really we want and will lead to
> mismatch.
>
>
Hi Alexandre,
On 26 January 2018 at 17:24, Arnd Bergmann wrote:
> On Fri, Jan 26, 2018 at 6:06 AM, Baolin Wang wrote:
>> If we convert one large time values to rtc_time, in the original formula
>> 'days * 86400' can be overflowed in 'unsigned int' type to make the formula
>> get one incorrect re
This patch adds fi->commit_lock to avoid the case that GCed node pages
are committed but GCed data pages are not committed. This can avoid the
db file run into inconsistent state when sudden-power-off happens if
data pages of atomic file is allowed to be GCed before.
Signed-off-by: Yunlong Song
-
Hi all,
Please do not add any v4.17 material to your linux-next included branches
until after v4.16-rc1 has been released.
Changes since 20180205:
Linus' tree lost its build failure.
The tip tree gained conflicts against Linus' tree.
The akpm tree lost a patch that turned up elsew
0001-linux2.6.36-netfilter-conntrack-Fix-conntrack-table-full-error-w.patch
Description: Binary data
2018-02-06 2:48 GMT+00:00 Steven Rostedt :
> On Tue, 6 Feb 2018 02:44:03 +
> Dmitry Safonov <0x7f454...@gmail.com> wrote:
>
>
>> Yes, I've planned to do this..
>> As it's merge-window now I thought doing this a week later.
>> So, it's up to you - just let me know so we will not end doing the sa
Hi, Houlong:
I've some inline comment.
On Wed, 2018-01-31 at 15:28 +0800, houlong@mediatek.com wrote:
> From: "hs.l...@mediatek.com"
>
> Add Mediatek CMDQ helper to create CMDQ packet and assemble GCE op code.
>
> Signed-off-by: Houlong Wei
> Signed-off-by: HS Liao
> ---
> drivers/soc/m
On Mon, Feb 5, 2018 at 1:13 PM, Arnaldo Carvalho de Melo
wrote:
> Em Mon, Feb 05, 2018 at 12:58:16PM -0800, Stephane Eranian escreveu:
>> On Mon, Feb 5, 2018 at 7:17 AM, Jiri Olsa wrote:
>> > On Fri, Feb 02, 2018 at 01:04:34PM -0800, Stephane Eranian wrote:
>> >> On Fri, Feb 2, 2018 at 12:40 PM,
On Tue, 6 Feb 2018 02:44:03 +
Dmitry Safonov <0x7f454...@gmail.com> wrote:
> Yes, I've planned to do this..
> As it's merge-window now I thought doing this a week later.
> So, it's up to you - just let me know so we will not end doing the same fix :)
>
If you haven't done it already, I'll j
On Mon, Feb 05, 2018 at 04:08:19PM -0600, Alan Tull wrote:
> On Mon, Nov 27, 2017 at 12:42 AM, Wu Hao wrote:
>
> Hi Hao,
>
> A couple comments below.
>
> > For feature devices, e.g FPGA Management Engine (FME),
>
> The first use I see of this function in this patchset is the FME PR,
> not the
2017-11-13 22:40 GMT+08:00 Paolo Bonzini :
> Add the CPUID bits, make the CR4.UMIP bit not reserved anymore, and
> add UMIP support for instructions that are already emulated by KVM.
>
> Signed-off-by: Paolo Bonzini
> ---
> arch/x86/include/asm/kvm_host.h | 2 +-
> arch/x86/kvm/cpuid.c
Hi Sylwester,
When I developed the clk-exynos5433.c I referred to the following description.
TRM specified that "Samsung recommends only the values
between 252MH ~ 400MHz in the PMS2460X PMS value" for aud_pll.
It looks like that you refer to clk-exynos5420.c driver.
But, I'm wondering exynos5433
于 2018年2月3日 GMT+08:00 上午3:49:35, Maxime Ripard 写到:
>On Fri, Feb 02, 2018 at 10:01:52PM +0800, Icenowy Zheng wrote:
>> Allwinner V3s SoC features an internal audio codec like the one in
>H3,
>> and a analog codec like the one in H3/A23 (but much simpler).
>>
>> Add them in the DTSI file.
>>
>>
2018-02-06 2:40 GMT+00:00 Steven Rostedt :
> On Tue, 6 Feb 2018 11:26:14 +0900
> Masami Hiramatsu wrote:
>
>> No, that code looks good to me. :)
>>
>> BTW, did you also remove "search = buff;" line in
>> unregister_ftrace_function_probe_func() too?
>
> That's a separate bug, and should be a separa
On Tue, 6 Feb 2018 11:26:14 +0900
Masami Hiramatsu wrote:
> No, that code looks good to me. :)
>
> BTW, did you also remove "search = buff;" line in
> unregister_ftrace_function_probe_func() too?
That's a separate bug, and should be a separate patch. Dmitry mentioned
that he was preparing a pa
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