ARMv8.2 requires implementation of the RAS extension. In
this extension, it adds SEI(SError Interrupt) notification
type, this patch adds new GHES error source SEI handling
functions. This error source parsing and handling method
is similar with the SEA.
Expose API ghes_notify_sei() to external us
If it is not RAS SError, directly inject virtual SError,
which will keep the old way, otherwise firstly let host
ACPI kernel driver to handle it. If the ACPI handling is
failed, KVM continues categorizing errors by the ESR_ELx.
For the recoverable error (UER), it has not been silently
propagated a
The ARM64 RAS SError Interrupt(SEI) syndrome value is specific to the
guest and user space needs a way to tell KVM this value. So we add a
new ioctl. Before user space specifies the Exception Syndrome Register
ESR(ESR), it firstly checks that whether KVM has the capability to
set the guest ESR, If
From: Xie XiuQi
ARM's v8.2 Extentions add support for Reliability, Availability and
Serviceability (RAS). On CPUs with these extensions system software
can use additional barriers to isolate errors and determine if faults
are pending.
Add cpufeature detection and a barrier in the context-switch
ARMv8.2 adds a new bit HCR_EL2.TEA which routes synchronous external
aborts to EL2, and adds a trap control bit HCR_EL2.TERR which traps
all Non-secure EL1&0 error record accesses to EL2.
This patch enables the two bits for the guest OS, guaranteeing that
KVM takes external aborts and traps attemp
From: James Morse
When we exit a guest due to an SError the vcpu fault info isn't updated
with the ESR. Today this is only done for traps.
The v8.2 RAS Extensions define ISS values for SError. Update the vcpu's
fault_info with the ESR on SError so that handle_exit() can determine
if this was a R
On 01/05/2018 10:53 PM, Hanjun Guo wrote:
>> + /*
>> +* PTI poisons low addresses in the kernel page tables in the
>> +* name of making them unusable for userspace. To execute
>> +* code at such a low address, the poison must be cleared.
>> +*/
>> + pgd->pgd &= ~_PAGE_NX;
On 01/05/2018 10:28 PM, Hanjun Guo wrote:
>> +
>> p4d = p4d_alloc(&tboot_mm, pgd, vaddr);
> Seems pgd will be re-set after p4d_alloc(), so should
> we put the code behind (or after pud_alloc())?
Yes, it has to go below where the PGD actually gets set which is
after pud_alloc(). You can put
On 1/6/2018 2:35 AM, Alan Cox wrote:
On Sat, 6 Jan 2018 01:54:36 +0530
"Kohli, Gaurav" wrote:
Hi Alan,
Sorry correcting the typo here:
+retval = tty_ldisc_lock(tty, 5 * HZ);
+if (retval)
+ goto err_release_lock;
tty->port->itty = tty;
/*
* Structures all installed ... call the ldis
On 2018/1/6 14:28, Hanjun Guo wrote:
> Hi Dave,
>
> Thank you very much for the quick response! Minor comments inline.
>
> On 2018/1/6 14:06, Dave Hansen wrote:
>> On 01/05/2018 08:54 PM, Hanjun Guo wrote:
>>> Do you mean NX bit will be brought back later? I'm asking this because
>>> I tested thi
On Sat, Jan 6, 2018 at 6:07 AM, syzbot
wrote:
> Hello,
>
> syzkaller hit the following crash on
> 8a4816cad00bf14642f0ed6043b32d29a05006ce
> git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console output is at
On 2018/1/6 2:33, Jiri Kosina wrote:
> On Fri, 5 Jan 2018, Xishi Qiu wrote:
>
>> I run the latest RHEL 7.2 with the KAISER/KPTI patch, and boot failed.
>>
>> ...
>> [0.00] PM: Registered nosave memory: [mem
>> 0x810-0x8ff]
>> [0.00] PM: Registered nosave memory: [
On 01/05/2018 06:12 PM, Tim Chen wrote:
> Thanks to everyone for the feedback on the initial posting.
> This is an updated patchset and I hope I've captured all
> the review comments. I've done a lot of code clean up
> per everyone's comments. Please let me know if I've missed
> something.
>
S
SoundWire bus provides sdw_read() and sdw_write() APIs for Slave
devices to program the registers. Provide support in regmap for
SoundWire bus.
Signed-off-by: Hardik T Shah
Signed-off-by: Sanyog Kale
Reviewed-by: Philippe Ombredanne
Acked-by: Pierre-Louis Bossart
Reviewed-by: Takashi Iwai
Sig
Hi Dave,
Thank you very much for the quick response! Minor comments inline.
On 2018/1/6 14:06, Dave Hansen wrote:
> On 01/05/2018 08:54 PM, Hanjun Guo wrote:
>> Do you mean NX bit will be brought back later? I'm asking this because
>> I tested this patch which it fixed the boot panic issue but th
On Fri, Jan 5, 2018 at 6:22 PM, Eric W. Biederman wrote:
> Dan Williams writes:
>
>> Quoting Mark's original RFC:
>>
>> "Recently, Google Project Zero discovered several classes of attack
>> against speculative execution. One of these, known as variant-1, allows
>> explicit bounds checks to be by
On 2018/1/5 22:54, Andrew Lunn wrote:
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -1126,6 +1126,7 @@ static int hns3_nic_set_features(struct net_device
*netdev,
{
struct hns3_nic_priv *priv = netdev_priv(netdev);
On Fri, Jan 05, 2018 at 05:05:52PM +, Mark Brown wrote:
> On Thu, Dec 14, 2017 at 11:19:38AM +0530, Vinod Koul wrote:
> > SoundWire bus provides sdw_read() and sdw_write() APIs for Slave
> > devices to program the registers. Provide support in regmap for
> > SoundWire bus.
>
> I can't apply th
On Fri, Jan 05, 2018 at 11:22:15AM -0600, Pierre-Louis Bossart wrote:
> On 1/5/18 11:04 AM, Mark Brown wrote:
> >On Thu, Dec 14, 2017 at 11:19:38AM +0530, Vinod Koul wrote:
> >
> >>+ /* SoundWire register address are contiguous */
> >>+ if (config->reg_stride != 0)
> >>+ return -ENOTS
On Fri, Jan 05, 2018 at 05:04:21PM +, Mark Brown wrote:
> On Thu, Dec 14, 2017 at 11:19:38AM +0530, Vinod Koul wrote:
>
> > + /* SoundWire register address are contiguous */
> > + if (config->reg_stride != 0)
> > + return -ENOTSUPP;
>
> That doesn't mean the chip hasn't decided
On 01/05/2018 08:54 PM, Hanjun Guo wrote:
> Do you mean NX bit will be brought back later? I'm asking this because
> I tested this patch which it fixed the boot panic issue but the system
> will hang when rebooting the system, because rebooting will also call efi
> then panic as NS bit is set.
Wow
On 01/04/18 18:00, David Woodhouse wrote:
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index d4fc98c..1009d1a 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -429,6 +429,19 @@ config GOLDFISH
> def_bool y
> depends on X86_GOLDFISH
>
> +config RETPOLINE
> +
On Fri, Jan 5, 2018 at 6:52 PM, Linus Torvalds
wrote:
> On Fri, Jan 5, 2018 at 5:10 PM, Dan Williams wrote:
>> From: Andi Kleen
>>
>> When access_ok fails we should always stop speculating.
>> Add the required barriers to the x86 access_ok macro.
>
> Honestly, this seems completely bogus.
>
> Th
Recently, how the pointers being printed with %p has been changed
by commit ad67b74d2469 ("printk: hash addresses printed with %p").
This is causing a regression while showing offset in the
uprobe_events file. Instead of %p, use %px to display offset.
Before patch:
# perf probe -vv -x /tmp/a.ou
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng
---
arch/arm64/
On Fri, Jan 5, 2018 at 6:55 PM, Linus Torvalds
wrote:
> On Fri, Jan 5, 2018 at 5:09 PM, Dan Williams wrote:
>> +#ifndef nospec_ptr
>> +#define nospec_ptr(ptr, lo, hi)
>>\
>
> Do we actually want this horrible interface?
>
> It just causes the compi
> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On
> Behalf Of Sagar Arun Kamble
> Sent: Thursday, December 14, 2017 11:38 PM
> To: linux-kernel@vger.kernel.org
> Cc: intel-wired-...@lists.osuosl.org; Richard Cochran
> ; Kamble, Sagar A
> ; net...@vger.kernel.org
> Subject: [Int
> -Original Message-
> From: Brown, Aaron F
> Sent: Friday, January 5, 2018 8:34 PM
> To: 'Sagar Arun Kamble' ; linux-
> ker...@vger.kernel.org
> Cc: intel-wired-...@lists.osuosl.org; Richard Cochran
> ; Kamble, Sagar A
> ; net...@vger.kernel.org
> Subject: RE: [Intel-wired-lan] [PATCH 22
The Allwinner H6 SoC has a CCU which has been largely rearranged.
Add support for it in the sunxi-ng CCU framework.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt|1 +
drivers/clk/sunxi-ng/Kconfig |5 +
drivers/clk/sunxi-ng/Mak
Hi Jiri,
Thanks for the fix, comments inline.
On 2018/1/6 2:19, Jiri Kosina wrote:
>
> [ adding Hugh ]
>
> On Thu, 4 Jan 2018, Dave Hansen wrote:
>
>>> BTW, we have just reported a bug caused by kaiser[1], which looks like
>>> caused by SMEP. Could you please help to have a look?
>>>
>>> [1] h
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +---
drivers/clk/sunxi-ng/c
Use the ratelimited printk() version for swap-device write error
reporting. We can use ZRAM as a swap-device, and the tricky part
here is that zsmalloc() stores compressed objects in memory, thus
it has to allocates pages during swap-out. If the system is short
on memory, then we begin to flood pri
Loan Offer at 3% Lowest Rate Get Now.
> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On
> Behalf Of Sagar Arun Kamble
> Sent: Thursday, December 14, 2017 11:39 PM
> To: linux-kernel@vger.kernel.org
> Cc: intel-wired-...@lists.osuosl.org; Richard Cochran
> ; Kamble, Sagar A
> ; net...@vger.kernel.org
> Subject: [Int
> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On
> Behalf Of Sagar Arun Kamble
> Sent: Thursday, December 14, 2017 11:39 PM
> To: linux-kernel@vger.kernel.org
> Cc: intel-wired-...@lists.osuosl.org; Richard Cochran
> ; Kamble, Sagar A
> ; net...@vger.kernel.org
> Subject: [Int
> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On
> Behalf Of Sagar Arun Kamble
> Sent: Thursday, December 14, 2017 11:38 PM
> To: linux-kernel@vger.kernel.org
> Cc: intel-wired-...@lists.osuosl.org; Richard Cochran
> ; Kamble, Sagar A
> ; net...@vger.kernel.org
> Subject: [Int
> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On
> Behalf Of Sagar Arun Kamble
> Sent: Thursday, December 14, 2017 11:39 PM
> To: linux-kernel@vger.kernel.org
> Cc: intel-wired-...@lists.osuosl.org; Richard Cochran
> ; Kamble, Sagar A
> ; net...@vger.kernel.org
> Subject: [Int
> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On
> Behalf Of Jeff Kirsher
> Sent: Wednesday, December 6, 2017 8:25 AM
> To: Kamble, Sagar A ; linux-
> ker...@vger.kernel.org
> Cc: alsa-de...@alsa-project.org; linux-r...@vger.kernel.org;
> net...@vger.kernel.org; Richard Cochra
The Allwinner H6 SoC has two pin controllers, one main controller
(called CPUX-PORT in user manual) and one controller in CPUs power
domain (called CPUS-PORT in user manual).
This commit introduces support for the main pin controller on H6.
The pin bank A and B are not wired out and hidden from t
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. This
situation cannot be processed with the current pinctrl IRQ code, as it
only expects a offset to all IRQ banks.
Update the code to use a logical IRQ bank to hardw
The Allwinner H6 pin controllers (both the main one and the CPUs one)
have no bus gate clocks.
Add support for this kind of pin controllers.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 --
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
This patchset adds initial support for the Allwinner H6 SoC.
It's quite different from earlier Allwinner SoCs. For example, the
memory map is refactored, and the CCU is rearranged. It's also the first
Allwinner SoC with PCI Express interface, and the second one with USB
3.0 (the first one is A80).
Hi Geert,
On Fri, 5 Jan 2018, Geert Uytterhoeven wrote:
>
> I assume you meant this to go in through the m68k tree?
>
Yes, please. Because the NuBus-PowerMac port is out-of-tree, the m68k tree
seems more appropriate than the powerpc tree for this submission.
> Can you please run this through
On 01/05/2018 06:12 PM, Tim Chen wrote:
> .macro ENABLE_IBRS
> - ALTERNATIVE "jmp .Lskip_\@", "", X86_FEATURE_SPEC_CTRL
> + testl $1, dynamic_ibrs
> + jz .Lskip_\@
There was an earlier suggestion to use STATIC_JUMP_IF_... here. That's
a good suggestion, but we encountered some
On Fri, Jan 5, 2018 at 6:52 PM, Linus Torvalds
wrote:
>
> The fact is, we have to stop speculating when access_ok() does *not*
> fail - because that's when we'll actually do the access. And it's that
> access that needs to be non-speculative.
I also suspect we should probably do this entirely dif
Hi, Rafael
Best Regards!
Anson Huang
> -Original Message-
> From: rjwyso...@gmail.com [mailto:rjwyso...@gmail.com] On Behalf Of Rafael
> J. Wysocki
> Sent: 2018-01-05 8:21 PM
> To: Anson Huang
> Cc: linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; Linux
> PM ; Linux Ker
Add 696MHz operating point according to datasheet
(Rev. 0, 12/2015).
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index d5181f8..963e169 100644
--- a/arch/arm/boot/
Add 696MHz operating point for i.MX6UL, only for those
parts with speed grading fuse set to 2b'10 supports
696MHz operating point, so, speed grading check is also
added for i.MX6UL in this patch, the clock tree for each
operating point are as below:
696MHz:
pll1 69600
On Fri, 2018-01-05 at 15:28 -0800, Hugh Dickins wrote:
> On Fri, Jan 5, 2018 at 6:03 AM, Mike Galbraith wrote:
> > On Fri, 2018-01-05 at 14:34 +0100, Greg Kroah-Hartman wrote:
> >>
> >> Ok, we found two patches that were missing in 4.4-stable that were in
> >> the SLES12 tree (thanks to Jamie Iles
On Fri, Jan 5, 2018 at 5:09 PM, Dan Williams wrote:
> +#ifndef nospec_ptr
> +#define nospec_ptr(ptr, lo, hi)
> \
Do we actually want this horrible interface?
It just causes the compiler - or inline asm - to generate worse code,
because it needs to
On Fri, Jan 5, 2018 at 5:10 PM, Dan Williams wrote:
> From: Andi Kleen
>
> When access_ok fails we should always stop speculating.
> Add the required barriers to the x86 access_ok macro.
Honestly, this seems completely bogus.
The description is pure garbage afaik.
The fact is, we have to stop
Hi Andrew,
>>> Andrew Morton 01/06/18 4:50 AM >>>
On Thu, 04 Jan 2018 23:31:12 -0700 "Gang He" wrote:
> Happy new year.
> Could you help to pick up this patch, which is used to fix a old patch
> 1cce4df04f37.
> If we have not this patch, some multiple node test cases will trigger
> softlocku
From: Andrea Arcangeli
Set IBRS upon kernel entrance via syscall and interrupts. Clear it
upon exit. IBRS protects against unsafe indirect branching predictions
in the kernel.
The NMI interrupt save/restore of IBRS state was based on Andrea
Arcangeli's implementation.
Here's an explanation by D
Clear IBRS on idle entry and set it on idle exit into kernel on mwait.
When we are in mwait, we are not running but if we leave IBRS on,
it will affect the performance on the sibling hardware thread. So
we disable IBRS and reenable it when we wake up.
Signed-off-by: Tim Chen
---
arch/x86/includ
From: Tim Chen
From: Andrea Arcangeli
There are 2 ways to control IBRS
1. At boot time
noibrs kernel boot parameter will disable IBRS usage
Otherwise if the above parameters are not specified, the system
will enable ibrs and ibpb usage if the cpu supports it.
2. At run time
echo 0 > /
On new microcode write, check whether IBRS
is present by rescanning IBRS feature.
Signed-off-by: Tim Chen
---
arch/x86/include/asm/spec_ctrl.h | 1 +
arch/x86/kernel/cpu/microcode/core.c | 4
arch/x86/kernel/cpu/spec_ctrl.c | 18 ++
3 files changed, 15 insertions(
Create macros to control IBRS. Use these macros to enable IBRS on kernel entry
paths and disable IBRS on kernel exit paths.
The registers rax, rcx and rdx are touched when controlling IBRS
so they need to be saved when they can't be clobbered.
Signed-off-by: Tim Chen
---
arch/x86/entry/calling
Don't use dynamic IBRS that toggle IBRS on entry/exit
to kernel code if retpoline is used.
Signed-off-by: Tim Chen
---
arch/x86/kernel/cpu/spec_ctrl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/cpu/spec_ctrl.c b/arch/x86/kernel/cpu/spec_ctrl.c
index 28107a2..076c470 10
From: David Woodhouse
We are impervious to the indirect branch prediction attack with retpoline
but firmware won't be, so we still need to set IBRS to protect
firmware code execution when calling into firmware at runtime.
Signed-off-by: David Woodhouse
Signed-off-by: Tim Chen
---
arch/x86/inc
cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
IA32_SPEC_CTRL (0x48)
IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS)
If IBRS is set, near returns and near indirect jumps/calls will not allow
their predicted target address to be controlled by code that exe
Thanks to everyone for the feedback on the initial posting.
This is an updated patchset and I hope I've captured all
the review comments. I've done a lot of code clean up
per everyone's comments. Please let me know if I've missed
something.
The retpoline related changes is moved to the end of the
On 5 January 2018 at 22:01, Anders Roxell wrote:
> aarch64-linux-gnu-gcc -Wl,-no-as-needed -Wall
> -lpthread seccomp_bpf.c -o seccomp_bpf
> seccomp_bpf.c: In function 'tracer_ptrace':
> seccomp_bpf.c:1720:12: error: '__NR_open' undeclared
> (first use in this function)
> if (nr == __NR_o
Dan Williams writes:
> Quoting Mark's original RFC:
>
> "Recently, Google Project Zero discovered several classes of attack
> against speculative execution. One of these, known as variant-1, allows
> explicit bounds checks to be bypassed under speculation, providing an
> arbitrary read gadget. Fu
Hi,
On Fri, Jan 05, 2018 at 04:00:25PM -0800, Linus Torvalds wrote:
> On Fri, Jan 5, 2018 at 2:04 PM, Aaro Koskinen wrote:
> > After v4.14, I've been unable to boot my AMD compilation box with the
> > v4.15-rc mainline Linux. It just ends up in a silent reboot loop.
> >
> > I bisected this to:
>
On Fri, Jan 5, 2018 at 5:53 PM, Srinivas Pandruvada
wrote:
> On Fri, 2018-01-05 at 17:10 -0800, Dan Williams wrote:
>> Static analysis reports that 'trip' may be a user controlled value
>> that
>> is used as a data dependency to read '*temp' from the 'd->aux_trips'
>> array. In order to avoid pot
On Fri, 2018-01-05 at 17:10 -0800, Dan Williams wrote:
> Static analysis reports that 'trip' may be a user controlled value
> that
> is used as a data dependency to read '*temp' from the 'd->aux_trips'
> array. In order to avoid potential leaks of kernel memory values,
> block
> speculative execut
The ohci-da8xx device only has one clock, so a con_id is not needed, so
remove it. This way we don't have to add an unnecessary property to the
device tree bindings for the clock.
Signed-off-by: David Lechner
---
drivers/usb/host/ohci-da8xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
This adds the DeviceTree binding for the Qualcomm SDM845 TLMM block.
Signed-off-by: Bjorn Andersson
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 176 +
1 file changed, 176 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pin
From: Rajendra Nayak
This adds the pinctrl definitions for the TLMM of SDM845.
Signed-off-by: Rajendra Nayak
[bjorn: consolidated functions]
Signed-off-by: Bjorn Andersson
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/
There is only one clock for the DA8xx MUSB device, so we don't need the
con_id, so remove it. This way we don't have to add an unnecessary
property to the device tree bindings for the clock.
Signed-off-by: David Lechner
---
drivers/usb/musb/da8xx.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 01/05/2018 04:42 AM, Sekhar Nori wrote:
On Friday 05 January 2018 08:29 AM, David Lechner wrote:
On 01/04/2018 11:50 AM, David Lechner wrote:
On 1/4/18 6:39 AM, Sekhar Nori wrote:
This is a pretty huge patch again and I hope it can be broken down.
Ideally one per SoC converted and then th
On Fri, Jan 05, 2018 at 04:11:07PM -0800, Kees Cook wrote:
> On Fri, Jan 5, 2018 at 2:59 PM, Tobin C. Harding wrote:
> > Script currently times out when parsing the following files:
> >
> > /proc/kallsyms
> > /proc/sched_debug
> > /proc/PID/smaps
>
> Seems like kallsyms wo
On 01/05/2018 12:54 PM, Greg Kroah-Hartman wrote:
On Fri, Jan 05, 2018 at 09:56:16AM -0800, Guenter Roeck wrote:
On Wed, Jan 03, 2018 at 09:11:06PM +0100, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.4.110 release.
There are 37 patches in this series, all wil
This set is a re-spin of
[PATCH] iio: add kernel-doc '@owner'
Patch 1 is the original patch. Adds a kernel-doc description for field
@owner clearing a sphinx build warning when building kernel documentation.
Patch 2 adds field identifier for @use_count. Currently this field has a
descrip
When building kernel documentation sphinx emits the following warning
warning: No description found for parameter 'owner'
Add description for struct member 'owner'.
Signed-off-by: Tobin C. Harding
---
include/linux/iio/trigger.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/inclu
Kernel-doc for @use_count does not currently have a field
identifier. All the rest of the fields do. @use_count is used internally
and should not be accessed directly by the driver so it should be
marked as so.
Add [INTERN] identifier to @use_count field.
Signed-off-by: Tobin C. Harding
---
inc
Currently msg_zerocopy is not included in any toctree. Sphinx emits a
build warning to this effect. The other three rst files in
Documentation/networking are all indexed. We can add msg_zerocopy to the
toctree to enable navigation of the document via HTML kernel docs.
Add msg_zerocopy to the netwo
On Wed, Jan 03, 2018 at 09:41:04AM +0100, SF Markus Elfring wrote:
> > I understand it can be frustrating to encounter different policies
> > across kernel maintainers.
>
> The change acceptance is varying for special transformation patterns.
>
>
> > You'll even run in to this with maintainers o
On 01/05/2018 03:16 AM, David Woodhouse wrote:
> On Thu, 2018-01-04 at 09:56 -0800, Tim Chen wrote:
>>
>> + mutex_lock(&spec_ctrl_mutex);
>> +
>> + if (enable == IBRS_DISABLED) {
>> + /* disable IBRS usage */
>> + set_ibrs_disabled();
>> + if (s
From: Mark Rutland
This patch implements nospec_ptr() for arm, following the recommended
architectural sequences for the arm and thumb instruction sets.
Signed-off-by: Mark Rutland
Signed-off-by: Dan Williams
---
arch/arm/include/asm/barrier.h | 75
Static analysis reports that 'offset' may be a user controlled value
that is used as a data dependency reading from a raw6_frag_vec buffer.
In order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue further
reads based on an inv
Static analysis reports that 'pos' may be a user controlled value that
is used as a data dependency determining which extent to return out of
'map'. In order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue further
reads based
Static analysis reports that 'index' may be a user controlled value that
is used as a data dependency reading 'rt' from the 'platform_label'
array. In order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue further
reads based
Expectedly, static analysis reports that 'fd' is a user controlled value
that is used as a data dependency to read from the 'fdt->fd' array. In
order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue reads
based on an invalid '
Static analysis reports that 'eahd->appAttrLocation' and
'eahd->impAttrLocation' may be a user controlled values that are used as
data dependencies for calculating source and destination buffers for
memmove operations. In order to avoid potential leaks of kernel memory
values, block speculative exe
Static analysis reports that 'trip' may be a user controlled value that
is used as a data dependency to read '*temp' from the 'd->aux_trips'
array. In order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue reads
based on an in
Static analysis reports that 'queue' may be a user controlled value that
is used as a data dependency to read 'txq_params' from the
'priv->tx_queue_params.params' array. In order to avoid potential leaks
of kernel memory values, block speculative execution of the instruction
stream that could issu
From: Andi Kleen
When access_ok fails we should always stop speculating.
Add the required barriers to the x86 access_ok macro.
Cc: Thomas Gleixner
Cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: Arnd Bergmann
Cc: x...@kernel.org
Signed-off-by: Andi Kleen
Signed-off-by: Dan Williams
---
arch/x86/
Static analysis reports that 'queue' may be a user controlled value that
is used as a data dependency to read from the 'priv->qos_params' array.
In order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue reads
based on an invali
Static analysis reports that 'handle' may be a user controlled value
that is used as a data dependency to read 'sp' from the
'req->outstanding_cmds' array. In order to avoid potential leaks of
kernel memory values, block speculative execution of the instruction
stream that could issue reads based
Static analysis reports that 'offset' may be a user controlled value
that is used as a data dependency reading from a raw_frag_vec buffer.
In order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue further
reads based on an inva
The new speculative execution barrier, nospec_barrier(), ensures
that any userspace controllable speculation doesn't cross the boundary.
Any user observable speculative activity on this CPU thread before this
point either completes, reaches a state it can no longer cause an
observable activity, or
Static analysis reports that 'queue' may be a user controlled value that
is used as a data dependency to read from the 'ar9170_qmap' array. In
order to avoid potential leaks of kernel memory values, block
speculative execution of the instruction stream that could issue reads
based on an invalid res
Static analysis reports that 'index' may be a user controlled value that
is used as a data dependency to read 'pin' from the
'selector->baSourceID' array. In order to avoid potential leaks of
kernel memory values, block speculative execution of the instruction
stream that could issue reads based on
From: Mark Rutland
Document the rationale and usage of the new nospec*() helpers.
Signed-off-by: Mark Rutland
Signed-off-by: Will Deacon
Cc: Dan Williams
Cc: Jonathan Corbet
Cc: Peter Zijlstra
Signed-off-by: Dan Williams
---
Documentation/speculation.txt | 166 +++
Quoting Mark's original RFC:
"Recently, Google Project Zero discovered several classes of attack
against speculative execution. One of these, known as variant-1, allows
explicit bounds checks to be bypassed under speculation, providing an
arbitrary read gadget. Further details can be found on the
From: Mark Rutland
This patch implements nospec_ptr() for arm64, following the recommended
architectural sequence.
Signed-off-by: Mark Rutland
Signed-off-by: Will Deacon
Cc: Dan Williams
Cc: Peter Zijlstra
Signed-off-by: Dan Williams
---
arch/arm64/include/asm/barrier.h | 55
From: Mark Rutland
Under speculation, CPUs may mis-predict branches in bounds checks. Thus,
memory accesses under a bounds check may be speculated even if the
bounds check fails, providing a primitive for building a side channel.
This patch adds helpers which can be used to inhibit the use of
ou
On Sat, Jan 06, 2018 at 12:30:23AM +0100, Rafael J. Wysocki wrote:
> On Wed, Jan 3, 2018 at 12:49 PM, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > Calling acpi_wmi_init() at the subsys_initcall() level causes ordering
> > issues to appear on some systems and they are difficult to
Hi Hugh,
Thank you very much for your very thoughtful input.
I quiet positive this problem is PTI regression, because exactly the
same problem I see with kernel 4.1 to which I back-ported all the
necessary PTI patches from 4.4.110. I will provide this thread with more
information as I collect
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