Hi,
On Thu, Dec 14, 2017 at 04:23:43PM +0100, Christoph Hellwig wrote:
> From: Matthew Wilcox
>
> The epoll code currently uses the unlocked waitqueue helpers for managing
The userfaultfd code
> fault_wqh, but instead of holding the waitqueue lock for this waitqueue
> around these calls, it th
On 12/16/2017 08:12 PM, vcap...@pengaru.com wrote:
On Sat, Dec 16, 2017 at 10:03:38AM -0800, vcap...@pengaru.com wrote:
On Sat, Dec 16, 2017 at 04:49:08PM +0200, Avi Kivity wrote:
On 12/14/2017 09:15 PM, Goldwyn Rodrigues wrote:
On 12/14/2017 11:38 AM, Avi Kivity wrote:
I'm looking to add
On Thu, Dec 14, 2017 at 4:30 PM, Philippe Ombredanne
wrote:
> Gilad,
>
> On Thu, Dec 14, 2017 at 3:02 PM, Gilad Ben-Yossef wrote:
>> The ccree driver has had a none standard sysfs interface for debugging.
>> Replace it with a proper debugfs interface.
>>
>> Signed-off-by: Gilad Ben-Yossef
>
>
>
Hi Randy,
Thanks a lot for the review.
> -Original Message-
> From: Randy Dunlap [mailto:rdun...@infradead.org]
> Sent: Saturday, December 16, 2017 2:18 PM
> To: Dhaval Rajeshbhai Shah ; a...@arndb.de;
> gre...@linuxfoundation.org; robh...@kernel.org; mark.rutl...@arm.com
> Cc: devicet...
On 12/16/2017 07:28 PM, Tetsuo Handa wrote:
Wei Wang wrote:
On 12/16/2017 02:42 AM, Matthew Wilcox wrote:
On Tue, Dec 12, 2017 at 07:55:55PM +0800, Wei Wang wrote:
+int xb_preload_and_set_bit(struct xb *xb, unsigned long bit, gfp_t gfp);
I'm struggling to understand when one would use this.
On Sun, Dec 17, 2017 at 3:19 AM, Nishanth Menon wrote:
> On 08:21-20171213, Lokesh Vutla wrote:
>>
>>
>> On Saturday 02 December 2017 03:52 PM, Nishanth Menon wrote:
>> > Switch to SPDX licensing and drop the GPL text which comes redundant.
>> >
>> > Signed-off-by: Nishanth Menon
>>
>>
>> Reviewe
Some of the MSRs related to LBR (Last Branch Record) have different names
and layouts among Intel and AMD, but the kernel does not distinguish them.
Currently it does not invoke any bugs, but it is better to assign them separate
macros in order to avoid confusion.
Signed-off-by: Soramichi Akiyama
Currently there is no support for TSCS42xx audio CODECs.
Add support for TSCS42xx audio CODECs.
Acked-by: Philippe Ombredanne
Signed-off-by: Steven Eckhoff
---
.../devicetree/bindings/sound/tscs42xx.txt | 16 +
.../devicetree/bindings/vendor-prefixes.txt|1 +
MAINTAINERS
From: Brendan McGrath
Date: Wed, 13 Dec 2017 22:14:57 +1100
> One example of when an ICMPv6 packet is required to be looped back is
> when a host acts as both a Multicast Listener and a Multicast Router.
>
> A Multicast Router will listen on address ff02::16 for MLDv2 messages.
>
> Currently, M
On Sat, 16 Dec 2017, Linus Torvalds wrote:
> Nico,
>
> On Sat, Dec 16, 2017 at 7:00 PM, kbuild test robot
> wrote:
> >
> > fs/cramfs/inode.c:641: undefined reference to `mtd_point'
> > fs/cramfs/inode.c:658: undefined reference to `mtd_unpoint'
> > fs/cramfs/inode.c:959: undefined reference to `
On Fri, Dec 15, 2017 at 8:07 AM, Ingo Molnar wrote:
>
> * Andy Lutomirski wrote:
>
>> On Fri, Dec 15, 2017 at 7:43 AM, Ingo Molnar wrote:
>> > Linus,
>>
>> >
>> > - two 5-level paging related fixes
>>
>> Which reminds me: can you grab this one, too?
>>
>> https://lkml.kernel.org/r/24c898b4f44fd
Nico,
On Sat, Dec 16, 2017 at 7:00 PM, kbuild test robot
wrote:
>
> fs/cramfs/inode.c:641: undefined reference to `mtd_point'
> fs/cramfs/inode.c:658: undefined reference to `mtd_unpoint'
> fs/cramfs/inode.c:959: undefined reference to `mount_mtd'
This does seem to be real.
As of 99c18ce580c6 (
On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy
wrote:
> From: "Gautham R. Shenoy"
>
> On POWER8 and POWER9, the PMSR and the PMCR registers define pstates
> to be 8-bit wide values. The device-tree exports pstates as 32-bit
> wide values of which the lower byte is the actual pstate.
>
> The c
On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy
wrote:
> From: "Gautham R. Shenoy"
>
> The code in powernv-cpufreq, makes the following two assumptions which
> are not guaranteed by the device-tree bindings:
>
> 1) Pstate ids are continguous: This is used in pstate_to_idx() to
>obt
On Wed, Dec 13, 2017 at 5:57 PM, Gautham R. Shenoy
wrote:
> From: "Gautham R. Shenoy"
>
> On POWERNV platform, the fields for pstates in the Power Management
> Status Register (PMSR) and the Power Management Control Register
> (PMCR) are 8-bits wide. On POWER8 the pstates are negatively numbered
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
branch HEAD: f3b5ad89de16f5d42e8ad36fbdf85f705c1ae051 Merge tag 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
Regressions in current branch:
cc1: error: '-march=r3900' requires '-mf
This is the second time i am sending you this mail.
I, Friedrich Mayrhofer Donates the sum of $ 1,000,000.00 to You, Email Me
personally for more details.
Regards.
Friedrich Mayrhofer
On Sat, Dec 16, 2017 at 3:35 PM, kbuild test robot
wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
> WIP.x86/pti-upstream
> head: 78e4da51f7c77587cc6f419af4f63a21b289bdb7
> commit: 7e482cfe4a23ead21215423c4566c8516ba21025 [38/50] x86/pti: Put the LDT
> in its own P
The compatible string for this panel was specified as
toshiba,lt089ac29000.txt. I believe this is a mistake.
Fixes: 06e733e41f87 ("drm/panel: simple: add Toshiba LT089AC19000")
Cc: Lucas Stach
Signed-off-by: Jonathan Neuschäfer
---
.../devicetree/bindings/display/panel/toshiba,lt089ac29000.txt
On Sat, 2017-12-16 at 09:47 -0800, Stephen Hemminger wrote:
> On Sat, 16 Dec 2017 15:42:25 +0100
> Knut Omang wrote:
>
> > This patch series implements features to make it easier to run checkers on
> > the
> > entire kernel as part of automatic and developer testing.
> >
> > This is done by rep
On Sat, 2017-12-16 at 10:24 -0800, Joe Perches wrote:
> On Sat, 2017-12-16 at 09:45 -0800, Stephen Hemminger wrote:
> > On Sat, 16 Dec 2017 15:42:29 +0100 Knut Omang wrote:
> > > +# Code simplification:
> > > +#
> > > +except ALLOC_WITH_MULTIPLY ib.c
> > > +except PREFER_PR_LEVEL ib_cm.c ib_recv.c
On Sat, 2017-12-16 at 12:00 -0800, santosh.shilim...@oracle.com wrote:
> On 12/16/17 10:24 AM, Joe Perches wrote:
> > On Sat, 2017-12-16 at 09:45 -0800, Stephen Hemminger wrote:
> >> On Sat, 16 Dec 2017 15:42:29 +0100 Knut Omang
> >> wrote:
> >>> +# Code simplification:
> >>> +#
> >>> +except ALL
2017-12-15 19:06 GMT+08:00 Marc Zyngier :
> On 15/12/17 01:40, Wanpeng Li wrote:
>> From: Wanpeng Li
>>
>> Reported by syzkaller:
>>
>> BUG: KASAN: stack-out-of-bounds in write_mmio+0x11e/0x270 [kvm]
>> Read of size 8 at addr 8803259df7f8 by task syz-executor/32298
>>
>> CPU: 6 PID: 3229
The following changes since commit ae64f9bd1d3621b5e60d7363bc20afb46aede215:
Linux 4.15-rc2 (2017-12-03 11:01:47 -0500)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git
tags/ext4_for_stable
for you to fetch changes up to 9d5afec6b8bd46d6e
On Sat, 2017-12-16 at 09:45 -0800, Stephen Hemminger wrote:
> On Sat, 16 Dec 2017 15:42:29 +0100
> Knut Omang wrote:
>
> > +
> > +# Important to fix from a quality perspective:
> > +#
> > +except AVOID_BUG connection.c ib.c ib_cm.c ib_rdma.c ib_recv.c ib_ring.c
> > ib_send.c
> info.c loop.c mess
From: Ondrej Jirman
Without this the AXP813 PMIC fails to probe on TBS A711.
Signed-off-by: Ondrej Jirman
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
ind
On Mon, 2017-12-11 at 14:43 -0800, Matthew Wilcox wrote:
> - There's no warning for the first paragraph of section 6:
>
> 6) Functions
>
>
> Functions should be short and sweet, and do just one thing. They should
> fit on one or two screenfuls of text (the ISO/ANSI screen size is 8
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
WIP.x86/pti-upstream
head: 78e4da51f7c77587cc6f419af4f63a21b289bdb7
commit: 7e482cfe4a23ead21215423c4566c8516ba21025 [38/50] x86/pti: Put the LDT
in its own PGD if PTI is on
config: i386-alldefconfig (attached as .config)
compi
On Sun, 2017-12-17 at 09:37 +1100, Dave Chinner wrote:
> On Sat, Dec 16, 2017 at 08:46:38AM -0500, Jeff Layton wrote:
> > From: Jeff Layton
> >
> > Add a documentation blob that explains what the i_version field is, how
> > it is expected to work, and how it is currently implemented by various
>
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Hi Nicolas,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: f3b5ad89de16f5d42e8ad36fbdf85f705c1ae051
commit: 99c18ce580c6cc6763e694b4ce320d7b226ab59b cramfs: direct memory access
support
date: 9 weeks ago
config:
On Saturday, December 16, 2017 5:47:07 PM CET Viresh Kumar wrote:
> On 16 December 2017 at 22:10, Rafael J. Wysocki wrote:
> > On Wed, Dec 13, 2017 at 10:53 AM, Viresh Kumar
> > wrote:
>
> >> +#define SCHED_CPUFREQ_CLEAR(1U << 31)
> >
> > I'm not thrilled by this, because schedutil is not t
From: Sai Praneeth
Since the previous patch added support for efi_mm, let's handle efi_pgd
through efi_mm and remove global variable efi_pgd.
Signed-off-by: Sai Praneeth Prakhya
Cc: Lee, Chun-Yi
Cc: Borislav Petkov
Cc: Tony Luck
Cc: Andy Lutomirski
Cc: Michael S. Tsirkin
Cc: Bhupesh Sharma
From: Sai Praneeth
Use helper function (efi_switch_mm()) to switch to/from efi_mm. We
switch to efi_mm before calling
1. efi_set_virtual_address_map() and
2. Invoking any efi_runtime_service()
Likewise, we need to switch back to previous mm (mm context stolen by
efi_mm) after the above calls ret
From: Sai Praneeth
Presently, only ARM uses mm_struct to manage efi page tables and efi
runtime region mappings. As this is the preferred approach, let's make
this data structure common across architectures. Specially, for x86,
using this data structure improves code maintainability and readabili
From: Sai Praneeth
Presently, in x86, to invoke any efi function like
efi_set_virtual_address_map() or any efi_runtime_service() the code path
typically involves read_cr3() (save previous pgd), write_cr3()
(write efi_pgd) and calling efi function. Likewise after returning from
efi function the co
* Linus Torvalds wrote:
> On Fri, Dec 15, 2017 at 5:58 PM, Ingo Molnar wrote:
> >
> > These are the x86-64 low level entry code preparatory patches for the page
> > table
> > isolation patches - which are required for PTI, which addresses KASLR and
> > similar
> > information leaks.
>
> Ugh.
From: Colin Ian King
Trivial fix to spelling mistake in dev_dbg debug message. Also
add in a missing comma.
Signed-off-by: Colin Ian King
---
drivers/misc/mei/bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c
index 2a5146b
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
WIP.x86/pti-upstream
head: 78e4da51f7c77587cc6f419af4f63a21b289bdb7
commit: 7e482cfe4a23ead21215423c4566c8516ba21025 [38/50] x86/pti: Put the LDT
in its own PGD if PTI is on
config: i386-randconfig-h0-12170619 (attached as .con
On Sat, Dec 16, 2017 at 01:33:26PM +0900, Seongbae Son wrote:
> > > Details can be found as follows.
> > >
> > > Son et al. "Guaranteeing the Metadata Update Atomicity in EXT4
> > > Filesystem”,
> > > In Proc. of APSYS 2017, Mumbai, India
>
> > This is behind a paywall, so I can't access it. I a
On Sat, Dec 16, 2017 at 12:29 PM, syzbot
wrote:
> Hello,
>
> syzkaller hit the following crash on
> 5c13e07580c8bd2af6aa902d6b62faa968c360bc
> git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console output is
On Fri, Dec 15, 2017 at 5:58 PM, Ingo Molnar wrote:
>
> These are the x86-64 low level entry code preparatory patches for the page
> table
> isolation patches - which are required for PTI, which addresses KASLR and
> similar
> information leaks.
Ugh.
Ok, I've read through this, and while I lik
On 12/12/17 1:29 AM, Ma Shimiao wrote:
If source string longer than max, kstrndup will alloc max+1 space.
So, we should make sure the result will not over limit.
Signed-off-by: Ma Shimiao
---
Applied. Thanks !!
On Thursday 09 November 2017 22:21:31 Pali Rohár wrote:
> So from all tests and discussion I would propose new unification:
>
> 1. Read label only from the root directory. If label in root directory
>is missing then disk would be treated as without label. Label from
>boot sector would not
On 12/16/17 12:40 PM, Nishanth Menon wrote:
Hi,
The following changes have been done in the updated series:
* Updates for couple few typo errors in commit messages
* copyrights are now always behind description
* rebased to maintainer branch (was previously against master)
Rebased to:
git://gi
On 12/2/17 2:20 AM, Nishanth Menon wrote:
mbox_msg->len is of type size_t and %d is incorrect format. Instead
use %zu for handling size_t correctly.
Signed-off-by: Nishanth Menon
---
Applied to 'for_4.16/drivers-soc' with Lokesh's ack.
On Sat, Dec 16, 2017 at 08:46:38AM -0500, Jeff Layton wrote:
> From: Jeff Layton
>
> Add a documentation blob that explains what the i_version field is, how
> it is expected to work, and how it is currently implemented by various
> filesystems.
>
> We already have inode_inc_iversion. Add several
Hi folks,
I just upgraded gcc to 6.4 on my centos 7 machine by Arnd's suggestion.
But, I ran into the below compile error with 4.15-rc3 kernel:
In file included from ./include/uapi/linux/uuid.h:21:0,
from ./include/linux/uuid.h:19,
from ./include/linux/mod_dev
On Sun, Dec 17, 2017 at 8:34 AM, Rob Landley wrote:
> I just added a ppc64 target to https://github.com/landley/mkroot which
> means I built 4.14 with the attached miniconfig and ran it with the
> attached qemu command line, and it works fine as is but if you remove
> the transactional mem line fr
On 12/16/17 4:24 AM, Arnd Bergmann wrote:
On Fri, Dec 15, 2017 at 7:01 PM, Yang Shi wrote:
On 12/15/17 4:51 AM, Arnd Bergmann wrote:
When the down_read_trylock() fails, 'vma' has not been initialized
yet, which gcc now warns about:
mm/khugepaged.c: In function 'khugepaged':
mm/khugepaged
On 12/16/17 12:09 PM, Kirill A. Shutemov wrote:
On Sat, Dec 16, 2017 at 12:45:25PM +0100, Michal Hocko wrote:
On Sat 16-12-17 04:04:10, Yang Shi wrote:
Hi Kirill & Michal,
Since both of you raised the same question about who holds the semaphore for
that long time, I just reply here to both o
On 12/14/2017 11:24 PM, Dhaval Shah wrote:
> Xilinx ZYNQMP logicoreIP Init driver is based on the new
> LogiCoreIP design created. This driver provides the processing system
> and programmable logic isolation. Set the frequency based on the clock
> information get from the logicoreIP register set.
Cong Wang writes:
> On Thu, Dec 14, 2017 at 1:08 PM, Al Viro wrote:
>> On Thu, Dec 14, 2017 at 12:17:57PM -0800, Cong Wang wrote:
>>> syzbot reported we have a use-after-free when mqueue_evict_inode()
>>> is called on __cleanup_mnt() path, where the ipc ns is already
>>> freed by the previous ex
Dear Friend,
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On 08:01-20171213, Lokesh Vutla wrote:
>
>
> On Saturday 02 December 2017 03:57 PM, Nishanth Menon wrote:
> > message->len is of type size_t and %d is incorrect format usage.
> > Instead use %zu for handling size_t correctly.
> >
> > Signed-off-by: Nishanth Menon
>
> Reviewed-by: Lokesh Vutla
From: Dave Hansen
If the kernel oopses while on the trampoline stack, it will print
"" even if SYSENTER is not involved. That is rather confusing.
The "SYSENTER" stack is used for a lot more than SYSENTER now. Give it a
better string to display in stack dumps, and rename the kernel code to
mat
From: Andy Lutomirski
The kernel is very erratic as to which pagetables have _PAGE_USER set. The
vsyscall page gets lucky: it seems that all of the relevant pagetables are
among the apparently arbitrary ones that set _PAGE_USER. Rather than
relying on chance, just explicitly set _PAGE_USER.
Th
On 08:21-20171213, Lokesh Vutla wrote:
>
>
> On Saturday 02 December 2017 03:52 PM, Nishanth Menon wrote:
> > Switch to SPDX licensing and drop the GPL text which comes redundant.
> >
> > Signed-off-by: Nishanth Menon
>
>
> Reviewed-by: Lokesh Vutla
>
Hi Jassi,
Gentle ping.
--
Regards,
From: Thomas Gleixner
In order to sanitize the LDT initialization on x86 arch_dup_mmap() must be
allowed to fail. Fix up all instances.
Signed-off-by: Thomas Gleixner
Signed-off-by: Peter Zijlstra (Intel)
Cc: Juergen Gross
Cc: Eduardo Valentin
Cc: Denys Vlasenko
Cc: aligu...@amazon.com
Cc:
From: Peter Zijlstra
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laight
Cc: Denys Vlasenko
Cc: Eduardo Valentin
Cc: Greg KH
Cc: H.
From: Andy Lutomirski
If something goes wrong with pagetable setup, vsyscall=native will
accidentally fall back to emulation. Make it warn and fail so that we
notice.
Signed-off-by: Andy Lutomirski
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Borislav Petkov
Cc: Brian Gerst
From: Thomas Gleixner
The LDT is inheritet independent of fork or exec, but that makes no sense
at all because exec is supposed to start the process clean.
The reason why this happens is that init_new_context_ldt() is called from
init_new_context() which obviously needs to be called for both for
From: Peter Zijlstra
The LDT is duplicated on fork() and on exec(), which is wrong as exec()
should start from a clean state, i.e. without LDT. To fix this the LDT
duplication code will be moved into arch_dup_mmap() which is only called
for fork().
This introduces a locking problem. arch_dup_mma
I case someone wonders. V149 is my version number of the patch queue since
this whole endeavour started. Hillarious, isn't it? But alone this
reshuffling created 22 new versions because I do that very fine grained and
archive each step in case something goes wrong. Being able to do fine
grained com
From: Peter Zijlstra
Commit: ec400ddeff20 ("x86/microcode_intel_early.c: Early update ucode on
Intel's CPU") grubbed into tlbflush internals without coherent explanation.
Since it says its precaution and the SDM doesn't mention anything like
this, take it out back.
Signed-off-by: Peter Zijlstra
From: Peter Zijlstra
__flush_tlb_single() is for user mappings, __flush_tlb_one() for
kernel mappings.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hanse
From: Peter Zijlstra
Since uv_flush_tlb_others() implements flush_tlb_others() which is
about flushing user mappings, we should use __flush_tlb_single(),
which too is about flushing user mappings.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
From: Dave Hansen
First, it's nice to remove the magic numbers.
Second, PAGE_TABLE_ISOLATION is going to consume half of the available ASID
space. The space is currently unused, but add a comment to spell out this
new restriction.
Signed-off-by: Dave Hansen
Signed-off-by: Thomas Gleixner
Sig
From: Dave Hansen
There are effectively two ASID types:
1. The one stored in the mmu_context that goes from 0..5
2. The one programmed into the hardware that goes from 1..6
This consolidates the locations where converting between the two (by doing
a +1) to a single place which gives us a nice
From: Peter Zijlstra
Unclutter tlbflush.h a little.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laight
Cc: Denys Vlasenko
Cc: Eduardo Valentin
Cc: Greg KH
Cc: H.
Ran checkpatch across the entire drivers/android
directory and fixed all relevant warnings. Summary
of changes done:
-> Convert all symbolic permissions into their
octal equivalents.
-> Use "%s", __func__ in logging macros where the
function name was previously hard-coded.
-> Add a blan
From: Peter Zijlstra
Per popular request..
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laight
Cc: Denys Vlasenko
Cc: Eduardo Valenti
From: Thomas Gleixner
Many x86 CPUs leak information to user space due to missing isolation of
user space and kernel space page tables. There are many well documented
ways to exploit that.
The upcoming software migitation of isolating the user and kernel space
page tables needs a misfeature flag
From: Dave Hansen
PAGE_TABLE_ISOLATION needs to switch to a different CR3 value when it
enters the kernel and switch back when it exits. This essentially needs to
be done before leaving assembly code.
This is extra challenging because the switching context is tricky: the
registers that can be c
From: Dave Hansen
Global pages stay in the TLB across context switches. Since all contexts
share the same kernel mapping, these mappings are marked as global pages
so kernel entries in the TLB are not flushed out on a context switch.
But, even having these entries in the TLB opens up something
From: Dave Hansen
Add the pagetable helper functions do manage the separate user space page
tables.
[ tglx: Split out from the big combo kaiser patch. Folded Andys
simplification ]
Signed-off-by: Dave Hansen
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
Cc: Andy Lutomirsk
For flushing the TLB, the ASID which has been programmed into the hardware
must be known. That differs from what is in 'cpu_tlbstate'.
Add functions to transform the 'cpu_tlbstate' values into to the one
programmed into the hardware (CR3).
It's not easy to include mmu_context.h into tlbflush.h,
From: Peter Zijlstra
atomic64_inc_return() already implies smp_mb() before and after.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laig
From: Dave Hansen
With PAGE_TABLE_ISOLATION the user portion of the kernel page tables is
poisoned with the NX bit so if the entry code exits with the kernel page
tables selected in CR3, userspace crashes.
But doing so trips the p4d/pgd_bad() checks. Make sure it does not do
that.
Signed-off-b
From: Andy Lutomirski
Provide infrastructure to:
- find a kernel PMD for a mapping which must be visible to user space for
the entry/exit code to work.
- walk an address range and share the kernel PMD with it.
This reuses a small part of the original KAISER patches to populate the
user sp
From: Thomas Gleixner
Force the entry through the trampoline only when PTI is active. Otherwise
go through the normal entry code.
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
Reviewed-by: Borislav Petkov
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Brian Gerst
Cc: Dave Hansen
From: Andy Lutomirski
This allows the CPU entry area PMDs to be shared between the kernel and
user space page tables.
[ tglx: Fixed bottom of by one and added guards so other fixmaps can be
added later ]
Signed-off-by: Andy Lutomirski
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas G
From: Dave Hansen
Kernel page table isolation requires to have two PGDs. One for the kernel,
which contains the full kernel mapping plus the user space mapping and one
for user space which contains the user space mappings and the minimal set
of kernel mappings which are required by the architectu
From: Thomas Gleixner
Share the entry text PMD of the kernel mapping with the user space
mapping. If large pages are enabled this is a single PMD entry and at the
point where it is copied into the user page table the RW bit has not been
cleared yet. Clear it right away so the user space visible m
From: Thomas Gleixner
The (irq)entry text must be visible in the user space page tables. To allow
simple PMD based sharing, make the entry text PMD aligned.
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
From: Thomas Gleixner
The Intel PEBS/BTS debug store is a design trainwreck as is expects virtual
addresses which must be visible in any execution context.
So it is required to make these mappings visible to user space when kernel
page table isolation is active.
Provide enough room for the buff
From: Thomas Gleixner
That makes it automatically a shared mapping along with the cpu_entry_area.
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laight
Cc: Denys Vlasenko
Cc:
From: Hugh Dickins
The BTS and PEBS buffers both have their virtual addresses programmed into
the hardware. This means that any access to them is performed via the page
tables. The times that the hardware accesses these are entirely dependent
on how the performance monitoring hardware events ar
From: Dave Hansen
If changing the page tables in such a way that an invalidation of all
contexts (aka. PCIDs / ASIDs) is required, they can be actively invalidated
by:
1. INVPCID for each PCID (works for single pages too).
2. Load CR3 with each PCID without the NOFLUSH bit set
3. Load CR3 w
From: Andy Lutomirski
Shrink vmalloc space from 16384TiB to 12800TiB to enlarge the hole starting
at 0xff90 to be a full PGD entry.
A subsequent patch will use this hole for the pagetable isolation LDT
alias.
Signed-off-by: Andy Lutomirski
Signed-off-by: Thomas Gleixner
Cc: Kees C
From: Dave Hansen
In preparation to adding additional PCID flushing, abstract the
loading of a new ASID into CR3.
[ PeterZ: Split out from big combo patch ]
Signed-off-by: Dave Hansen
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lu
From: Dave Hansen
This uses INVPCID to shoot down individual lines of the user mapping
instead of marking the entire user map as invalid. This
could/might/possibly be faster.
This for sure needs tlb_single_page_flush_ceiling to be redetermined;
esp. since INVPCID is _slow_.
[ Peterz: Split out
From: Dave Hansen
Finally allow CONFIG_PAGE_TABLE_ISOLATION to be enabled.
PARAVIRT generally requires that the kernel not manage its own page tables.
It also means that the hypervisor and kernel must agree wholeheartedly
about what format the page tables are in and what they contain.
PAGE_TABLE
From: Peter Zijlstra
Ideally we'd also use sparse to enforce this separation so it becomes much
more difficult to mess up.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian G
From: Peter Zijlstra
Most NMI/paranoid exceptions will not in fact change pagetables and would
thus not require TLB flushing, however RESTORE_CR3 uses flushing CR3
writes.
Restores to kernel PCIDs can be NOFLUSH, because we explicitly flush the
kernel mappings and now that we track which user PC
The upcoming support for dumping the kernel and the user space page tables
of the current process would create more random files in the top level
debugfs directory.
Add a page table directory and move the existing file to it.
Signed-off-by: Borislav Petkov
Signed-off-by: Ingo Molnar
Signed-off-
From: Peter Zijlstra
We can use PCID to retain the TLBs across CR3 switches; including those now
part of the user/kernel switch. This increases performance of kernel
entry/exit at the cost of more expensive/complicated TLB flushing.
Now that we have two address spaces, one for kernel and one for
From: Thomas Gleixner
ptdump_walk_pgd_level_checkwx() checks the kernel page table for WX pages,
but does not check the PAGE_TABLE_ISOLATION user space page table.
Restructure the code so that dmesg output is selected by an explicit
argument and not implicit via checking the pgd argument for !NU
From: Andy Lutomirski
With PTI enabled, the LDT must be mapped in the usermode tables somewhere.
The LDT is per process, i.e. per mm.
An earlier approach mapped the LDT on context switch into a fixmap area,
but that's a big overhead and exhausted the fixmap space when NR_CPUS got
big.
Take adva
From: Thomas Gleixner
Add two debugfs files which allow to dump the pagetable of the current
task.
current_kernel dumps the regular page table. This is the page table which
is normally shared between kernel and user space. If kernel page table
isolation is enabled this is the kernel space mappin
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