Am 25.09.2017 12:40 schrieb Harinath Nampally:
Improves code readability, no impact on functionality.
Signed-off-by: Harinath Nampally
---
I'd prefer a shorter subject line here too, see patch 2/3.
Hello Kalyan,
On Wed, 27 Sep 2017 13:55:16 +1300
Kalyan Kinthada wrote:
> When the arbitration between NOR and NAND flash is enabled
> the field bit[21] in the Data Flash Control Register
> needs to be set to 1 according to guidleine GL-5830741.
>
> This commit sets the FORCE_CSX bit to 1 for
Hi Markus,
On Tue, Sep 26, 2017 at 10:05:59PM +0200, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Tue, 26 Sep 2017 22:00:05 +0200
>
> Omit an extra message for a memory allocation failure in this function.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-
Am 25.09.2017 12:40 schrieb Harinath Nampally:
Improves code readability, no impact on functionality.
Signed-off-by: Harinath Nampally
Please make the headline shorter and put some of it in the git commit
message.
(And please just resend it "--in-reply-to" this conversation, this patch
nr 2
Am Mittwoch, 27. September 2017, 00:42:46 CEST schrieb Josh Poimboeuf:
> > Here is another variant of the warning, it matches the attached .config:
> I can take a look at it. Unfortunately, for these types of issues I
> often need the vmlinux file to be able to make sense of the unwinder
> dump.
Am 25.09.2017 12:40 schrieb Harinath Nampally:
'mma8452_read_thresh' and 'mma8452_write_thresh' functions
does more than just read/write threshold values.
They also handle IIO_EV_INFO_HIGH_PASS_FILTER_3DB and
IIO_EV_INFO_PERIOD therefore renaming to generic names.
Improves code readability, no
On 2017年09月26日 15:55, Nickey Yang wrote:
This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must
Hi Rob,
On 09/19/2017 07:40 PM, Rob Herring wrote:
Thanks for reviewing the patch.
On Tue, Sep 12, 2017 at 05:31:07PM +0530, Vivek Gautam wrote:
ARM MMU-500 implements a TBU (uTLB) for each connected master
besides a single TCU which controls and manages the address
translations. Each of the
On Tuesday, 26 September 2017 23:31:29 CEST Greg Kroah-Hartman wrote:
> On Tue, Sep 26, 2017 at 05:50:55PM +0200, Federico Vaga wrote:
> > Hello,
> >
> > I'm writing a sysfs binary attribute that makes use of the `mmap`
> > operation.
> Eeek, why? What are you using that for?
I have a bus (VME)
On Tue, Sep 26, 2017 at 11:30:57AM -0600, Ross Zwisler wrote:
> I agree that Christoph's idea about having the system intelligently adjust to
> use DAX based on performance information it gathers about the underlying
> persistent memory (probably via the HMAT on x86_64 systems) is interesting,
> bu
> As long as I know, the last product with this solution was shipped
> at 2010. Thus the driver is under maintenance.
Thanks for your information.
> I have some tasks for this driver as well as drivers in ALSA firewire stack,
> however basically this driver is under maintenance and might not get
>
> On Tue, Sep 26, 2017 at 02:36:57AM -0400, Pankaj Gupta wrote:
> >
> > >
> > > A bit late to a party, but:
> > >
> > > On Mon, Dec 8, 2014 at 12:50 AM, Amos Kong wrote:
> > > > From: Rusty Russell
> > > >
> > > > There's currently a big lock around everything, and it means that we
> > > >
From: Wanpeng Li
PLE_Window: Software can configure this field as an upper bound on the amount
of time
a guest is allowed to execute in a PAUSE LOOP.
KVM doesn't expose the PLE capability to the L1 hypervsior, however, ple_window
still
shows the default value on L1 hypervsior. This patch fixes
From: Wanpeng Li
Vectors 0-15 are reserved, and a physical LAPIC - upon sending or
receiving one - would generate an APIC error instead of doing the
requested action. Make our emulation behave similarly.
Cc: Paolo Bonzini
Cc: Radim Krčmář
Signed-off-by: Wanpeng Li
---
arch/x86/kvm/lapic.c |
On 09/27/2017 04:14 AM, Subhash Jadavani wrote:
On 2017-08-03 23:48, Vivek Gautam wrote:
Set the phy mode based on the UFS HS PA mode. This lets the
controller let phy know the mode in which the PHY Adapter is
running and set the phy rates accordingly.
Signed-off-by: Vivek Gautam
---
driver
The majority of the clocks in the system are gates paired with a reset
controller that holds the IP in reset.
This borrows from clk_hw_register_gate, but registers two 'gates', one
to control the clock enable register and the other to control the reset
IP. This allows us to enforce the ordering:
There are some resets that are not associated with gates. These are
represented by a reset controller.
Signed-off-by: Joel Stanley
---
v3:
- Add named initalisers for the reset defines
- Add define for ADC
---
drivers/clk/clk-aspeed.c | 82 +++-
i
This registers a platform driver to set up all of the non-core clocks.
The clocks that have configurable rates are now registered.
Signed-off-by: Joel Stanley
--
v3:
- Fix bclk and eclk calculation
- Seperate out ast2400 and ast25000 for pll calculation
Signed-off-by: Joel Stanley
---
driv
This adds the stub of a driver for the ASPEED SoCs. The clocks are
defined and the static registration is set up.
Signed-off-by: Joel Stanley
---
v3:
- use named initlisers for aspeed_gates table
- fix clocks typo
- Move ASPEED_NUM_CLKS to the bottom of the list
- Put gates at the start of th
This registers the core clocks; those which are required to calculate
the rate of the timer peripheral so the system can load a clocksource
driver.
Signed-off-by: Joel Stanley
---
v3:
- Fix ast2400 ahb calculation
- Remove incorrect 'this is wrong' comment
- Separate out clkin calc to be p
This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from
Aspeed.
This is version three of the series. Version one contained two patches; an
update
to the binding document and a single patch for the driver. Lee has merged the
bindings change, so that is dropped from this series, an
Santosh Sivaraj writes:
> * Sergey Senozhatsky wrote (on 2017-09-20
> 16:29:02 +):
>
>> Hello
>>
>> RFC
>>
>> On some arches C function pointers are indirect and point to
>> a function descriptor, which contains the actual pointer to the code.
>> This mostly doesn'
On Sep 27 2017 15:19, Bhumika Goyal wrote:
Make these const as they are only passed to a const argument of the
function snd_pcm_set_ops in the file referencing them. Also, add const
to the declaration in the headers.
Structures found using Coccinelle and changes done by hand.
Signed-off-by: Bhu
Hi all,
News: I will not be doing linux-next releases from Setp 30 to Oct 30
(inclusive).
Changes since 20170926:
The cifs tree lost its build failure.
The staging tree lost its build failure.
Non-merge commits (relative to Linus' tree): 2216
2254 files changed, 69344 insertions(+),
Hi Subhash,
On Wed, Sep 27, 2017 at 4:43 AM, Subhash Jadavani
wrote:
> Hi Vivek,
>
> Please find one comment inline below, rest look good.
>
> Regards,
> Subhash
>
>
> On 2017-08-03 23:48, Vivek Gautam wrote:
>>
>> Refactor ufs_qcom_power_up_sequence() to get rid of ugly
>> exported phy APIs and
Make these const as they are only passed to a const argument of the
function snd_pcm_set_ops in the file referencing them. Also, add const
to the declaration in the headers.
Structures found using Coccinelle and changes done by hand.
Signed-off-by: Bhumika Goyal
---
sound/usb/line6/capture.c |
On Mon, Sep 25, 2017 at 10:40 PM, Andrew Jeffery wrote:
> On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote:
>> + /*
>> + * Memory controller (M-PLL) PLL. This clock is configured by the
>> + * bootloader, and is exposed to Linux as a read-only clock rate.
>> + */
>> +
On Mon, Sep 25, 2017 at 10:54 PM, Andrew Jeffery wrote:
> On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote:
>> +static const u8 aspeed_resets[] = {
>> + 25, /* x-dma */
>> + 24, /* mctp */
>> + 23, /* adc */
>> + 22, /* jtag-master */
>> + 18, /* mic */
>> + 9, /* pwm
On Mon, Sep 25, 2017 at 10:02 PM, Andrew Jeffery wrote:
>> +static const struct clk_div_table ast2400_div_table[] = {
>> + { 0x0, 2 },
>> + { 0x1, 4 },
>> + { 0x2, 6 },
>> + { 0x3, 8 },
>> + { 0x4, 10 },
>> + { 0x5, 12 },
>> + { 0x6, 14 },
>> + { 0x7, 16 },
>> +
On Mon, Sep 25, 2017 at 1:40 PM, Andrew Jeffery wrote:
>> +struct aspeed_clk_gate {
>> + struct clk_hw hw;
>> + struct regmap *map;
>> + u8 clock_idx;
>> + s8 reset_idx;
>> + u8 flags;
>> + spinlock_t *lock;
>> +};
>
> It fee
On 2017年09月26日 15:55, Nickey Yang wrote:
Rockchip driver has been moved to using the
DRM_DEV_ERROR log messages, so change all
instances of dev_err.
Signed-off-by: Nickey Yang
Hi Nickey
Haneen Mohammed already send similar patch, and it was applied, see following
patch on drm-misc-next
On Tue, Sep 26, 2017 at 6:56 PM, Palmer Dabbelt wrote:
> As per suggestions on our v8 patch set, I've split the core architecture code
> out from our drivers and would like to submit this patch set to be included
> into linux-next, with the goal being to be merged in during the next merge
> window
On Tue, Sep 26, 2017 at 10:15 PM, Tycho Andersen wrote:
> Hi,
>
> On Fri, Sep 22, 2017 at 05:22:29PM +0200, Oleg Nesterov wrote:
>> On 09/21, Kees Cook wrote:
>> > Can you resend the two patches; I can send the backport to -stable
>> > manually...
>>
>> Not sure I understand... Do you mean this f
fls and __fls will now require boot time patching on T4
and above. Redefining these functions under arc/sparc/lib.
Signed-off-by: Vijay Kumar
Reviewed-by: Babu Moger
---
arch/sparc/include/asm/bitops_64.h |7 +-
arch/sparc/lib/Makefile|1 +
arch/sparc/lib/fls.S
For T4 and above, patch fls and __fls functions
at the boot time to use lzcnt instruction.
Signed-off-by: Vijay Kumar
Reviewed-by: Babu Moger
---
arch/sparc/Makefile |1 +
arch/sparc/kernel/head_64.S |2 ++
arch/sparc/lib/Makefile |3 +++
arch/sparc/lib/NG4fls.S |
SPARC provides lzcnt instruction (with VIS3) which can be used to
optimize fls, fls64 and __fls functions. For the systems that supports
lzcnt instruction, we now do boot time patching to use sparc
optimized fls, fls64 and __fls functions.
Vijay Kumar (2):
sparc64: Define SPARC default fls an
On Wed, 27 Sep 2017 09:27:34 +1000
Stephen Rothwell wrote:
> Commit
>
> fc9abdb8a661 ("samples/kprobes: Add s390 case in kprobe example module")
>
> is missing a Signed-off-by from its committer.
Fixed, thanks!
--
blue skies,
Martin.
"Reality continues to ruin my life." - Calvin.
Hi Wei-Ning,
On Tue, Sep 26, 2017 at 8:03 PM, Wei-Ning Huang wrote:
>
> The current hid-multitouch driver only allow the report of two
> orientations, vertical and horizontal. We use the Azimuth orientation
> usage 0x5b under the Digitizer usage page to report orientation directly
> from the hid
On 2017/9/26 19:00, Michal Hocko wrote:
> On Tue 26-09-17 11:45:16, Vlastimil Babka wrote:
>> On 09/26/2017 11:22 AM, Xishi Qiu wrote:
>>> On 2017/9/26 17:13, Xishi Qiu wrote:
> This is still very fuzzy. What are you actually trying to achieve?
I don't expect page fault any more afte
From: Sahitya Tummala
There is a rare scenario in HW, where the first clear pulse could
be lost when the actual reset and clear/read of status register
are happening at the same time. Fix this by retrying upto 10 times
to ensure the status register gets cleared. Otherwise, this will
lead to a spu
Register writes which change voltage of IO lines or turn the IO bus
on/off require controller to be ready before progressing further. When
the controller is ready, it will generate a power irq which needs to be
handled. The thread which initiated the register write should wait for
power irq to comp
Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific
register read and write APIs, if registered, can be used.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
inde
From: Subhash Jadavani
SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by registering the interrupt
handler), we need to ensure that any pending power irq interrupt s
Register writes which change voltage of IO lines or turn the IO bus on/off
require sdhc controller to be ready before progressing further. Once a
register write which affects IO lines is done, the driver should wait for
power irq from controller. Once the irq comes, the driver should acknowledge
th
Hi David,
On Tuesday, 26 September 2017 21:53:21 PDT David Miller wrote:
> From: Paul Burton
> Date: Tue, 26 Sep 2017 21:30:56 -0700
>
> > Nobody said that you are required to do anything, I suggested that
> > it would be beneficial if you were to suggest a change to the
> > documented DMA API s
Hi Hans,
Thank you very much for your review.
On 2017/9/25 21:24, Hans Verkuil wrote:
Hi Wenyou,
On 18/09/17 08:39, Wenyou Yang wrote:
To improve the readability of code, split the format array into two,
one for the format description, other for the register configuration.
Meanwhile, add the
pidhash is no longer required as all the information
can be looked up from idr tree. nr_hashed represented
the number of pids that had been hashed. Since, nr_hashed and
PIDNS_HASH_ADDING are no longer relevant, it has been renamed
to pid_allocated and PIDNS_ADDING respectively.
Signed-off-by: Garg
This patch replaces the current bitmap implemetation for
Process ID allocation. Functions that are no longer required,
for example, free_pidmap(), alloc_pidmap(), etc. are removed.
The rest of the functions are modified to use the IDR API.
The change was made to make the PID allocation less complex
This patch series replaces kernel bitmap implementation of PID allocation
with IDR API. These patches are written to simplify the kernel by replacing
custom code with calls to generic code.
The following are the stats for pid and pid_namespace object files
before and after the replacement. There
On Tue, Sep 26, 2017 at 03:21:29PM +0200, Michal Hocko wrote:
> On Thu 21-09-17 09:33:10, Huang, Ying wrote:
> > From: Huang Ying
> >
> > This patch adds a new Kconfig option VMA_SWAP_READAHEAD and wraps VMA
> > based swap readahead code inside #ifdef CONFIG_VMA_SWAP_READAHEAD/#endif.
> > This is
Sergey Senozhatsky writes:
> On (09/22/17 16:48), Luck, Tony wrote:
> [..]
>> Tested patch series on ia64 successfully.
>>
>> Tested-by: Tony Luck
>
> thanks!
>
>> After this goes upstream, you should submit a patch to get rid of
>> all uses of %pF (70 instances in 35 files) and %pf (63 in 34)
From: Paul Burton
Date: Tue, 26 Sep 2017 21:30:56 -0700
> Nobody said that you are required to do anything, I suggested that
> it would be beneficial if you were to suggest a change to the
> documented DMA API such that it allows your usage where it currently
> does not.
Documentation is often w
From: Mika Westerberg
Date: Mon, 25 Sep 2017 14:07:38 +0300
> +struct thunderbolt_ip_header {
> + u32 route_hi;
> + u32 route_lo;
> + u32 length_sn;
> + uuid_t uuid;
> + uuid_t initiator_uuid;
> + uuid_t target_uuid;
> + u32 type;
> + u32 command_id;
> +} __packed;
From: Mika Westerberg
Date: Mon, 25 Sep 2017 14:07:24 +0300
> +struct tb_property_entry {
> + u32 key_hi;
> + u32 key_lo;
> + u16 length;
> + u8 reserved;
> + u8 type;
> + u32 value;
> +} __packed;
> +
> +struct tb_property_rootdir_entry {
> + u32 magic;
> + u32 le
From: Mika Westerberg
Date: Mon, 25 Sep 2017 14:07:28 +0300
> +struct icm_fr_event_xdomain_connected {
> + struct icm_pkg_header hdr;
> + u16 reserved;
> + u16 link_info;
> + uuid_t remote_uuid;
> + uuid_t local_uuid;
> + u32 local_route_hi;
> + u32 local_route_lo;
> +
Hi David,
On Tuesday, 26 September 2017 19:52:44 PDT David Miller wrote:
> From: Paul Burton
> Date: Tue, 26 Sep 2017 14:30:33 -0700
>
> > I'd suggest that at a minimum if you're unwilling to obey the API as
> > described in Documentation/DMA-API.txt then it would be beneficial
> > if you could
On Tue, 2017-09-26 at 12:43 +0200, Borislav Petkov wrote:
> Hi,
>
> On Fri, Aug 18, 2017 at 05:27:53PM -0700, Ricardo Neri wrote:
> >
> > When computing a linear address and segmentation is used, we need
> > to know
> > the base address of the segment involved in the computation. In
> > most of
>
On Thu, 2017-09-21 at 18:11 -0700, David Miller wrote:
> From: Samuel Mendoza-Jonas
> Date: Fri, 22 Sep 2017 11:00:00 +1000
>
> > If we haven't configured a channel yet (or are in the process of doing
> > so) we won't have a hot_channel - does it make more sense to
> > - check against the hot_cha
From: Changbin Du
The struct page.mapping can NULL or points to one object of type
address_space, anon_vma or KSM private structure.
Signed-off-by: Changbin Du
---
v2: add back flag reference.
---
include/linux/mm_types.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
On Tue, Sep 26, 2017 at 04:30:27PM -0700, Andrew Morton wrote:
> On Tue, 26 Sep 2017 15:14:17 +0800 changbin...@intel.com wrote:
>
> > From: Changbin Du
> >
> > The struct page.mapping can NULL or points to one object of type
> > address_space, anon_vma or KSM private structure.
> >
> > ...
> >
On Tue, Sep 26, 2017 at 5:56 PM, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Sep 26, 2017 at 06:59:09AM +, Chen-Yu Tsai wrote:
>> On systems with 2 TCONs such as the A31, it is possible to demux the
>> output of the TCONs to one encoder.
>>
>> Add support for this for the A31.
>>
>> Signed-off-by:
On 2017/9/27 2:59, Atul Garg wrote:
The Arasan controller is based on a FPGA platform and has integrated phy
with specific phy registers used during the initialization and
management of different modes. The phy and the controller are integrated
and registers are very specific to Arasan.
Arasan
From: Miles Chen
dma-debug reports the following warning:
[name:panic&]WARNING: CPU: 3 PID: 298 at kernel-4.4/lib/dma-debug.c:604
debug _dma_assert_idle+0x1a8/0x230()
DMA-API: cpu touching an active dma mapped cacheline [cln=0x0882300]
CPU: 3 PID: 298 Comm: vold Tainted: GW O4.4
On Tue, Sep 26, 2017 at 5:32 PM, Maxime Ripard
wrote:
> On Tue, Sep 26, 2017 at 06:59:08AM +, Chen-Yu Tsai wrote:
>> The HDMI DDC clock found in the CCU is the parent of the actual DDC
>> clock within the HDMI controller. That clock is also named "hdmi-ddc".
>>
>> Rename the one in the CCU to
Hi all,
After merging the tip tree, today's linux-next build (x86_64 allnoconfig)
produced this warning:
kernel/printk/printk.c:1983:12: warning: 'printk_time' defined but not used
[-Wunused-variable]
static int printk_time;
^
Introduced by commit
310b454a8653 ("printk: Add mono
I'm excited to see this being discussed again - it's been years since
the last attempt. I've tried to stay out of the conversation, but I
feel obligated say something and then go back to lurking.
On Tue, Sep 26, 2017 at 10:26 AM, Johannes Weiner wrote:
> On Tue, Sep 26, 2017 at 03:30:40PM +0200,
Different namespace application might require enable TCP Fast Open
feature independently of the host.
This patch series continues making more of the TCP Fast Open related
sysctl knobs be per net-namespace.
Reported-by: Luca BRUNO
Signed-off-by: Haishuang Yan
---
Changes since v5:
* Splite pa
The 'publish' logic is not necessary after commit dfea2aa65424 ("tcp:
Do not call tcp_fastopen_reset_cipher from interrupt context"), because
in tcp_fastopen_cookie_gen，it wouldn't call tcp_fastopen_init_key_once.
Signed-off-by: Haishuang Yan
---
include/net/tcp.h | 2 +-
net/ipv4/af_in
Different namespace application might require different time period in
second to disable Fastopen on active TCP sockets.
Tested:
Simulate following similar situation that the server's data gets dropped
after 3WHS.
C syn-data ---> S
C <--- syn/ack - S
C ack > S
S (accept & wri
Different namespace application might require different tcp_fastopen_key
independently of the host.
David Miller pointed out there is a leak without releasing the context
of tcp_fastopen_key during netns teardown. So add the release action in
exit_batch path.
Tested:
1. Container namespace:
# cat
Hi James,
On Tue, 26 Sep 2017 14:09:47 +1000 Stephen Rothwell
wrote:
>
> After merging the scsi-mkp tree, today's linux-next build (x86_64
> allmodconfig) produced this warning:
>
> drivers/scsi/hisi_sas/hisi_sas_main.c: In function
> 'hisi_sas_controller_reset':
> drivers/scsi/hisi_sas/hisi_s
On Tue, 2017-09-26 at 18:17 +0800, Yingjoe Chen wrote:
> On Tue, 2017-09-26 at 10:02 +0800, Ryder Lee wrote:
> > This patch updates pio, usb and crypto nodes to make them be consistent
> > with the binding documents.
> >
> > Signed-off-by: Ryder Lee
> > ---
> > arch/arm/boot/dts/mt7623.dtsi | 52
From: Kalle Valo
Date: Mon, 25 Sep 2017 11:55:22 +0300
> here a pull request to net for 4.14, more info in the signed tag below.
> Please let me know if there are any problems.
Pulled, thanks Kalle.
From: Vivien Didelot
Date: Tue, 26 Sep 2017 17:15:30 -0400
> DSA currently stores a phy_device pointer in each slave private
> structure. This requires to implement our own ethtool ksettings
> accessors and such.
>
> This patchset removes the private phy_device in favor of the one
> provided in
When bootup a PVM guest with large memory(Ex.240GB), XEN provided initial
mapping overlaps with kernel module virtual space. When mapping in this space
is cleared by xen_cleanhighmap(), in certain case there could be an 2MB mapping
left. This is due to XEN initialize 4MB aligned mapping but xen_cle
The current hid-multitouch driver only allow the report of two
orientations, vertical and horizontal. We use the Azimuth orientation
usage 0x5b under the Digitizer usage page to report orientation directly
from the hid device. A new quirk MT_QUIRK_REPORT_ORIENTATION is added so
user can enable this
From: Tim Hansen
Date: Tue, 26 Sep 2017 20:54:05 -0400
> Signed-off-by: Tim Hansen
This is a poor patch submission on many levels.
But the main problem, is that there is no use of
sk_for_each_entry_offset_rcu() in any of my networking kernel trees.
Referencing code by line number never works,
On 2017/9/27 0:18, Doug Ledford wrote:
On 9/26/2017 9:13 AM, Wei Hu (Xavier) wrote:
On 2017/9/26 1:36, Doug Ledford wrote:
On Mon, 2017-09-25 at 20:18 +0300, Leon Romanovsky wrote:
On Mon, Sep 25, 2017 at 01:06:53PM -0400, Doug Ledford wrote:
On Wed, 2017-08-30 at 17:23 +0800, Wei Hu (Xavi
From: Paul Burton
Date: Tue, 26 Sep 2017 14:30:33 -0700
> I'd suggest that at a minimum if you're unwilling to obey the API as
> described in Documentation/DMA-API.txt then it would be beneficial
> if you could propose a change to it such that it works for you, and
> perhaps we can extend the API
This series adds UniPhier GPIO driver.
The interrupt controller part is implemented by using hierarchy irqdomain.
IMHO, the problem of the hierarchy irqdomain is that drivers must hard-code
the fwspec of the interrupt parent. We will never know the DT binding of
the parent unless we parse #inte
This GPIO controller is used on UniPhier SoC family.
It also serves as an interrupt controller, but interrupt signals are
just delivered to the parent irqchip without any latching or OR'ing.
This type of hardware can be well described with hierarchy IRQ domain.
One unfortunate thing for this devi
This GPIO controller is used on UniPhier SoC family.
The vendor specific property "socionext,interrupt-ranges" is for
specifying interrupt mapping to the parent interrupt controller
because the mapping is not contiguous. It works like "ranges",
but transforms "interrupts" instead of "reg".
Signe
2017-09-25 19:11 GMT+09:00 Thomas Gleixner :
> On Thu, 21 Sep 2017, Linus Walleij wrote:
>
>> On Wed, Sep 13, 2017 at 10:56 AM, Masahiro Yamada
>> wrote:
>>
>> > This helper will be useful for irqchip drivers that need to convert
>> > DT binding into IRQ fwspec.
>> >
>> > Signed-off-by: Masahiro Y
This GPIO controller is used on UniPhier SoC family.
It also serves as an interrupt controller, but interrupt signals are
just delivered to the parent irqchip without any latching or OR'ing.
This type of hardware can be well described with hierarchy IRQ domain.
One unfortunate thing for this devi
This series adds UniPhier GPIO driver.
The interrupt controller part is implemented by using hierarchy irqdomain.
IMHO, the problem of the hierarchy irqdomain is that drivers must hard-code
the fwspec of the interrupt parent. We will never know the DT binding of
the parent unless we parse #inter
This GPIO controller is used on UniPhier SoC family.
The vendor specific property "socionext,interrupt-ranges" is for
specifying interrupt mapping to the parent interrupt controller
because the mapping is not contiguous. It works like "ranges",
but transforms "interrupts" instead of "reg".
Signe
On 09/26/17 10:59, Mauro Carvalho Chehab wrote:
> kernel-doc-nano-HOWTO.txt has a chapter about man pages
> production. While we don't have a working "make manpages"
> target, add it.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
> Documentation/doc-guide/kernel-doc.rst | 61
> +++
On 2017年09月27日 03:26, Michael S. Tsirkin wrote:
On Fri, Sep 22, 2017 at 04:02:30PM +0800, Jason Wang wrote:
Hi:
This series tries to implement basic tx batched processing. This is
done by prefetching descriptor indices and update used ring in a
batch. This intends to speed up used ring updati
On 2017年09月27日 03:25, Michael S. Tsirkin wrote:
On Fri, Sep 22, 2017 at 04:02:35PM +0800, Jason Wang wrote:
This patch implements basic batched processing of tx virtqueue by
prefetching desc indices and updating used ring in a batch. For
non-zerocopy case, vq->heads were used for storing the p
On 09/26/17 10:59, Mauro Carvalho Chehab wrote:
> Add a new section to describe kernel-doc arguments,
> adding examples about how identation should happen, as failing
> to do that causes Sphinx to do the wrong thing.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
> Documentation/doc-guide/kernel
Many ports (m32r, microblaze, mips, parisc, score, and sparc) use
functionally identical copies of various GCC library routine files,
which came up as we were submitting the RISC-V port (which also uses
some of these).
This patch adds a new copy of these library routine files, which are
functional
From: Jonathan Neuschäfer
RISC-V needs a MAINTAINERS entry. Let's add one.
Signed-off-by: Jonathan Neuschäfer
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6671f375f7fc..715e0e534d18 100644
--- a/M
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system. When a file was
init-related this patch contains the entire file.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/bug.h | 88 ++
arch/riscv/include/as
This patch contains all the build infrastructure that actually enables
the RISC-V port. This includes Makefiles, linker scripts, and Kconfig
files. It also contains the only top-level change, which adds RISC-V to
the list of architectures that need a sed run to produce the ARCH
variable when buil
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling. It also contains some generic code that is ABI visible.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu.h | 26 +++
arch/riscv/i
As per suggestions on our v8 patch set, I've split the core architecture code
out from our drivers and would like to submit this patch set to be included
into linux-next, with the goal being to be merged in during the next merge
window. This patch set is based on 4.14-rc2, but if it's better to ha
This patch contains code to manage the RISC-V MMU, including definitions
of the page tables and the page walking code.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/mmu_context.h | 69 ++
arch/riscv/include/asm/page.h | 130 ++
arch/riscv/include/asm/pgalloc.h
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/current.h | 45
arch/riscv/include/asm/kprobes.h | 22 ++
arch/riscv/inclu
On 26.09.2017 17:50, Jon Hunter wrote:
>
> On 26/09/17 00:22, Dmitry Osipenko wrote:
>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
>> on Tegra20/30 SoC's.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23
>> ++
This contains all the code that directly interfaces with the RISC-V
memory model. While this code corforms to the current RISC-V ISA
specifications (user 2.2 and priv 1.10), the memory model is somewhat
underspecified in those documents. There is a working group that hopes
to produce a formal mem
1 - 100 of 894 matches
Mail list logo
