From: Marcus Cooper
Hi All,
please find attached a series of patches to bring i2s support to the
Allwinner H3 SoC. This has been tested with the following setups:
A20 Olimex EVB connected to a pcm5102
Orange Pi 2 connected to a uda1380
Orange Pi 2 hdmi audio playback
Pine 64 connected to the aud
From: Marcus Cooper
The sun8i-h3 introduces a lot of changes to the i2s block such
as different register locations, extended clock division and
more operational modes. As we have to consider the earlier
implementation then these changes need to be isolated.
Signed-off-by: Marcus Cooper
---
...
From: Marcus Cooper
In preparation for changing this driver to support newer SoC
implementations then where needed there has been a switch from
regmap_update_bits to regmap_field. Also included are adjustment
variables although they are not set as no adjustment is required
for the current support
On Thu, Jul 06, 2017 at 02:20:20PM +0200, Pierre-Yves MORDRET wrote:
> +static int stm32_dmamux_probe(struct platform_device *pdev)
> +{
> + struct device_node *node = pdev->dev.of_node;
> + struct device_node *dma_node;
> + struct stm32_dmamux_data *stm32_dmamux;
> + struct resourc
Hi Oliver,
> Currently we are calling usb_submit_urb directly to submit deferred tx
> urbs after unanchor them.
>
> So the usb_giveback_urb_bh would failed to unref it in usb_unanchor_urb
> and cause memory leak:
> unreferenced object 0xffc0ce0fa400 (size 256):
> ...
> backtrace:
>[] __s
On 07/21/2017 09:28 PM, Rob Herring wrote:
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring
Acked-by: Niklas Söderlund
Acked-by: Laurent Pinch
Hi Derek,
> Fixed alignment of all block comments.
> Found using checkpatch
>
> Signed-off-by: Derek Robson
> ---
> drivers/bluetooth/ath3k.c | 3 ++-
> drivers/bluetooth/bt3c_cs.c | 8 +---
> drivers/bluetooth/btmrvl_sdio.c | 6 --
> drivers/bluetooth/btsdio.c | 3 ++-
>
On Sat, 22 Jul 2017, Borislav Petkov wrote:
> On Fri, Jul 21, 2017 at 10:08:12PM +0200, Julia Lawall wrote:
> > Someone pointed out that the rule is probably not OK when the address of
> > the static variable is taken, because then it is likely being used as
> > permanent storage.
>
> Makes sens
On Fri, Jul 21, 2017 at 10:08:12PM +0200, Julia Lawall wrote:
> Someone pointed out that the rule is probably not OK when the address of
> the static variable is taken, because then it is likely being used as
> permanent storage.
Makes sense to me.
> An improved rule is:
Do you think it is worth
On Fri, Jul 21, 2017 at 06:38:52PM +, Kani, Toshimitsu wrote:
> Enterprise platforms have very different model (I do not say it's
> better for everyone from the cost perspective). Typically, such
But you do tell your customers that the error counts they see are not
really what *actually* happ
On Fri, Jul 21, 2017 at 11:24:37AM -0700, Loc Ho wrote:
> X-Gene platforms describe multiple GHES error sources with the same hardware
> error notification type (external interrupt) and interrupt number.
> Change the GHES interrupt request to support sharing the same IRQ.
>
> Co-authored-by: Tuan
On Fri, Jul 21, 2017 at 06:49:42PM -0500, Grygorii Strashko wrote:
> There could be significant delay in CPTS work schedule under high system
> load and on -RT which could cause CPTS misbehavior due to internal counter
> overflow. Usage of own kthread_worker allows to avoid such kind of issues
> an
Hi Sinan, Bjorn:
On 2017/7/14 21:54, Sinan Kaya wrote:
> On 7/13/2017 9:26 PM, Ding Tianhong wrote:
>> There is no code to enable the PCIe Relaxed Ordering bit in the
>> configuration space,
>> it is only be enable by default according to the PCIe Standard
>> Specification, what we
>> do is to d
From: Hanjun Guo
When running 4.13-rc1 on top of D05, I got the boot log:
[0.00] SRAT: PXM 0 -> ITS 0 -> Node 0
[0.00] SRAT: PXM 0 -> ITS 1 -> Node 0
[0.00] SRAT: PXM 0 -> ITS 2 -> Node 0
[0.00] SRAT: PXM 1 -> ITS 3 -> Node 1
[0.00] SRAT: ITS affinity exce
On 2017/7/21 19:42, Ganapatrao Kulkarni wrote:
> Hi Hanjun,
>
>
> On Fri, Jul 21, 2017 at 4:50 PM, Marc Zyngier wrote:
>> On 21/07/17 11:06, Hanjun Guo wrote:
>>> On 2017/7/21 17:51, Hanjun Guo wrote:
From: Hanjun Guo
When running 4.13-rc1 on top of D05, I got the boot log:
>>
Fixed checkpatch errors of "please, no spaces at the start of a line"
Signed-off-by: Derek Robson
---
drivers/staging/pi433/rf69.c | 4 +-
drivers/staging/pi433/rf69_enum.h | 206 +++---
2 files changed, 105 insertions(+), 105 deletions(-)
diff --git a/dri
Fixed checkpatch errors of "no space before tabs"
Signed-off-by: Derek Robson
---
drivers/staging/pi433/pi433_if.c | 12 ++--
drivers/staging/pi433/pi433_if.h | 4 ++--
drivers/staging/pi433/rf69.c | 8
drivers/staging/pi433/rf69.h | 6 +++---
4 files changed, 15 inse
Fixed the alignment of block comments
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/pi433/pi433_if.c | 38 +++--
drivers/staging/pi433/rf69.c | 10 +-
drivers/staging/pi433/rf69_registers.h | 280 -
3 files changed, 169 i
Assorted styel fix across whole driver
Found using checkpatch
Derek Robson (3):
staging: pi433: Style fix - align block comments
staging: pi433: - style fix, space before tabs
staging: pi433: - style fix, space at start of line
drivers/staging/pi433/pi433_if.c | 50 +++---
drivers
Hi Martin,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.13-rc1 next-20170721]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Martin-Wilck/Improve-readbility-of-NVME
On 2017/7/21 19:20, Marc Zyngier wrote:
> On 21/07/17 11:06, Hanjun Guo wrote:
>> On 2017/7/21 17:51, Hanjun Guo wrote:
>>> From: Hanjun Guo
>>>
>>> When running 4.13-rc1 on top of D05, I got the boot log:
>>>
>>> [0.00] SRAT: PXM 0 -> ITS 0 -> Node 0
>>> [0.00] SRAT: PXM 0 -> ITS
From: Elaine Zhang
The RK808 and RK805 PMICs are using a similar register map.
We can reuse the clk driver for the RK805 PMIC. So let's add
the RK805 in the Kconfig description.
Signed-off-by: Elaine Zhang
---
drivers/clk/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On Fri, Jul 21, 2017 at 2:22 PM, Andrew Morton
wrote:
> On Thu, 20 Jul 2017 11:11:06 +0200 Ingo Molnar wrote:
>
>>
>> * Kees Cook wrote:
>>
>> > This implements refcount_t overflow protection on x86 without a noticeable
>> > performance impact, though without the fuller checking of REFCOUNT_FULL
Hi Ganapat,
On 2017/6/8 12:44, Ganapatrao Kulkarni wrote:
> Add code to parse proximity domain in SMMUv3 IORT table to
> set numa node mapping for smmuv3 devices.
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> drivers/acpi/arm64/iort.c | 28 ++--
> 1 file changed, 26 inse
在 2017-05-29 15:34，Chen-Yu Tsai 写道：
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in
[ adding Chris ]
On Fri, Jul 21, 2017 at 4:44 PM, Dan Williams wrote:
> On Fri, Jul 21, 2017 at 3:58 PM, Ingo Molnar wrote:
>>
>> * Dan Williams wrote:
>>
>>> [...]
>>>
>>> * Like perf, ndctl borrows the sub-command architecture and option
>>> parsing from git. So, this code could be refactored
This patchset contains only two patches.
The first one is a minor fix for the A10 pinctrl driver, add a function
of a pin, which used to be missing in A10/A20 pinctrl driver. Thanks for
Chen-Yu for discovering it when reviewing my R40 pinctrl patchset.
The second one is the real R40 pinctrl part,
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v3:
- Fixed a missing comma in v2.
- Added Chen-Yu's review tag.
The PH16 pin has a function with mux id 0x5, which is the DET pin of the
"sim" (smart card reader) IP block.
This function is missing in old versions of A10/A20 SoCs' datasheets and
user manuals, so it's also missing in the old drivers. The newest A10
Datasheet V1.70 and A20 Datasheet V1.41 contai
The SoPine official baseboard uses the A64 chip's EMAC to provide an
Ethernet link.
Add the ethernet0 alias in the device tree, in order to let U-Boot
generate a MAC address from the chip's SID.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 1 +
Allwinner A64 SoC has an EMAC which is used to provide Ethernet
function on several boards.
The EMAC itself doesn't have a fixed MAC address, but the sunxi
mainline U-Boot have the ability to generate one based on the eFUSE
SID in the chip, and add the generated MAC address to the device
tree when
The Pine64 (including the Plus models) board uses the A64 chip's
EMAC to provide Ethernet link.
Add the ethernet0 alias in the device tree, in order to let U-Boot
generate a MAC address from the chip's SID.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 1
The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet
link.
Add the ethernet0 alias in the device tree, in order to let U-Boot
generate a MAC address from the chip's SID.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 +
1 file chan
The SoPine SoM has an AXP803 PMIC connected to the RSB bus of the A64
SoC, and the regulators of the PMIC are used both on the SoM itself and
on the official baseboard
Add related device tree parts to the SoPine SoM DTSI file and the
baseboard DT.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
Add support of AXP803 regulators in the Pine64 device tree.
The phy-supply regulator is also set in EMAC device node, in order to
prevent Ethernet regression by regulator get disabled by regulator
framework.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change the min voltage of vdd-cpux to
The Pine64 and SoPine w/ baseboard boards have an AXP803 PMIC, and the
regulators of the PMIC are used.
This patchset adds the regulators to the device tree of these two boards.
The first patch is for Pine64 and the second if for SoPine w/ official
baseboard.
The patches that drop the dummy regu
On Fri, Jul 21, 2017 at 1:32 PM, Randy Dunlap wrote:
>
> and send with correct file encoding!
Congratulations, you were indeed successful in fixing whatever locale
issue that was biting you.
Linus
Changes from V1 (https://lkml.org/lkml/2017/7/20/180)
* Refactor topology extension logic into __get_topoext() (per Boris)
Suravee Suthikulpanit (2):
x86/amd: Refactor topology extension related code
x86/amd: Fixup cpu_core_id for family17h downcore configuration
arch/x86/kernel/cpu/amd.c
For family17h, current cpu_core_id is directly taken from the value
CPUID_Fn801E_EBX[7:0] (CoreId), which is the physical ID of the
core within a die. However, on system with downcore configuration
(where not all physical cores within a die are available), this could
result in the case where cp
Refactoring in preparation for subsequent changes.
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kernel/cpu/amd.c | 79 ++-
1 file changed, 44 insertions(+), 35 deletions(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/a
On Sat, Jul 22, 2017 at 1:25 AM, Rafael J. Wysocki wrote:
> On Tuesday, July 18, 2017 06:04:19 PM Andy Shevchenko wrote:
>> Some platform might take care of legacy devices on theirs own.
>> Let's allow them to do that by exporting a weak function.
>>
>> Signed-off-by: Andy Shevchenko
>
> I'd rath
On Sat, Jul 22, 2017 at 1:28 AM, Rafael J. Wysocki wrote:
> On Tuesday, July 18, 2017 06:04:20 PM Andy Shevchenko wrote:
>> As per note in 5.2.9 Fixed ACPI Description Table (FADT) chapter of ACPI
>> specification OSPM will ignore fields related to the ACPI HW register
>> interface, one of which i
Fixed alignment of all block comments.
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/bluetooth/ath3k.c | 3 ++-
drivers/bluetooth/bt3c_cs.c | 8 +---
drivers/bluetooth/btmrvl_sdio.c | 6 --
drivers/bluetooth/btsdio.c | 3 ++-
drivers/bluetooth/btuart_c
On 7/17/2017 9:45 PM, santosh.shilim...@oracle.com wrote:
On 7/17/17 8:26 PM, Suman Anna wrote:
Hi Santosh,
The following patch series adds the necessary defconfig options to
keystone_defconfig to enable the TI-SCI protocol and their respective
genpd/clock/reset drivers.
This is the first of
From: Chao Yu
When ->freeze_fs is called from lvm for doing snapshot, it needs to
make sure there will be no more changes in filesystem's data, however,
previously, background threads like GC thread wasn't aware of freezing,
so in environment with active background threads, data of snapshot
becom
(Cc netdev and Intel)
On Tue, Jul 18, 2017 at 1:57 PM, Justin Piszcz wrote:
> Hello,
>
> Kernel: 4.12.0
> Arch: x86_64
>
> What causes this issue?
It is likely a igb driver issue.
>
> [199141.434449] NETDEV WATCHDOG: eth1 (igb): transmit queue 7 timed out
> [199141.434501] [ cut h
Hi Jaegeuk,
On 2017/7/22 4:54, Jaegeuk Kim wrote:
> Hi Chao,
>
> On 07/21, Chao Yu wrote:
>> When ->freeze_fs is called from lvm for doing snapshot, it needs to
>> make sure there will be no more changes in filesystem's data, however,
>> previously, background GC wasn't aware of freezing, so in e
Hi Qiuyang,
This fails xfstests/generic/413.
Thanks,
On 07/20, sunqiuyang wrote:
> From: Qiuyang Sun
>
> This patch implements Direct Access (DAX) in F2FS, including:
> - a mount option to choose whether to enable DAX or not
> - read/write and mmap of regular files in the DAX way
> - zero-o
Andi Kleen [a...@firstfloor.org] wrote:
> From: Andi Kleen
>
> Today, when a JSON file fails parsing the build continues,
> but there are no json files built in, which is difficult to debug later.
> Make the build stop on a parse error instead.
I see the problem and we were being defensive to no
Implement the probe function for the pvcalls frontend. Read the
supported versions, max-page-order and function-calls nodes from
xenstore.
Introduce a data structure named pvcalls_bedata. It contains pointers to
the command ring, the event channel, a list of active sockets and a list
of passive so
Send PVCALLS_CONNECT to the backend. Allocate a new ring and evtchn for
the active socket.
Introduce a data structure to keep track of sockets. Introduce a
waitqueue to allow the frontend to wait on data coming from the backend
on the active socket (recvmsg command).
Two mutexes (one of reads and
Send a PVCALLS_SOCKET command to the backend, use the masked
req_prod_pvt as req_id. This way, req_id is guaranteed to be between 0
and PVCALLS_NR_REQ_PER_RING. We already have a slot in the rsp array
ready for the response, and there cannot be two outstanding responses
with the same req_id.
Wait
Introduce a xenbus frontend for the pvcalls protocol, as defined by
https://xenbits.xen.org/docs/unstable/misc/pvcalls.html.
This patch only adds the stubs, the code will be added by the following
patches.
Signed-off-by: Stefano Stabellini
CC: boris.ostrov...@oracle.com
CC: jgr...@suse.com
---
Send PVCALLS_ACCEPT to the backend. Allocate a new active socket. Make
sure that only one accept command is executed at any given time by
setting PVCALLS_FLAG_ACCEPT_INFLIGHT and waiting on the
inflight_accept_req waitqueue.
sock->sk->sk_send_head is not used for ip sockets: reuse the field to
sto
Implement recvmsg by copying data from the "in" ring. If not enough data
is available and the recvmsg call is blocking, then wait on the
inflight_conn_req waitqueue. Take the active socket in_mutex so that
only one function can access the ring at any given time.
If not enough data is available on
Also add pvcalls-front to the Makefile.
Signed-off-by: Stefano Stabellini
CC: boris.ostrov...@oracle.com
CC: jgr...@suse.com
---
drivers/xen/Kconfig | 9 +
drivers/xen/Makefile | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
index 4545561
Send data to an active socket by copying data to the "out" ring. Take
the active socket out_mutex so that only one function can access the
ring at any given time.
If not enough room is available on the ring, rather than returning
immediately or sleep-waiting, spin for up to 5000 cycles. This small
Implement pvcalls frontend removal function. Go through the list of
active and passive sockets and free them all, one at a time.
Signed-off-by: Stefano Stabellini
CC: boris.ostrov...@oracle.com
CC: jgr...@suse.com
---
drivers/xen/pvcalls-front.c | 28
1 file changed,
Send PVCALLS_LISTEN to the backend.
Signed-off-by: Stefano Stabellini
CC: boris.ostrov...@oracle.com
CC: jgr...@suse.com
---
drivers/xen/pvcalls-front.c | 49 +
drivers/xen/pvcalls-front.h | 1 +
2 files changed, 50 insertions(+)
diff --git a/drivers
Send PVCALLS_BIND to the backend. Introduce a new structure, part of
struct sock_mapping, to store information specific to passive sockets.
Introduce a status field to keep track of the status of the passive
socket.
Introduce a waitqueue for the "accept" command (see the accept command
implementa
Hi all,
this series introduces the frontend for the newly introduced PV Calls
procotol.
PV Calls is a paravirtualized protocol that allows the implementation of
a set of POSIX functions in a different domain. The PV Calls frontend
sends POSIX function calls to the backend, which implements them a
For active sockets, check the indexes and use the inflight_conn_req
waitqueue to wait.
For passive sockets, send PVCALLS_POLL to the backend. Use the
inflight_accept_req waitqueue if an accept is outstanding. Otherwise use
the inflight_req waitqueue: inflight_req is awaken when a new response
is r
Send PVCALLS_RELEASE to the backend and wait for a reply. Take both
in_mutex and out_mutex to avoid concurrent accesses. Then, free the
socket.
Signed-off-by: Stefano Stabellini
CC: boris.ostrov...@oracle.com
CC: jgr...@suse.com
---
drivers/xen/pvcalls-front.c | 86 ++
Hi Punit,
On 07/21/2017 05:20 AM, Punit Agrawal wrote:
The change makes sense.
FWIW,
Acked-by: Punit Agrawal
Thanks, I appreciate that.
I was wondering how you hit the issue. Is there a test case that could
have spotted this earlier?
This was actually just by inspection.
I checked selft
There could be significant delay in CPTS work schedule under high system
load and on -RT which could cause CPTS misbehavior due to internal counter
overflow. Usage of own kthread_worker allows to avoid such kind of issues
and makes it possible to tune priority of CPTS kthread_worker thread on -RT
(
With the low Ethernet connection speed cpdma notification about packet
processing can be received before CPTS TX timestamp event, which is set
when packet actually left CPSW while cpdma notification is sent when packet
pushed in CPSW fifo. As result, when connection is slow and CPU is fast
enough T
With the low speed Ethernet connection CPDMA notification about packet
processing can be received before CPTS TX timestamp event, which is set
when packet actually left CPSW while cpdma notification is sent when packet
pushed in CPSW fifo. As result, when connection is slow and CPU is fast
enough
On Fri, Jul 21, 2017 at 3:58 PM, Ingo Molnar wrote:
>
> * Dan Williams wrote:
>
>> [...]
>>
>> * Like perf, ndctl borrows the sub-command architecture and option
>> parsing from git. So, this code could be refactored into something
>> shared / generic, i.e. the bits in tools/perf/util/.
>
> Just
On 07/21/17 at 07:37pm, Ingo Molnar wrote:
>
> * Baoquan He wrote:
>
> > > > +static inline bool process_efi_entries(unsigned long minimum,
> > > > + unsigned long image_size)
> > >
> > > ugly linebreak again ...
> >
> > The whole line is more than 80. I br
On Sat, Jul 22, 2017 at 12:48:06AM +0300, Alexey Khoroshilov wrote:
> The order of resource deallocations is messed up in acpi_wmi_init().
> It should be vice versa.
>
> Found by Linux Driver Verification project (linuxtesting.org).
>
> Signed-off-by: Alexey Khoroshilov
Eeek. Thank you. Applied
On 2017/07/20 16:07:14 -0700, Paul E. McKenney wrote:
> On Fri, Jul 21, 2017 at 07:52:03AM +0900, Akira Yokosawa wrote:
>> On 2017/07/20 14:42:34 -0700, Paul E. McKenney wrote:
[...]
>>> For the compilers I know about at the present time, yes.
>>
>> So if I respin the patch with the extern, would y
On Fri, Jul 21, 2017 at 1:34 PM, Anna Schumaker
wrote:
>
> gpg claims it was able to sync my key with the keyserver, so hopefully
> you're able to update it now.
I can see the updated key, yes.
However, this:
> Peng Tao (1):
> nfs: add export operations
and probably a couple of other one
On Fri, 23 Jun 2017 15:12:51 +0800 "Huang, Ying" wrote:
> From: Huang Ying
>
> Hi, Andrew, could you help me to check whether the overall design is
> reasonable?
>
> Hi, Johannes and Minchan, Thanks a lot for your review to the first
> step of the THP swap optimization! Could you help me to r
On Fri, 2017-07-21 at 16:17 -0400, Waiman Long wrote:
> On 07/21/2017 03:30 PM, James Bottomley wrote:
> >
> > On Fri, 2017-07-21 at 09:43 -0400, Waiman Long wrote:
> > >
> > > Having a limit for the number of negative dentries does have an
> > > undesirable side effect that no new negative dentr
On Fri, Jul 21, 2017 at 03:29:39AM +, Chakravarty, Souvik K wrote:
> Just missed the email from Darren.
:-)
> Reviewed-by: Souvik K Chakravarty
Thank you Souvik.
While these one liners are OK for trivial changes like this, please note that
Andy and I depend on individual driver maintainers
On 07/21, Andreas Dilger wrote:
> > On Jul 21, 2017, at 2:11 PM, Jaegeuk Kim wrote:
> >
> > This patch adds an ioctl to provide feature information to user.
> > For exapmle, SQLite can use this ioctl to detect whether f2fs support atomic
> > write or not.
>
> Just for reference, ext4 exposes fun
On Thu, 20 Jul 2017 08:56:26 +0200 Michal Hocko wrote:
>
> > > --- a/mm/vmscan.c
> > > +++ b/mm/vmscan.c
> > > @@ -1713,9 +1713,15 @@ shrink_inactive_list(unsigned long nr_to_scan,
> > > struct lruvec *lruvec,
> > > int file = is_file_lru(lru);
> > > struct pglist_data *pgdat = lruvec_pgdat(
Arnd, Olof,
Two DT patches for 4.13, fixing NAND flash support on sama5d2.
The following changes since commit 5771a8c08880cdca3bfb4a3fc6d309d6bba20877:
Linux v4.13-rc1 (2017-07-15 15:22:10 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/abellon
* Dan Williams wrote:
> [...]
>
> * Like perf, ndctl borrows the sub-command architecture and option
> parsing from git. So, this code could be refactored into something
> shared / generic, i.e. the bits in tools/perf/util/.
Just as a side note, stacktool (tools/stacktool/) is using the Git su
On 07/11, Chunyan Zhang wrote:
> Introduce a new binding with its documentation for Spreadtrum clock
> sub-framework.
>
> Signed-off-by: Chunyan Zhang
> ---
> Documentation/devicetree/bindings/clock/sprd.txt | 36
>
> 1 file changed, 36 insertions(+)
> create mode 1006
Looks good,
On 07/21/2017 05:34 AM, Alexandre Torgue wrote:
> Initially each pin was declared in "include/dt-bindings/stm32f429-pinfunc.h"
> and each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX).
> Since this approach was approved, the number of supported MCU has
> increased (
Hi Linus,
Would you be open to the ndctl [1] project moving its development into
the kernel tree? The main reasons why I ask are:
* Unit test development can touch both the kernel-side emulated nvdimm
infrastructure in tools/testing/nvdimm/ and the corresponding tests in
tools/ndctl/test/ in the
Right now if a file includes acpi_numa.h and they don't happen to include
linux/numa.h before it, they get the following warning:
./include/acpi/acpi_numa.h:9:5: warning: "MAX_NUMNODES" is not defined [-Wundef]
#if MAX_NUMNODES > 256
^~~~
Signed-off-by: Ross Zwisler
Acked-by: Rafae
To save someone the time of searching the ACPI spec for "Static Resource
Affinity Table".
Signed-off-by: Ross Zwisler
---
drivers/acpi/numa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/numa.c b/drivers/acpi/numa.c
index edb0c79..917f1cc 100644
--- a/drivers/
On 07/18, Rob Herring wrote:
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
>
> Signed-off-by: Rob Herring
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Maxi
On Thursday, July 13, 2017 02:49:53 PM Viresh Kumar wrote:
> On 13-07-17, 11:19, Michal Simek wrote:
> > From: Shubhrajyoti Datta
> >
> > Add zynqmp to the cpufreq dt platform device.
> >
> > Signed-off-by: Shubhrajyoti Datta
> > Signed-off-by: Michal Simek
> > ---
> >
> > drivers/cpufreq/cp
On Wednesday, July 12, 2017 11:10:14 PM Stephen Boyd wrote:
> On 07/12, Viresh Kumar wrote:
> > Some platforms add the OPPs dynamically from platform specific drivers
> > instead of getting them statically from DT. The cpufreq-dt driver
> > already ignores the return value of dev_pm_opp_of_cpumask_
On Tuesday, July 04, 2017 10:09:21 PM Gustavo A. R. Silva wrote:
> Remove unnecessary static on local variable hostbridge.
> Such variable is initialized before being used,
> on every execution path throughout the function.
> The static has no benefit and, removing it reduces
> the code size.
>
>
We will only reach the lock initialization code
in alloc_swap_slot_cache when the cpu's swap_slots_cache's slots
have not been allocated and swap_slots_cache has not been initialized
previously. So the lock_initialized check is redundant and unnecessary.
Remove lock_initialized flag from swap_slot
Memory allocations can happen before the swap_slots cache initialization
is completed during cpu bring up. If we are low on memory, we could call
get_swap_page and access swap_slots_cache before it is fully initialized.
Add a check in get_swap_page for initialized swap_slots_cache
to prevent this
dax_load_hole() will soon need to call dax_insert_mapping_entry(), so it
needs to be moved lower in dax.c so the definition exists.
dax_wake_mapping_entry_waiter() will soon be removed from dax.h and be made
static to dax.c, so we need to move its definition above all its callers.
Signed-off-by:
To be able to use the common 4k zero page in DAX we need to have our PTE
fault path look more like our PMD fault path where a PTE entry can be
marked as dirty and writeable as it is first inserted, rather than waiting
for a follow-up dax_pfn_mkwrite() => finish_mkwrite_fault() call.
Right now we c
Now that we no longer insert struct page pointers in DAX radix trees the
page cache code no longer needs to know anything about DAX exceptional
entries. Move all the DAX exceptional entry definitions from dax.h to
fs/dax.c.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
---
fs/dax.c
Now that we no longer insert struct page pointers in DAX radix trees we can
remove the special casing for DAX in page_cache_tree_insert(). This also
allows us to make dax_wake_mapping_entry_waiter() local to fs/dax.c,
removing it from dax.h.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
--
Changes since v3:
- Rebased onto the current linux/master which is based on v4.13-rc1.
- Instead of adding vm_insert_mkwrite_mixed() and duplicating code from
vm_insert_mixed(), instead just add a 'mkwrite' parameter to
vm_insert_mixed() and update all call sites. (Vivek)
- Added a sani
When servicing mmap() reads from file holes the current DAX code allocates
a page cache page of all zeroes and places the struct page pointer in the
mapping->page_tree radix tree. This has three major drawbacks:
1) It consumes memory unnecessarily. For every 4k page that is read via a
DAX mmap()
On Tuesday, July 18, 2017 06:04:20 PM Andy Shevchenko wrote:
> As per note in 5.2.9 Fixed ACPI Description Table (FADT) chapter of ACPI
> specification OSPM will ignore fields related to the ACPI HW register
> interface, one of which is SCI_INT.
>
> Follow the spec and ignore any configuration don
On 07/21/17 15:03, Rafael J. Wysocki wrote:
> On Thursday, July 20, 2017 12:13:24 PM frowand.l...@gmail.com wrote:
>> From: Frank Rowand
>>
>> ACPI is impacted by changes to fwnode.h, add a file entry
>> to ACPI
>>
>> Signed-off-by: Frank Rowand
>
> ACK for this one.
>
> Or do you want me to ap
On Tuesday, July 18, 2017 06:04:19 PM Andy Shevchenko wrote:
> Some platform might take care of legacy devices on theirs own.
> Let's allow them to do that by exporting a weak function.
>
> Signed-off-by: Andy Shevchenko
I'd rather do it at the time when acpi_reduced_hw_init() actually needs to
On Thursday, July 20, 2017 03:45:15 PM Lorenzo Pieralisi wrote:
> Some devices have limited addressing capabilities and cannot
> reference the whole memory address space while carrying out DMA
> operations (eg some devices with bus address bits range smaller than
> system bus - which prevents them
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