Ansis Atteka [mailto:aatt...@nicira.com]
> Sent: Tuesday, January 03, 2017 8:41 AM
[...]
> Hayes, in your iperf reproduction environment did you
> 1) connect sender and receiver directly with an Ethernet cable?
> 2) use iperf's TCP mode instead of UDP mode, because I believe that
> with UDP mode pa
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 092ee9fbaf2b..df8ab4fc240a 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -1991,6 +1991,7 @@ registers, find a list below:
PPC | KVM_REG_PPC_TM_VSCR |
diff --git a/Documentation/sphinx/rstFlatTable.py
b/Documentation/sphinx/rstFlatTable.py
index 26db852e3c74..99163598f18b 100644
--- a/Documentation/sphinx/rstFlatTable.py
+++ b/Documentation/sphinx/rstFlatTable.py
@@ -151,6 +151,11 @@ class ListTableBuilder(object):
def buildTableNode(self):
I'm announcing the release of the 4.4.41 kernel.
All users of the 4.4 kernel series must upgrade.
The updated 4.4.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-4.4.y
and can be browsed at the normal kernel.org git web browser:
I'm announcing the release of the 4.8.17 kernel.
--
NOTE, this is the LAST 4.8-stable kernel to be released. This tree is
now end-of-life. Please move to the 4.9-stable tree. If there are any
reasons preventing you from doing this, please let me know.
--
All use
diff --git a/Documentation/sphinx/rstFlatTable.py
b/Documentation/sphinx/rstFlatTable.py
index 55f275793028..25feb0d35e7a 100755
--- a/Documentation/sphinx/rstFlatTable.py
+++ b/Documentation/sphinx/rstFlatTable.py
@@ -157,6 +157,11 @@ class ListTableBuilder(object):
def buildTableNode(self):
I'm announcing the release of the 4.9.2 kernel.
All users of the 4.9 kernel series must upgrade.
The updated 4.9.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
linux-4.9.y
and can be browsed at the normal kernel.org git web browser:
> cat /proc/sys/net/ipv4/tcp_notsent_lowat
-1
> echo 4294967295 > /proc/sys/net/ipv4/tcp_notsent_lowat
-bash: echo: write error: Invalid argument
> echo -2147483648 > /proc/sys/net/ipv4/tcp_notsent_lowat
> cat /proc/sys/net/ipv4/tcp_notsent_lowat
-2147483648
but in documentation we have "tcp_notse
>>> I run into same issue and posted a patch:
>>
>>> "ASoC: Fix binding and probing of auxiliary components".
>>
>> Which I applied so I guess things are fine now without the revert? I'm
>> still working through backlog from the holidays so didn't check
>> properly yet.
>
> This fixes the Allwinn
On 06.01.2017 09:36, Inki Dae wrote:
>
> 2017년 01월 06일 17:18에 Andi Shyti 이(가) 쓴 글:
>> Hi Inki,
>>
>> Thanks for the reply, but...
>>
> +static const struct drm_display_mode default_mode = {
> + .clock = 222372,
> + .hdisplay = 1440,
> + .hsync_start = 1440 + 1,
> + .hsync_end =
On 2017/1/7 0:07, Clemens Gruber wrote:
On Fri, Jan 06, 2017 at 10:54:35AM +0800, Shawn Lin wrote:
On 2017/1/6 8:41, Clemens Gruber wrote:
Hi,
with the current mainline 4.10-rc2 kernel, I can no longer boot from
the eMMC on my i.MX6Q board.
Details:
The eMMC is a Micron MTFC4GACAJCN-1M WT but
Mon, Jan 09, 2017 at 12:15:52AM CET, vivien.dide...@savoirfairelinux.com wrote:
>In the new DTS bindings for DSA (dsa2), the "ethernet" and "link"
>phandles are respectively mandatory and exclusive to CPU port and DSA
>link device tree nodes.
>
>Simplify dsa2.c a bit by checking the presence of suc
Hi Jaechul,
I tested this patch on TM2 board. It is well working
with platform.
Reviewed-by: Chanwoo Choi
Tested-by: Chanwoo Choi
Best Regards,
Chanwoo Choi
On 2017년 01월 09일 16:22, Jaechul Lee wrote:
> Add DT node support for TM2 touchkey device.
>
> Signed-off-by: Beomho Seo
> Signed-off-b
It is possible that device is capable of 64-bit DMA addresses, and
device driver tries to set wide DMA mask, but bridge or bus used to
connect device to the system can't handle wide addresses.
With swiotlb, memory above 4G still can be used by drivers for streaming
DMA, but *dev->mask and dev->dma
Hi Jaechul,
Looks good to me. I tested this patch on TM2 board.
It is well working.
Reviewed-by: Chanwoo Choi
Tested-by: Chanwoo Choi
Best Regards,
Chanwoo Choi
On 2017년 01월 09일 16:22, Jaechul Lee wrote:
> This patch adds support for the TM2 touch key and led
> functionality.
>
> The driver
Add DT node support for TM2 touchkey device.
Signed-off-by: Beomho Seo
Signed-off-by: Jaechul Lee
Signed-off-by: Andi Shyti
Reviewed-by: Javier Martinez Canillas
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boo
This patch adds the binding description of the tm2 touchkey
device driver.
Signed-off-by: Jaechul Lee
Reviewed-by: Javier Martinez Canillas
Reviewed-by: Andi Shyti
Reviewed-by: Chanwoo Choi
Acked-by: Rob Herring
Acked-by: Krzysztof Kozlowski
---
.../bindings/input/cypress,tm2-touchkey.txt
This patch adds support for the TM2 touch key and led
functionality.
The driver interfaces with userspace through an input device and
reports KEY_PHONE and KEY_BACK event types. LED brightness can be
controlled by "/sys/class/leds/tm2-touchkey/brightness".
Signed-off-by: Beomho Seo
Signed-off-by
Hi,
This patch is last three patch from https://lkml.org/lkml/2017/1/6/277.
because 1 and 2 patches have already been merged by Krzysztof.
This patchset adds support for the tm2 touchkey device.
The driver has been ported from Tizen Kernel, originally written
by Beomho. I ported it to the latest
On 06/01/17 22:57, Boris Ostrovsky wrote:
> On 01/06/2017 10:05 AM, Juergen Gross wrote:
>> Today a Xenstore watch event is delivered via a callback function
>> declared as:
>>
>> void (*callback)(struct xenbus_watch *,
>> const char **vec, unsigned int len);
>>
>> As all watch eve
On 2017/1/6 23:56, Clemens Gruber wrote:
On Fri, Jan 06, 2017 at 10:33:49AM +0800, Shawn Lin wrote:
On 2017/1/6 8:41, Clemens Gruber wrote:
Hi,
with the current mainline 4.10-rc2 kernel, I can no longer boot from
the eMMC on my i.MX6Q board.
Details:
The eMMC is a Micron MTFC4GACAJCN-1M WT bu
On 06/01/17 21:52, Boris Ostrovsky wrote:
> On 01/06/2017 10:05 AM, Juergen Gross wrote:
>> The xenbus driver has an awful mixture of internal and global visible
>> headers: some of the internal used only stuff is defined in the
>> global header include/xen/xenbus.h while some stuff defined in inte
The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.
Therefore, we need to add them.
Signed-off-b
>> +if (mask > dev->archdata.parent_dma_mask)
>> +mask = dev->archdata.parent_dma_mask;
>> +
>> +
>
>One empty line is enough...
Ok
>> +/*
>> + * Whatever the parent bus can set. A device must not set
>> + * a DMA mask larger than this.
>> + */
>> +dev->archda
On 2017/1/9 14:34, Hanjun Guo wrote:
Hi Sinan,
On 2017/1/8 5:09, Sinan Kaya wrote:
On 1/5/2017 1:29 PM, Lorenzo Pieralisi wrote:
Commit 618f535a6062 ("ACPI/IORT: Add single mapping function")
introduced a function (iort_node_get_id()) to retrieve ids for IORT
named components.
iort_node_get_i
Commit-ID: 20b1e22d01a4b0b11d3a1066e9feb04be38607ec
Gitweb: http://git.kernel.org/tip/20b1e22d01a4b0b11d3a1066e9feb04be38607ec
Author: Nicolai Stange
AuthorDate: Thu, 5 Jan 2017 13:51:29 +0100
Committer: Ingo Molnar
CommitDate: Sat, 7 Jan 2017 08:58:07 +0100
x86/efi: Don't allocate mem
Commit-ID: fa37361e291bfe528872b9aef5c8644a3fc7ff20
Gitweb: http://git.kernel.org/tip/fa37361e291bfe528872b9aef5c8644a3fc7ff20
Author: Prarit Bhargava
AuthorDate: Thu, 5 Jan 2017 10:09:25 -0500
Committer: Ingo Molnar
CommitDate: Sat, 7 Jan 2017 08:54:38 +0100
perf/x86/intel/uncore: Fix
From: Christoffer Dall
Some bits of the TCR weren't defined and since we're about to use these
in KVM, add these defines.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/pgtable-hwdef.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/
On 2017/1/9 13:41, Jaehoon Chung wrote:
On 01/09/2017 12:39 PM, Ziyuan wrote:
On 01/05/2017 03:34 PM, Shawn Lin wrote:
On 2017/1/5 15:23, Ziyuan Xu wrote:
It's necessary to setup bus if any slots are present.
- update clock after ctrl reset
- if the host has genpd node, we can guarantee the
From: Christoffer Dall
Set the initial exception level of the guest to EL2 if nested
virtualization feature is enabled.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/reset.c
From: Christoffer Dall
Add an option that allows nested hypervisor support.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/Kconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index 6eaf12c..37263ff 10
From: Christoffer Dall
When running in virtual EL2 we use the shadow EL1 systerm register array
for the save/restore process, so that hardware and especially the memory
subsystem behaves as code written for EL2 expects while really running
in EL1.
This works great for EL1 system register accesse
From: Christoffer Dall
When running a nested hypervisor we occasionally have to figure out if
the mode we are switching into is the virtual EL2 mode or a regular
EL0/1 mode.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 6 ++
arch/a
From: Christoffer Dall
We were not allowing userspace to set a more privileged mode for the VCPU
than EL1, but now that we support nesting with a virtual EL2 mode, do
allow this!
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/guest.c | 2 ++
1 file changed, 2 in
Nested virtualization is the ability to run a virtual machine inside another
virtual machine. In other words, it???s about running a hypervisor (the guest
hypervisor) on top of another hypervisor (the host hypervisor).
This series supports nested virtualization on arm64. ARM recently announced an
From: Christoffer Dall
When entering virtual EL2, we need to reflect virtual EL2 register
states to corresponding shadow EL1 registers. We can simply copy them if
their formats are identical. Otherwise, we need to convert EL2 register
state to EL1 register state.
Signed-off-by: Christoffer Dall
Emulate taking an exception to the guest hypervisor running in the
virtual EL2 as described in ARM ARM AArch64.TakeException().
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 14
arch/arm64/include/asm/kvm_emulate.h | 19 +++
arch/arm64/kvm/Makefile
When HCR.NV bit is set, eret instruction execution in the guest
hypervisor will trap with EC code 0x1A. Let ELR_EL2 and SPSR_EL2 state
from the guest's perspective be restored to the hardware on the next
guest entry.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/esr.h | 1 +
arch/arm64/
Forward virtual memory register traps to the guest hypervisor
if it has set corresponding bits to the virtual HCR_EL2.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys
For the same reason we trap virtual memory register accesses in virtual
EL2, we need to trap SPSR_EL1, ELR_EL1 and VBAR_EL1 accesses. ARM v8.3
introduces the HCR_EL2.NV1 bit to be able to trap on those register
accesses in EL1. Do not set this bit until the whole nesting support is
complete.
Signe
Forward ELR_EL1, SPSR_EL1 and VBAR_EL1 traps to the guest hypervisor if
it has set the NV1 bit to the virtual HCR_EL2. The guest hypervisor
would set this NV1 bit to run a hypervisor in its VM (i.e. another level
of nested hypervisor).
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_ar
For the same reason we trap virtual memory register accesses in virtual
EL2, we trap CPACR_EL1 access too. Basically, we don't want the guest
hypervisor to access the real CPACR_EL1, which is used to emulate
virtual EL2. Instead, we want it to access virtual CPACR_EL1 which is
used to run software
From: Christoffer Dall
When running in virtual EL2 mode, we actually run the hardware in EL1
and therefore have to use the EL1 registers to ensure correct operation.
By setting the HCR.TVM and HCR.TVRM we ensure that the virtual EL2 mode
doesn't shoot itself in the foot when setting up what it b
Forward CPACR_EL1 traps to the guest hypervisor if it has configured the
virtual CPTR_EL2 to do so.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 321ecbc..e66f40d 10064
From: Christoffer Dall
If we exit a nested VM with a pending maintenance interrupt from the
GIC, then we need to forward this to the guest hypervisor so that it can
re-sync the appropriate LRs and sample level triggered interrupts again.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Li
VMs used to execute hvc #0 for the psci call. However, when we come to
provide virtual EL2 to the VM, the host OS inside the VM also calls
kvm_call_hyp which is also hvc #0. So, it's hard to differentiate
between them from the host hypervisor's point of view.
So, let the VM execute smc for the psc
Forward exceptions due to hvc instruction to the guest hypervisor.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_nested.h | 5 +
arch/arm64/kvm/Makefile | 1 +
arch/arm64/kvm/handle_exit.c| 11 +++
arch/arm64/kvm/handle_exit_nested.c | 27 +++
Hi Joel,
[auto build test WARNING on next-20170106]
[also build test WARNING on v4.10-rc3]
[cannot apply to linus/master linux/master robh/for-next v4.9-rc8 v4.9-rc7
v4.9-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://git
From: Christoffer Dall
When running a guest hypervisor in virtual EL2, the translation context
has to be separate from the rest of the system, including the guest
EL1/0 translation regime, so we allocate a separate VMID for this mode.
Considering that we have two different vttbr values due to se
From: Christoffer Dall
Abstract stage-2 MMU state into a separate structure and change all
callers referring to page tables, VMIDs, and the VTTBR to use this new
indirection.
This is about to become very handy when using shadow stage-2 page
tables.
Signed-off-by: Christoffer Dall
Signed-off-by
From: Christoffer Dall
Now that the vttbr value will be different depending on the VM's
exception level, we set it on each VM entry.
We only have one mmu instance at this point, but there will be
multiple of them when we run nested VMs.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Li
Hello all,
I'm experiencing display noise in the form of 8x1 pixel bars spuriously
appearing in random locations. This doesn't happen on 4.9, the machine
is an X61s, a Core2Duo 1.8Ghz w/XGA via LVDS.
I was able to bisect the issue to a6a7cc4b7:
commit a6a7cc4b7db6deaeca11cdd38844ea147a354c7a
Au
Register a device for the virtual interface control block(GICH) access
from the guest hypervisor.
TODO: Get GICH address from DT, which is hardcoded now.
Signed-off-by: Jintack Lim
---
arch/arm64/include/uapi/asm/kvm.h | 6 ++
include/kvm/arm_vgic.h | 5 -
virt/kvm/arm/vg
Hi Sinan,
On 2017/1/8 5:09, Sinan Kaya wrote:
On 1/5/2017 1:29 PM, Lorenzo Pieralisi wrote:
Commit 618f535a6062 ("ACPI/IORT: Add single mapping function")
introduced a function (iort_node_get_id()) to retrieve ids for IORT
named components.
iort_node_get_id() takes an index as input to refer t
Emulate GICH interface accesses from the guest hypervisor.
Signed-off-by: Jintack Lim
Signed-off-by: Shih-Wei Li
Signed-off-by: Christoffer Dall
---
arch/arm64/kvm/Makefile| 1 +
virt/kvm/arm/vgic/vgic-v2-nested.c | 207 +
2 files changed, 208
From: Christoffer Dall
Inject stage-2 page faults to the guest hypervisor.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/esr.h | 1 +
arch/arm64/kvm/mmu-nested.c | 30 --
2 files changed, 25 insertions(+), 6 deletions(-)
d
From: Christoffer Dall
Sometimes when we are invalidating the TLB for a certain S2 MMU
context, this context can also have EL2 context associated with it and
we have to invalidate this too.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/kvm/arm.c | 6 ++
arch/arm
If we have a pending IRQ for the guest and the guest expects IRQs
to be handled in its virtual EL2 mode (the virtual IMO bit is set)
and it is not already running in virtual EL2 mode, then we have to
emulate an IRQ exception.
Signed-off-by: Jintack Lim
Signed-off-by: Christoffer Dall
---
virt/k
When entering a nested VM, we set up the hypervisor control interface
based on what the guest hypervisor has set. Especially, we investigate
each list register written by the guest hypervisor whether HW bit is
set. If so, we translate hw irq number from the guest's point of view
to the real hardwa
Since vgic state is properly prepared and is pointed by hw_v2_cpu_if,
let's use it to manipulate vgic.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/hyp/vgic-v2-sr.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kvm/arm/hy
Now that everything is ready, we enable nested virtualization by setting
the HCR NV and NV1 bit.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kvm/hyp/switch.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kv
From: Christoffer Dall
stage2_flush_xxx functions take a pointer to the kvm struct as the first
parameter but they are never used. Clean this up before modifying mmu
code for nested virtualization support.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/kvm/mmu.c | 12
A non-secure EL0 or EL1 read of MPIDR_EL1 should return the value of
VMPIDR_EL2. We emulate this by copying the virtual VMPIDR_EL2 value to
MPIDR_EL1 when entering VM's EL0 or EL1.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/a
From: Christoffer Dall
Unmap/flush shadow stage 2 page tables for the nested VMs as well as the
stage 2 page table for the guest hypervisor.
Note: A bunch of the code in mmu.c relating to MMU notifiers is
currently dealt with in an extremely abrupt way, for example by clearing
out an entire shad
From: Christoffer Dall
If we are faulting on a shadow stage 2 translation, we have to take
extra care in faulting in a page, because we have to collapse the two
levels of stage 2 paging by walking the L2-to-L1 stage 2 page tables in
software.
This approach tries to integrate as much as possible
Add the shadow stage-2 MMU context to be used for the nesting, but don't
do anything with it yet.
The host hypervisor maintains mmu structures for each nested VM. When
entering a nested VM, the host hypervisor searches for the nested VM's
mmu using vmid as a key. Note that this vmid is from the gu
From: Christoffer Dall
Make mmu functions non-static so that we can reuse those functions
to support mmu for the nested VMs.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/kvm/mmu.c | 90 +++-
arch/arm64/include/asm/kv
From: Christoffer Dall
Move this little function to the header files for arm/arm64 so other
code can make use of it directly.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_emulate.h | 8
arch/arm/kvm/mmu.c | 8
ar
From: Christoffer Dall
Based on the pseudo-code in the ARM ARM, implement a stage 2 software
page table walker.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_mmu.h | 11 ++
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/include/asm/kvm_mmu.h
The guest hypervisor sets cntvoff_el2 for its VM (i.e. nested VM). Note
that physical/virtual counter value in the guest hypervisor's point of
view is already offsetted by the virtual offset set by the host
hypervisor. Therefore, the correct offset we need to write to the
cntvoff_el2 is the sum o
From: Christoffer Dall
When translating an L2 IPA to an L1 IPA, we some times need to know at
which level this translation occurred and what the resulting permissions
was, so populate the translation result structure with these additional
fields.
Signed-off-by: Christoffer Dall
Signed-off-by: J
Expose physical address of vgic virtual cpu interface.
Signed-off-by: Jintack Lim
---
include/kvm/arm_vgic.h | 1 +
virt/kvm/arm/vgic/vgic-v2.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index 5bda20c..05c7811 100644
--- a/incl
The original kvm_phys_addr_ioremap function only uses mmu pointing to
the VM's mmu context. However, it would be very useful to reuse this
function for the nested mmu context. Therefore, create a function named
__kvm_phys_addr_ioremapp which takes mmu as an argument, and let
kvm_phys_addr_ioremap c
From: Christoffer Dall
So far we were flushing almost the entire universe whenever a VM would
load/unload the SCTLR_EL1 and the two versions of that register had
different MMU enabled settings. This turned out to be so slow that it
prevented forward progress for a nested VM, because a scheduler
Create a mapping from the nested VM's cpu interface to the hardware
virtual cpu interface. This is to allow the nested VM to access virtual
cpu interface directly.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_mmu.h | 3 +++
arch/arm/kvm/mmu.c | 5 +
arch/arm64/in
Each nested VM is supposed to have a mmu (i.e. shadow stage-2 page
table), and we create it when the guest hypervisor writes to vttbr_el2
with a new vmid.
In case the guest hypervisor writes to vttbr_el2 with existing vmid, we
check if the base address is changed. If so, then what we have in the
s
From: Christoffer Dall
When faulting on a shadow stage 2 page table we have to check if the
fault was a permission fault and if so, if that fault needs to be
handled by the guest hypervisor before us, in case the guest hypervisor
has created a less permissive S2 entry than the operation required.
From: Christoffer Dall
Currently, we flush ALL shadow stage-2 page tables on the tlbi
instruction execution. We may be able to do this more efficiently by
considering the vttbr_el2 value of the guest hypervisor, but leave it
for now.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
-
Currently, if a vcpu thread tries to change its own active state when
the irq is already in AP list, it'll loop forever. Since the VCPU thread
has already synced back LR state to the struct vgic_irq, let it modify
its own state safely.
Signed-off-by: Jintack Lim
---
virt/kvm/arm/vgic/vgic-mmio.c
From: Christoffer Dall
This adds a couple of extra data structures:
The nested_vgic_vX structures contain the data manipulated by the guest
hypervisor when it faults/traps on accesses to the GICH_ interface.
The shadow_vgic_vX arrays contain the shadow copies of the LRs. That
is, it is a modif
ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
this bit is set, accessing EL2 registers in EL1 traps to EL2. In
addition, executing following instructions in EL1 will trap to EL2 -
tlbi and at instructions which are undefined when exectued in EL1, eret
instruction, msr/mrs
When HCR.NV bit is set, execution of the EL2 translation regime Address
Translation instructions and TLB maintenance instructions are trapped to
EL2. In addition, execution of the EL1 translation regime Address
Translation instructions and TLB maintenance instructions that are only
accessible from
Forward exceptions due to floating-point register accesses to the guest
hypervisor if it has set CPTR_EL2.TFP bit.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_nested.h | 1 +
arch/arm64/kernel/asm-offsets.c | 1 +
arch/arm64/kvm/handle_exit.c| 3 +++
arch/arm64/kvm/h
Forward exceptions due to WFI or WFE to the guest hypervisor if the
guest hypervisor has set corresponding virtual HCR_EL2.TWX bits.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_nested.h | 1 +
arch/arm64/kvm/handle_exit.c| 11 ++-
arch/arm64/kvm/handle_exit_nested.
With the nested virtualization support, the context of the guest
includes EL2 register states. The host manages a set of virtual EL2
registers. In addition to that, the guest hypervisor supposed to run in
EL2 is now deprivilaged and runs in EL1. So, the host also manages a set
of shadow system reg
From: Christoffer Dall
Set up virutal EL2 context to hardware if the guest exception level is
EL2.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/arch
From: Christoffer Dall
Add a framework to set up the guest's context depending on the guest's
exception level. A chosen context is written to hardware in the lowvisor.
We don't set the virtual EL2 context yet.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm/include/asm
Thanks Hanjun ,
On Mon, Jan 9, 2017 at 10:39 AM, Hanjun Guo wrote:
> Hi Prakash,
> I didn't test "cpuset01" on D05 but according to the test in
> Linaro, LTP full test is passed on D05 with Ard's 2 patches.
>
>>
>> Any idea what might be causing this issue.
>
>
> Since it's not happening on D05,
Connect to the highest rssi with the required SSID in the shadow
table if the connection criteria is based only on the SSID.
For the first matching SSID, an index to the table is saved.
Later the index is updated if matching SSID has a higher
RSSI value than the last saved index.
However if decisi
On Thu, 5 Jan 2017 15:14:50 +0300
Dan Carpenter wrote:
> On Thu, Jan 05, 2017 at 01:03:41PM +0530, Aditya Shankar wrote:
> > Connect to the highest rssi with the required SSID in the shadow
> > table if the connection criteria is based only on the SSID.
> > For the first matching SSID, an index t
On Fri, 6 Jan 2017, Kees Cook wrote:
> On Fri, Jan 6, 2017 at 1:32 PM, Kees Cook wrote:
> > There were some bugs in the JNE64 and JLT64 comparision macros. This fixes
> > them, improves comments, and cleans up the file while we are at it.
> >
> > Reported-by: Stephen Röttger
> > Signed-off-by: M
On Jan 4, 2017, at 22:14, Gustavo A. R. Silva
wrote:
>
> Simplify return logic to avoid unnecessary variable assignments.
> These issues were detected using Coccinelle and the following semantic patch:
>
> @@
> local idexpression ret;
> expression e;
> @@
>
> -ret =
> +return
> e;
> -retur
On 01/09/2017 12:39 PM, Ziyuan wrote:
>
>
> On 01/05/2017 03:34 PM, Shawn Lin wrote:
>> On 2017/1/5 15:23, Ziyuan Xu wrote:
>>> It's necessary to setup bus if any slots are present.
>>> - update clock after ctrl reset
>>> - if the host has genpd node, we can guarantee the clock is available
>>> b
Hi, Yu
> From: Chen, Yu C
> Subject: [PATCH] ACPI / EC: Use busy polling mode when GPE is not enabled
>
> From: Lv Zheng
>
> Previously we have report that during system bootup, the EC command
> was running too slow because the EC GPE has not been enabled yet
> (For example, _REG tries to acces
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.
Signed-off-by: Joel Holdsworth
Reviewed-by: Marek Vasut
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/f
Hi Fengguang,
On 01/06/2017 10:52 PM, kbuild test robot wrote:
Hi Eric,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.10-rc2 next-20170106]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0da
This adds documentation of the device tree bindings of the Lattice iCE40
FPGA driver for the FPGA manager framework.
Signed-off-by: Joel Holdsworth
Acked-by: Rob Herring
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Acked-by: Marek Vasut
---
.../bindings/fpga/lattice-ice40-fpga-mgr.txt
Lattice Semiconductor Corporation is a manufacturer of integrated
circuits and IP products, including low-power FPGAs, video connectivity
devices and millimeter wave wireless products.
Website: http://latticesemi.com
Signed-off-by: Joel Holdsworth
Acked-by: Rob Herring
Acked-by: Alan Tull
Acke
Regards
Shashank
On 12/30/2016 10:23 PM, Jose Abreu wrote:
HDMI 2.0 introduces a new sampling mode called YCbCr 4:2:0.
According to the spec the EDID may contain two blocks that
signal this sampling mode:
- YCbCr 4:2:0 Video Data Block
- YCbCr 4:2:0 Video Capability Map Data Bl
Hi, Borislav
> From: Zheng, Lv
> Subject: RE: 174cc7187e6f ACPICA: Tables: Back port
> acpi_get_table_with_size() and
> early_acpi_os_unmap_memory() from Linux kernel
>
> Hi,
>
> > From: linux-acpi-ow...@vger.kernel.org
> > [mailto:linux-acpi-ow...@vger.kernel.org] On Behalf Of Zheng,
> > Lv
>
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