On 08 October 2016 01:22, Guenter Roeck wrote:
> On 10/07/2016 04:35 PM, Dmitry Torokhov wrote:
> > On Fri, Oct 07, 2016 at 06:01:23PM +, Steve Twiss wrote:
> >> On 07 October 2016 18:02, Guenter Roeck wrote:
> >>
> On 06 October 2016 19:49, Guenter Roeck wrote:
> > On Thu, Oct 06, 201
Hi Shawn,
On 2016/10/8 10:40, Shawn Lin wrote:
> Hi,
>
> 在 2016/10/7 23:22, Gregory CLEMENT 写道:
>> From: Ziji Hu
>>
>> Export sdhci_start_signal_voltage_switch() from sdhci.c.
>> Thus vendor sdhci driver can implement its own signal voltage
>> switch routine.
>>
>
> You can overwtite this callb
Apologies that not everyone got CC'd on the cover letter, like the
rest of the patch series:
https://lkml.org/lkml/2016/10/8/12
Also, this patch series is an RFC, I screwed up the subject line.
Thanks,
Joel
On Fri, Oct 7, 2016 at 10:28 PM, Joel Fernandes wrote:
>
> Currently pstore has a global
* Andy Lutomirski wrote:
> Now that eagerfpu= is gone, remove it from the docs. Whoops.
>
> Fixes: ca6938a1cd8a ("x86/fpu: Hard-disable lazy FPU mode")
> Signed-off-by: Andy Lutomirski
> ---
> Documentation/kernel-parameters.txt | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/
On Fri, Oct 7, 2016 at 10:33 PM, Yinghai Lu wrote:
> On Fri, Oct 7, 2016 at 10:26 PM, Yinghai Lu wrote:
>> On Fri, Oct 7, 2016 at 6:28 AM, tip-bot for Thomas Gleixner
>>> diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
>>> index 32a7d70..6d35baf 100644
>>> --- a/arch/x86/ke
On Fri, Oct 7, 2016 at 10:26 PM, Yinghai Lu wrote:
> On Fri, Oct 7, 2016 at 6:28 AM, tip-bot for Thomas Gleixner
>> diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
>> index 32a7d70..6d35baf 100644
>> --- a/arch/x86/kernel/acpi/boot.c
>> +++ b/arch/x86/kernel/acpi/boot.c
>> @
PMSG now uses ramoops_pstore_write_buf_user instead of ramoops_pstore_write_buf
Remove the case where we check PSTORE_TYPE_PMSG case.
Signed-off-by: Joel Fernandes
---
fs/pstore/ram.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/fs/pstore/ram.c b/fs/pstore/ram.c
index 751197d..519404c
Up until this patch, each of the per CPU buffers appear as a separate
ftrace-ramoops-N file. In this patch we merge all the zones into one and
populate the ftrace-ramoops-0 file.
Signed-off-by: Joel Fernandes
---
fs/pstore/ram.c | 91 +
1 f
In preparation of not locking at all for certain buffers depending on if
there's contention, make locking optional depending if caller requested it.
Signed-off-by: Joel Fernandes
---
fs/pstore/ram.c| 10 +-
fs/pstore/ram_core.c | 27 ---
include/
If FTRACE_PER_CPU flag is passed to ramoops pdata, split the space into
multiple zones depending on the number of CPUs.
This speeds up the performance of function tracing by about 280% in my tests as
we avoid the locking. The trade off being lesser space available per CPU. Let
the ramoops user de
In preparation for merging the per CPU buffers into one buffer when we retrieve
the pstore ftrace data, we store the timestamp as a counter in the ftrace
pstore record. We store the CPU number as well if !PSTORE_CPU_IN_IP, in this
case we shift the counter and may lose ordering there but we preser
Currently ramoops_init_przs is hard wired only for panic dump zone array. In
preparation for the ftrace zone array (one zone per-cpu), make the function
more generic to be able to handle this case.
Add a new ramoops_init_dump_przs function and use the generic function for the
dump prz array.
Sign
Currently pstore has a global spinlock for all zones. Since the zones are
independent and modify different areas of memory, there's no need to have
a global lock, make the lock per-zone to protect the respective zone.
Signed-off-by: Joel Fernandes
---
fs/pstore/ram_core.c | 11 +--
Here's an early RFC for a patch series on improving ftrace throughput with
ramoops. I am hoping to get some early comments so I'm releasing it in advance.
It is functional and tested.
Currently ramoops uses a single zone to store function traces. To make this
work, it has to uses locking to synchr
On Fri, Oct 7, 2016 at 6:28 AM, tip-bot for Thomas Gleixner
wrote:
> Commit-ID: 8237bded3959c6d038798b905485d3ba94b8ea10
> Gitweb: http://git.kernel.org/tip/8237bded3959c6d038798b905485d3ba94b8ea10
> Author: Thomas Gleixner
> AuthorDate: Fri, 7 Oct 2016 14:02:12 +0200
> Committer: Thoma
Hi tglx,
At 10/07/2016 09:00 PM, Thomas Gleixner wrote:
On Fri, 7 Oct 2016, Thomas Gleixner wrote:
On Fri, 7 Oct 2016, Dou Liyang wrote:
Is it possible that the "-1/ox" could appear in the MADT which is one
of the ACPI tables?
According to the SDM the x2apic id is a 32bit ID, so 0xff
This driver allows rpmsg instances to expose access to rpmsg endpoints
to user space processes. It provides a control interface, allowing
userspace to export endpoints and an endpoint interface for each exposed
endpoint.
The implementation is based on prior art by Texas Instrument, Google,
PetaLog
Similar to other subsystems it's useful to provide a mechanism to force
a specific driver match on a device, so introduce this.
Signed-off-by: Bjorn Andersson
---
drivers/rpmsg/rpmsg_core.c | 3 +++
include/linux/rpmsg.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/rpmsg/r
Create and register a rpmsg device for use with the rpmsg user space
interface, allowing user space to access SMD channels.
Also provide the "rpmsg_name" device attribute to expose the edge name
in sysfs, allowing the user to write udev rules for specific rpmsg
devices and their children.
Signed-
Some types of rpmsg drivers does not have a primary endpoint to tie
their existence upon, but wishes to create and destroy endpoints
dynamically, e.g. based on user interactions.
Allow rpmsg drivers to omit a driver callback to signal this case and
make the probe path not create a primary endpoint
SMD channels are created by the remotes in "opening" state, but
sometimes as we close and try to reopen them they linger in closing
state.
Following the search for a matching channel the create_ept() will verify
that the channel is in a suitable state, so we can lax the restrictions
of the search
This patch helps with Sukadev's JSON event tree where such events can happen.
>From Andi Kleen:
Any event inclduing a .c/.o/.bpf currently triggers BPF compilation or loading
and then an error. This can happen for some Intel JSON events, which cannot
be used.
This patch fixes this problem by f
Hi tglx,
At 10/07/2016 09:07 PM, Thomas Gleixner wrote:
On Thu, 6 Oct 2016, Dou Liyang wrote:
+ if (processor->id >= 255) {
+ ++disabled_cpus;
Incrementing disabled_cpus here is simply wrong because 0xff is an invalid
local APIC id. So we can simply return -EINVAL and be
From: Christophe JAILLET
Date: Fri, 7 Oct 2016 22:58:47 +0200
> Size used with 'dma_alloc_coherent()' and 'dma_free_coherent()' should be
> consistent.
> Here, the size of a pointer is used in dma_alloc... and the size of the
> pointed structure is used in dma_free...
>
> This has been spotted
On 2016/10/7 4:18, Arnaldo Carvalho de Melo wrote:
Em Wed, Oct 05, 2016 at 12:47:10PM -0700, Andi Kleen escreveu:
From: Andi Kleen
This is a generic bug fix, but it helps with Sukadev's JSON event tree
where such events can happen.
Any event inclduing a .c/.o/.bpf currently triggers BPF com
From: Xander Huff
Date: Fri, 7 Oct 2016 10:13:22 -0500
> From: Nathan Sullivan
>
> To ensure the dev->phydev pointer is not used after becoming invalid in
> mdiobus_unregister, set it to NULL. This happens when removing the macb
> driver without first taking its interface down, since unregister
Reviewed-by: Kiwoong Kim
> Vendor specific setup_clocks callback may require the clocks managed
> by ufshcd driver to be ON. So if the vendor specific setup_clocks callback
> is called while the required clocks are turned off, it could result into
> unclocked register access.
>
> To prevent poss
Hi Uffe, Arnd and Scott,
Any comments on this latest patcheset?
Could we consider to merge it if no any other changes needed?
:)
Thanks.
Best regards,
Yangbo Lu
> -Original Message-
> From: Y.B. Lu
> Sent: Monday, September 26, 2016 11:15 AM
> To: linux-...@vger.kernel.org; ulf.hans...
Hi Neil,
On 5 October 2016 at 18:44, NeilBrown wrote:
> On Wed, Oct 05 2016, Felipe Balbi wrote:
>
>> Hi Baolin,
>>
>> Baolin Wang writes:
> But you do!
> The mA number from the USB configuration is passed to
> usb_gadget_vbus_draw.
> Your patch passes that to usb_charger_set_cu
On Friday 07 October 2016 08:02 PM, Steve Twiss wrote:
Hi,
On 06 October 2016 17:34, Steve Twiss wrote:
On 06 October 2016 11:38, Keerthy [mailto:a0393...@ti.com], wrote:
+ int cell_num;
No need of cell_num.
+ cell_num = ARRAY_SIZE(da9061_devs);
No need of the above as
vmxnet3_set_mc() still assumes zero is invalid pa:
it assumes dma_mapping_error(...,0) returns true if vmxnet3_copy_mc() fails;
it calls dma_unmap_single() iff new_table_pa is not zero.
The patch adds an explicit variable to track status of new_table_pa.
Found by Linux Driver Verification pro
在 2016/10/7 23:22, Gregory CLEMENT 写道:
From: Ziji Hu
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Three types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Signed-off-by: Hu Ziji
Reviewed-by: Gregory CLEMENT
Hi,
在 2016/10/7 23:22, Gregory CLEMENT 写道:
From: Ziji Hu
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
You can overwtite this callback within your driver itself.
That is what other sdhci variant drivers
The UniPhier reset driver (drivers/reset/reset-uniphier.c) has been
merged. Select ARCH_HAS_RESET_CONTROLLER from the SoC Kconfig.
Signed-off-by: Masahiro Yamada
---
This is a counter-part of the following ARM-32bit variant:
https://patchwork.kernel.org/patch/9341021/
As discussed with Philipp
2016-09-20 16:30 GMT+09:00 Philipp Zabel :
> Am Dienstag, den 20.09.2016, 13:43 +0900 schrieb Masahiro Yamada:
>> The UniPhier reset driver (drivers/reset/reset-uniphier.c) has been
>> merged. Select ARCH_HAS_RESET_CONTROLLER from the SoC Kconfig.
>>
>> Signed-off-by: Masahiro Yamada
>
> Acked-by
On 10/07/16 16:39, Frank Rowand wrote:
> On 10/07/16 08:17, Pantelis Antoniou wrote:
>> Add Juniper's PTXPMB FPGA CPLD driver. Those FPGAs
>> are present in Juniper's PTX series of routers.
>>
>> The MFD driver provices watchdog/i2c/gpio/mtd devices.
>>
>> There are full device tree binding documen
Hi Linus,
Last topical branch, this is the conversion of blk-mq to the new hotplug
state machine. This should merge cleanly.
Please pull!
git://git.kernel.dk/linux-block.git for-4.9/block-smp
Jens Axboe (1):
Merge branc
Hi Linus,
This is the block-irq topic branch for 4.9-rc. It's mostly from
Christoph, and it allows drivers to specify their own mappings, and more
importantly, to share the blk-mq mappings with the IRQ affinity
mappings. It's a good step towards making this work better out of the
box.
This will
With centralized MTU checking, there's nothing productive done by
eth_change_mtu that isn't already done in dev_set_mtu, so mark it as
deprecated and remove all usage of it in the kernel. All callers have been
audited for calls to alloc_etherdev* or ether_setup directly, which means
they all have a
While looking into an MTU issue with sfc, I started noticing that almost
every NIC driver with an ndo_change_mtu function implemented almost
exactly the same range checks, and in many cases, that was the only
practical thing their ndo_change_mtu function was doing. Quite a few
drivers have either 6
On 2016/10/6 7:20, Arnaldo Carvalho de Melo wrote:
Em Mon, Sep 26, 2016 at 07:26:54AM +, Wang Nan escreveu:
This patch add builtin clang, allow perf compile BPF scripts on the fly.
This is the first step to implement what I announced at LinuxCon 2016 NA:
Ok, so I refreshed this series to
Jarod Wilson (2):
net: centralize net_device min/max MTU checking
net: deprecate eth_change_mtu, remove usage
While looking into an MTU issue with sfc, I started noticing that almost
every NIC driver with an ndo_change_mtu function implemented almost
exactly the same range checks, and in many
Hello,
On Friday 07 October 2016 at 04:37:26PM, Dmitry Torokhov has written:
> Hi Christophe,
>
> On Fri, Oct 07, 2016 at 12:41:48PM +0800, Christophe Tordeux wrote:
> > From: Christophe TORDEUX
> >
> > With kernel v4.6 and later, the Sentelic touchpad STL3888_C0 and
> > probably other Sentelic
On Fri, Sep 30, 2016 at 03:15:11PM +0200, Thomas Gleixner wrote:
> On Tue, 27 Sep 2016, Rich Felker wrote:
> > I've managed to get a trace with a stall. I'm not sure what the best
> > way to share the full thing is, since it's large, but here are the
> > potentially interesting parts.
>
> Upload i
Hi folks,
I'm seeing a repeatable crash on my HP EliteBook 840 G2/2216 when
booting it while in a docking station connected to two external
DisplayPort monitors, undocking, and then either logging out or
shutting down -- regardless of whether I've redocked it beforehand or
not. Both logout and shu
Hi Joe,
On 2016/10/8 4:44, Joe Perches wrote:
> On Fri, 2016-10-07 at 17:22 +0200, Gregory CLEMENT wrote:
>> Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host
>> Controller drivers.
> []
>> diff --git a/MAINTAINERS b/MAINTAINERS
> []
>> @@ -7578,6 +7578,11 @@ M:Nicolas Pitre
>> S: Od
The following changes since commit 3eab887a55424fc2c27553b7bfe32330df83f7b8:
Linux 4.8-rc4 (2016-08-28 15:04:33 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
tags/armsoc-drivers
for you to fetch changes up to d6db68b2deaa0158d2
The following changes since commit 3eab887a55424fc2c27553b7bfe32330df83f7b8:
Linux 4.8-rc4 (2016-08-28 15:04:33 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
tags/armsoc-defconfig
for you to fetch changes up to 3f0958d8aea70801
The following changes since commit 3eab887a55424fc2c27553b7bfe32330df83f7b8:
Linux 4.8-rc4 (2016-08-28 15:04:33 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/armsoc-dt
for you to fetch changes up to adff807988f92d4646c50b60
The following changes since commit f2a89d3b2b85b90b05453872aaabfdb412a21a03:
arm64: dts: Fix broken architected timer interrupt trigger (2016-09-14
22:47:22 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/armsoc-dt64
for you
The following changes since commit 3eab887a55424fc2c27553b7bfe32330df83f7b8:
Linux 4.8-rc4 (2016-08-28 15:04:33 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
tags/armsoc-cleanup
for you to fetch changes up to e13688fe618881dd40
The following changes since commit 3eab887a55424fc2c27553b7bfe32330df83f7b8:
Linux 4.8-rc4 (2016-08-28 15:04:33 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/armsoc-soc
for you to fetch changes up to e40454d3f444ba7f8cc78dd
The following changes since commit 3eab887a55424fc2c27553b7bfe32330df83f7b8:
Linux 4.8-rc4 (2016-08-28 15:04:33 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
tags/armsoc-arm64
for you to fetch changes up to a119a2c4c09371619357
Hi Linus,
Here are 749 patches for ARM SoCs for this merge window, a bit less than
average this time. We support 29 new machines but all five SoCs we add
are in a family that is already supported.
Out of 165 developers contributing at least one patch, the most active
by number of patches are:
The following changes since commit d63a5e7c713a68bd368016f2022326a1a91310d8:
clk: sunxi-ng: Add hardware dependency (2016-09-10 11:41:21 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/armsoc-late
for you to fetch changes up
On 10/07/2016 04:35 PM, Dmitry Torokhov wrote:
On Fri, Oct 07, 2016 at 06:01:23PM +, Steve Twiss wrote:
On 07 October 2016 18:02, Guenter Roeck wrote:
On 06 October 2016 19:49, Guenter Roeck wrote:
On Thu, Oct 06, 2016 at 04:28:14PM +, Steve Twiss wrote:
I am using the compatible str
Next part of cleaning up the watermark code for skl. This is easy, since
it seems that we never actually needed to keep track of the linetime in
the skl_wm_values struct anyway.
Signed-off-by: Lyude
Reviewed-by: Paulo Zanoni
Reviewed-by: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Paulo Zanoni
--
First part of cleaning up all of the skl watermark code. This moves the
structures for storing the ddb allocations of each pipe into
intel_crtc_state, along with moving the structures for storing the
current ddb allocations active on hardware into intel_crtc.
Changes since v1:
- Don't replace allo
Having skl_wm_level contain all of the watermarks for each plane is
annoying since it prevents us from having any sort of object to
represent a single watermark level, something we take advantage of in
the next commit to cut down on all of the copy paste code in here.
Changes since v1:
- Style nit
Signed-off-by: Lyude
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2c682bc..6191baf 1
There's not much of a reason this should have the locations to read out
the hardware state hardcoded, so allow the caller to specify the
location and add this function to intel_drv.h. As well, we're going to
need this function to be reusable for the next patch.
Signed-off-by: Lyude
Cc: Maarten La
Finally, add some debugging output for ddb changes in the atomic debug
output. This makes it a lot easier to spot bugs from incorrect ddb
allocations.
Signed-off-by: Lyude
Reviewed-by: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c | 57 ++
Helper we're going to be using for implementing verification of the wm
levels in skl_verify_wm_level().
Signed-off-by: Lyude
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 14 ++
2 files cha
Thanks to Paulo Zanoni for indirectly pointing this out.
Looks like we never actually added any code for checking whether or not
we actually wrote watermark levels properly. Let's fix that.
Signed-off-by: Lyude
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Paulo Zanoni
---
drivers/gpu/drm/i915
Now that we've make skl_wm_levels make a little more sense, we can
remove all of the redundant wm information. Up until now we'd been
storing two copies of all of the skl watermarks: one being the
skl_pipe_wm structs, the other being the global wm struct in
drm_i915_private containing the raw regis
This function is a wreck, let's help it get it's life back together and
cleanup all of the copy pasta here.
(adding Maarten's reviewed-by since this is just a split-up version of one
of the previous patches)
Signed-off-by: Lyude
Reviewed-by: Maarten Lankhorst
Cc: Ville Syrjälä
Cc: Paulo Zanoni
While it (mostly) works, the code for handling watermarks on Skylake has been
kind of ugly for a while. As well a lot of it isn't that friendly to atomic
transactions, Lots of copy paste, redundant wm values, etc. While this isn't a
full cleanup, it's a good start. As well, we add a couple of featu
Added braces to else statements where checkpatch complained.
Signed-off-by: Chase Metzger
---
drivers/staging/greybus/audio_codec.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/greybus/audio_codec.c
b/drivers/staging/greybus/audio_codec.c
index 8a0744b.
Just in case you think that part 0010 is a bit complex setting
up all that infrastructure for just the L3 cache and using
for_each_rdt_resource() all over the place to loop over just one
thing. Here's the payoff.
Untested because I don't have a machine handy that supports L2 ... but this
should be
From: Fenghua Yu
Check CPUID leaves for all the Resource Director Technology (RDT)
Cache Allocation Technology (CAT) bits.
Prescence of allocation features:
CPUID.(EAX=7H, ECX=0):EBX[bit 15] X86_FEATURE_RDT_A
L2 and L3 caches are each separately enabled:
CPUID.(EAX=10H, ECX=0):EBX[bit 1
From: Fenghua Yu
The documentation describes user interface of how to allocate resource
in Intel RDT.
Please note that the documentation covers generic user interface. Current
patch set code only implemente CAT L3. CAT L2 code will be sent later.
Signed-off-by: Fenghua Yu
Signed-off-by: Tony L
From: Fenghua Yu
Cache id is retrieved from APIC ID and CPUID leaf 4 on x86.
For more details see the section on "Cache ID Extraction Parameters" in
"Intel 64 Architecture Processor Topology Enumeration" at
https://software.intel.com/sites/default/files/63/1a/Kuo_CpuTopology_rc1.rh1.final.pdf
A
From: Fenghua Yu
Resource control groups are represented as directories in the resctrl
file system. The root directory describes the default resources available
to tasks that have not been assigned specific resources. Other directories
can be created at the root level to make new resource groups.
From: Fenghua Yu
The root directory all subdirectories are automatically populated
with a read/write (mode 0644) file named "tasks". When read it will
show all the task IDs assigned to the resource group. Tasks can be
added (one at a time) to a group by writing the task ID to the file.
E.g.
Memb
From: Tony Luck
Last of the per resource group files. Also mode 0644. This one shows
the resources available to the group. Syntax depends on whether the
"cdp" mount option was given. With code/data prioritization disabled
it is simply a list of masks for each cache domain. Initial value
allows ac
From: Fenghua Yu
Introduce CONFIG_INTEL_RDT (default: no, dependent on X86 and
CPU_SUP_INTEL) to control inclusion of Resource Director Technology in
the build.
Simple init() routine just checks which features are present. If they are
pr_info() one line summary for each feature.
Signed-off-by:
From: Tony Luck
Now we populate each directory with a read/write (mode 0644) file
named "cpus". This is used to over-ride the resources available
to processes in the default resource group when running on specific
CPUs. Each "cpus" file reads as a cpumask showing which CPUs belong
to this resour
From: Fenghua Yu
We create five new files for Intel RDT resource allocation:
arch/x86/kernel/cpu/intel_rdt.c
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
arch/x86/kernel/cpu/intel_rdt_schemata.c
arch/x86/include/asm/intel_rdt.h
Documentation/x86/intel_rdt_ui.txt
Fenghua Yu will maintain this code.
From: Fenghua Yu
For the convenience of applications we make the decoded values of some
of the CPUID values available in read-only (0444) files.
Signed-off-by: Fenghua Yu
Signed-off-by: Tony Luck
---
arch/x86/include/asm/intel_rdt.h | 24 +
arch/x86/kernel/cpu/intel_rdt_rdtgroup.
Hi Hn,
On Tue, Sep 06, 2016 at 11:47:39AM +, Hn Chen wrote:
> Hi Benjamin,
>
> Sorry for my poor English and leading you misunderstanding.
>
> The FW of WDT8752 can support HIDI2C for Windows products. And then we
> develop this driver.
> So we "borrowed" something from HIDI2C.
> What I try
From: Fenghua Yu
Cache management software needs a name for each instance of a cache of
a particular type.
The current cacheinfo structure does not provide any information about
the underlying hardware so there is no way to expose it.
Hardware with cache management features provides means (cpui
From: Fenghua Yu
Use kernfs as basis for our user interface filesystem. This patch
supports mount/umount, and one mount parameter "cdp" to enable code/data
prioritization (though all we do at this point is ensure that the system
can support CDP). The file system is not populated yet in this patc
From: Fenghua Yu
Hook the x86 scheduler code to update closid based on whether the current
task is assigned to a specific closid or running on a CPU assigned to a
specific closid.
Signed-off-by: Fenghua Yu
Signed-off-by: Tony Luck
---
arch/x86/include/asm/intel_rdt.h | 41
From: Fenghua Yu
Define struct rdt_resource to hold all the parameterized
values for an RDT resource. Fill in some of those values
from CPUID leaf 0x10 (on Haswell we hard code them).
Signed-off-by: Fenghua Yu
Signed-off-by: Tony Luck
---
arch/x86/include/asm/intel_rdt.h | 67
From: Tony Luck
We use the cpu hotplug notifier to catch each cpu in turn and look at
its cache topology w.r.t each of the resource groups. As we discover
new resources, we initialize the bitmask array for each to the default
(full access) value.
Signed-off-by: Tony Luck
Signed-off-by: Fenghua
From: Fenghua Yu
A CLOSID goes into effect when written to the PQR_ASSOC MSR. But this MSR
also contains the RMID used for preformance monitoring of cache occupancy
and memory bandwidth. Move the management code for this MSR out of
arch/x86/events/intel/cqm.c and into generic RDT code so we can c
From: Fenghua Yu
Some Haswell generation CPUs support RDT, but they don't enumerate this
using CPUID. Use rdmsr_safe() and wrmsr_safe() to probe the MSRs on
cpu model 63 (INTEL_FAM6_HASWELL_X)
Signed-off-by: Fenghua Yu
Signed-off-by: Tony Luck
---
arch/x86/events/intel/cqm.c | 2
From: Fenghua Yu
[I know we are in the middle of the merge window ... just putting
these out there now so that if anyone has a boring meeting or plane
ride they can have something interesting to do]
Dave: Got rid of the atomic ops in fork() ... in fact there is no hook
at all now. Memb
From: Fenghua Yu
Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id.
Signed-off-by: Fenghua Yu
Signed-off-by: Tony Luck
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/ABI/testin
2016-10-07 20:30 GMT+08:00 Radim Krčmář :
> 2016-09-30 10:29+0200, Paolo Bonzini:
>> On 29/09/2016 22:41, Radim Krčmář wrote:
>>> for (msr = 0x800; msr <= 0x8ff; msr++) {
>>> if (msr == 0x839 /* TMCCT */)
>>> continue;
>>> -vmx_disable_intercept_ms
On 10/07/16 08:17, Pantelis Antoniou wrote:
> Add Juniper's PTXPMB FPGA CPLD driver. Those FPGAs
> are present in Juniper's PTX series of routers.
>
> The MFD driver provices watchdog/i2c/gpio/mtd devices.
>
> There are full device tree binding documents for the
> master mfd driver and for all sl
On Fri, Oct 7, 2016 at 2:42 PM, Linda Knippers wrote:
>
>
> On 10/7/2016 3:52 PM, Dan Williams wrote:
>> On Fri, Oct 7, 2016 at 11:19 AM, Linda Knippers
>> wrote:
>>> Hi Dan,
>>>
>>> A couple of general questions...
>>>
>>> On 10/7/2016 12:38 PM, Dan Williams wrote:
With the arrival of the
Hi Christophe,
On Fri, Oct 07, 2016 at 12:41:48PM +0800, Christophe Tordeux wrote:
> From: Christophe TORDEUX
>
> With kernel v4.6 and later, the Sentelic touchpad STL3888_C0 and
> probably other Sentelic FSP touchpads are detected as a BYD touchpad and
> lose multitouch features.
>
> During th
On Fri, Oct 7, 2016 at 4:09 PM, Tony Luck wrote:
> On Fri, Oct 7, 2016 at 4:01 PM, Tony Luck wrote:
>> What if there isn't a "next printk" call for hours, or days?
>>
>> That poor little message without a "\n" will sit in the kernel buffers,
>> and the user who might want to see the message can't
On Fri, Oct 07, 2016 at 06:01:23PM +, Steve Twiss wrote:
> On 07 October 2016 18:02, Guenter Roeck wrote:
>
> > > On 06 October 2016 19:49, Guenter Roeck wrote:
> > > > On Thu, Oct 06, 2016 at 04:28:14PM +, Steve Twiss wrote:
> > > > > I am using the compatible string to pick a different c
On Fri, 2016-10-07 at 22:03 +0200, Dmitry Vyukov wrote:
> Hello,
>
> I am hitting lots of the following warnings while running syzkaller
> fuzzer. Seems that path does not hold proper lock.
>
> WARNING: CPU: 1 PID: 12090 at fs/locks.c:610 locks_unlink_lock_ctx+0x2c7/0x370
> CPU: 1 PID: 12090 Comm
This series contains the CPUfreq driver for Broadcom SoCs that use "AVS
Firmware" for voltage and frequency scaling. All voltage and frequency
transitions are performed by the firmware and are therefore hidden from
Linux.
The driver provides a standard CPUfreq interface to other kernel
components
In order to aid debugging, we add a debugfs interface to the driver
that allows direct interaction with the AVS co-processor.
The debugfs interface provides a means for reading all and writing some
of the mailbox registers directly from the shell prompt and enables a
user to execute the communicat
Add the binding document for the new brcmstb-avs-cpufreq driver.
Signed-off-by: Markus Mayer
Acked-by: Viresh Kumar
---
.../bindings/cpufreq/brcm,stb-avs-cpu-freq.txt | 76 ++
MAINTAINERS| 7 ++
2 files changed, 83 insertions(+)
This series contains the CPUfreq driver for Broadcom SoCs that use "AVS
Firmware" for voltage and frequency scaling. All voltage and frequency
transitions are performed by the firmware and are therefore hidden from
Linux.
The driver provides a standard CPUfreq interface to other kernel
components
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