Hi Len, Rafael, and all,
AMD proposed a new instruction named mwaitx. This is an extension of
mwait with a configurable timer (mwaitx = mwait + timer). And mwaitx
will act as mwait if timer is disabled. However, mwait/mwaitx cannot
let cpu core go to C1 state at current AMD processors, but has les
Commit-ID: b41e6ec242cba0151f0b32041cfa728e7ca6e0b7
Gitweb: http://git.kernel.org/tip/b41e6ec242cba0151f0b32041cfa728e7ca6e0b7
Author: Borislav Petkov
AuthorDate: Wed, 13 May 2015 19:42:24 +0200
Committer: Ingo Molnar
CommitDate: Thu, 14 May 2015 07:25:35 +0200
x86/asm/uaccess: Get rid
Commit-ID: 26e7d9dee8a5b6c844178c8e2d91be540ce311c0
Gitweb: http://git.kernel.org/tip/26e7d9dee8a5b6c844178c8e2d91be540ce311c0
Author: Borislav Petkov
AuthorDate: Wed, 13 May 2015 19:42:22 +0200
Committer: Ingo Molnar
CommitDate: Thu, 14 May 2015 07:25:34 +0200
x86/asm/uaccess: Remove
Commit-ID: 9e6b13f761d5914a8c9b83610e8d459653515c94
Gitweb: http://git.kernel.org/tip/9e6b13f761d5914a8c9b83610e8d459653515c94
Author: Borislav Petkov
AuthorDate: Wed, 13 May 2015 19:42:23 +0200
Committer: Ingo Molnar
CommitDate: Thu, 14 May 2015 07:25:34 +0200
x86/asm/uaccess: Unify t
Add eSDHC compatible list for P2041/P3041/P4080/P5020/P5040.
Signed-off-by: Yangbo Lu
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 1 +
ar
Enable interrupt mode to detect card instead of polling mode
for P1020/P4080/P5020/P5040/T1040 by removing the quirk
SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data
transferring performance and avoid the call trace caused by
polling card status sometime.
Signed-off-by: Yangbo Lu
C
* Len Brown wrote:
> > [0.404369] x86: Booting SMP configuration:
> ...
> > [2.737884] x86: Booted up 4 nodes, 120 CPUs
> > [2.743758] smpboot: Total of 120 processors activated (671097.18
> > BogoMIPS)
> >
> > (2.743758-0.404369) = 2.339389 for all 119 processors
> > /119 = .019658
Current code does not lock anything when calculating the TX and RX stats.
As a result, the RX and TX data reported by ifconfig are not accuracy in a
system with high network throughput and multiple CPUs (in my test,
RX/TX = 83% between 2 HyperV VM nodes which have 8 vCPUs and 40G Ethernet).
This p
> [0.404369] x86: Booting SMP configuration:
...
> [2.737884] x86: Booted up 4 nodes, 120 CPUs
> [2.743758] smpboot: Total of 120 processors activated (671097.18 BogoMIPS)
>
> (2.743758-0.404369) = 2.339389 for all 119 processors
> /119 = .01965873109243697478 - lets call it 19ms each
On 05/14/2015 12:53 PM, Alex Williamson wrote:
On Thu, 2015-05-14 at 12:34 +1000, Alexey Kardashevskiy wrote:
On 05/14/2015 09:27 AM, Gavin Shan wrote:
On Wed, May 13, 2015 at 02:51:36PM +0200, Thomas Huth wrote:
On Wed, 13 May 2015 16:30:16 +1000
Alexey Kardashevskiy wrote:
On 05/13/2015 0
On 05/14/2015 01:47 AM, Rafael J. Wysocki wrote:
> ...
If I'm supposed to apply this, I need ACKs from the appropriate people on
all the patches where they are still missing. Thanks!
I believe Thierry Reding will apply the series; your ACK as cpufreq
maintainer for patch 13, and maybe also
CPUCFG is a collection of registers that are mapped to the SoC's signals
from each individual processor core and associated peripherals, such as
resets for processors, L1/L2 cache and other things.
These registers are used for SMP bringup and CPU hotplugging.
Signed-off-by: Chen-Yu Tsai
---
arc
The A80 is a big.LITTLE SoC with 1 cluster of 4 Cortex-A7s and
1 cluster of 4 Cortex-A15s.
This patch adds support to bring up the second cluster and thus all
cores using the common MCPM code. Core/cluster power down has not
been implemented, thus CPU hotplugging and big.LITTLE switcher is
not sup
The PRCM is a collection of clock controls, reset controls, and various
power switches/gates. Some of these can be independently listed and
supported, while a number of CPU related ones are used in tandem with
CPUCFG for SMP bringup and CPU hotplugging.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/b
The A80 stores some magic flags in a portion of the secure SRAM. The
BROM jumps directly to the software entry point set by the SMP code
if the flags are set. This is required for CPU0 hotplugging.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 20
1 file
This sets the flags that makes BROM jump execution on the
primary core (cpu0)to the SMP software entry code.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/mach-sunxi/mcpm.c | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-sunxi/mcpm.c b/arch/arm/mach
Hi everyone,
This is my attempt to support SMP and CPU hot plugging on the Allwinner
A80 SoC. The A80 is a big.Little processor with 2 clusters of 4x Cortex-A7
and 4x Cortex-A15 cores.
Much of the sunxi-specific MCPM code is derived from Allwinner code and
documentation, with some references to t
The A80 includes an ARM CCI-400 interconnect to support multi-cluster
CPU caches.
Also add the default clock frequency for the CPUs.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 46
1 file changed, 46 insertions(+)
diff --git a/arc
The primary core (cpu0) requires setting flags to have the BROM bounce
execution to the SMP software entry code.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/mach-sunxi/mcpm.c | 103 +++--
1 file changed, 99 insertions(+), 4 deletions(-)
diff --git a/arch/arm
On Thu, 14 May 2015 13:55:08 +0800 Yuanhan Liu
wrote:
> On Thu, May 14, 2015 at 03:45:11PM +1000, NeilBrown wrote:
> > On Wed, 29 Apr 2015 10:48:55 +0800 Yuanhan Liu
> > wrote:
> >
> > > diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
> > > index 64d5bea..697d77a 100644
> > > --- a/drivers
On 05/14/2015 07:30 AM, Alex Williamson wrote:
On Tue, 2015-05-12 at 01:39 +1000, Alexey Kardashevskiy wrote:
The existing implementation accounts the whole DMA window in
the locked_vm counter. This is going to be worse with multiple
containers and huge DMA windows. Also, real-time accounting wo
> On May 13, 2015, at 23:36 , Maxime Ripard
> wrote:
>
> Hi Pantelis,
>
> On Wed, May 13, 2015 at 10:38:17AM +0300, Pantelis Antoniou wrote:
>> For DT and in-kernel users there is no interface to the
>> at24 EEPROMs so provide an EEPROM framework interface.
>>
>> This allows us to use AT24 ba
On Wed, May 13, 2015 at 08:41:55AM +0200, Michael S. Tsirkin wrote:
> > This also sounds like a case for implementing a shutdown callback and
> > disabling things properly. A properly shutdown driver should have
> > already disabled MSI's. A driver is responsible for enabling MSIs so it
> > shoul
Signed-off-by: Thiébaud Weksteen
---
scripts/gdb/linux/tasks.py | 16
1 file changed, 16 insertions(+)
diff --git a/scripts/gdb/linux/tasks.py b/scripts/gdb/linux/tasks.py
index 0fa33b0..862a4ae 100644
--- a/scripts/gdb/linux/tasks.py
+++ b/scripts/gdb/linux/tasks.py
@@ -66,6 +6
> -Original Message-
> From: David Miller [mailto:da...@davemloft.net]
> Sent: Wednesday, May 13, 2015 9:52 PM
> To: Simon Xiao
> Cc: KY Srinivasan; Haiyang Zhang; de...@linuxdriverproject.org;
> net...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH net-next,1/1] hv_n
Signed-off-by: Thiébaud Weksteen
---
scripts/gdb/linux/tasks.py | 2 --
1 file changed, 2 deletions(-)
diff --git a/scripts/gdb/linux/tasks.py b/scripts/gdb/linux/tasks.py
index 89d38e1..0fa33b0 100644
--- a/scripts/gdb/linux/tasks.py
+++ b/scripts/gdb/linux/tasks.py
@@ -20,7 +20,6 @@ task_type
On Thu, May 14, 2015 at 03:45:11PM +1000, NeilBrown wrote:
> On Wed, 29 Apr 2015 10:48:55 +0800 Yuanhan Liu
> wrote:
>
> > diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
> > index 64d5bea..697d77a 100644
> > --- a/drivers/md/raid5.c
> > +++ b/drivers/md/raid5.c
> > @@ -344,7 +344,8 @@ stati
Hi,
On Thursday 14 May 2015 12:19 AM, Brian Norris wrote:
On Wed, May 13, 2015 at 04:37:05PM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Wednesday 13 May 2015 04:58 AM, Brian Norris wrote:
Supports up to two ports which can each be powered on/off and configured
independently.
Signed-off-by:
On Wed, 29 Apr 2015 10:48:55 +0800 Yuanhan Liu
wrote:
> diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
> index 64d5bea..697d77a 100644
> --- a/drivers/md/raid5.c
> +++ b/drivers/md/raid5.c
> @@ -344,7 +344,8 @@ static void release_inactive_stripe_list(struct r5conf
> *conf,
>
From: Colin Cronin
Fixed spelling error in comment.
Signed-off-by: Colin Cronin
---
drivers/staging/xgifb/vb_setmode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/xgifb/vb_setmode.c
b/drivers/staging/xgifb/vb_setmode.c
index a47395e..3f7c10e 100644
---
Signed-off-by: Thiébaud Weksteen
---
scripts/gdb/linux/dmesg.py | 1 -
scripts/gdb/linux/symbols.py | 9 -
scripts/gdb/linux/tasks.py | 2 ++
scripts/gdb/linux/utils.py | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/scripts/gdb/linux/dmesg.py b/scripts/gdb/li
Signed-off-by: Thiébaud Weksteen
---
scripts/gdb/linux/utils.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/gdb/linux/utils.py b/scripts/gdb/linux/utils.py
index 128c306..d7ff3a3 100644
--- a/scripts/gdb/linux/utils.py
+++ b/scripts/gdb/linux/utils.py
@@ -83,7 +83,
Set of patches to clean up scripts/gdb
Thiébaud Weksteen (3):
scripts/gdb: Fix typo in exception name
scripts/gdb: Fix PEP8 compliance
scripts/gdb: Remove useless global instruction
scripts/gdb/linux/dmesg.py | 1 -
scripts/gdb/linux/symbols.py | 9 -
scripts/gdb/linux/tasks.py
On Tue, May 12, 2015 at 10:44 PM, Maxime Ripard
wrote:
> Hi,
>
> On Sun, May 10, 2015 at 12:54:50PM +0200, Jens Kuske wrote:
>> On 09/05/15 13:27, Maxime Ripard wrote:
>> > On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
>> >> The H3 clock control unit is similar to the those of other
On 14-05-15, 13:07, Kukjin Kim wrote:
> On 05/13/15 23:08, Bartlomiej Zolnierkiewicz wrote:
> >
> > Hi,
> >
> Hi Bart,
>
> > On Friday, April 03, 2015 06:43:43 PM Bartlomiej Zolnierkiewicz wrote:
> >> Hi,
> >>
> >> This patch series removes the use of Exynos4210 specific support
> >> from cpufre
On 03-04-15, 18:43, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham
>
> The new CPU clock type allows the use of generic CPUfreq driver.
> Switch Exynos4210 to using generic cpufreq driver.
>
> Changes by Bartlomiej:
> - removed non-Exynos4210 support for now
>
> Cc: Tomasz Figa
> Cc:
* Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the tip tree got a conflict in
> tools/testing/selftests/x86/run_x86_tests.sh between commit
> c1e6e5cb941b ("selftests, x86: Remove useless run_tests rule") from
> the kselftest-fixes tree and commit e22438f8e997 ("x86, sel
On 03-04-15, 18:43, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham
>
> Exynos4210 based platforms have switched over to use generic
> cpufreq driver for cpufreq functionality. So the Exynos
> specific cpufreq support for these platforms can be removed.
>
> Changes by Bartlomiej:
> - dro
On Tue, May 12, 2015 at 01:39:15AM +1000, Alexey Kardashevskiy wrote:
>This is a part of moving DMA window programming to an iommu_ops
>callback. pnv_pci_ioda2_set_window() takes an iommu_table_group as
>a first parameter (not pnv_ioda_pe) as it is going to be used as
>a callback for VFIO DDW code.
From: six...@microsoft.com
Date: Tue, 12 May 2015 15:50:02 -0700
> From: Simon Xiao
>
> Current code does not lock anything when calculating the TX and RX stats.
> As a result, the RX and TX data reported by ifconfig are not accuracy in a
> system with high network throughput and multiple CPUs (
On 2015/5/14 12:05, Hanjun Guo wrote:
> On 2015年05月14日 09:09, Jiang Liu wrote:
>> On 2015/5/13 21:25, Hanjun Guo wrote:
>>> On 2015年05月13日 20:24, Jiang Liu wrote:
On 2015/5/13 17:29, Hanjun Guo wrote:
> Hi Jiang,
>
> On 2015年05月05日 10:46, Jiang Liu wrote:
>
> struct pci_con
From: Tejun Heo
Date: Wed, 13 May 2015 11:46:20 -0400
> Hello, David.
>
> On Tue, May 12, 2015 at 07:23:22PM -0400, David Miller wrote:
>> Second question, is there an upper bound on this header size?
>> Because if there is, it seems to me that there is no reason why we
>> can't just avoid the f
2015-05-14 11:41 GMT+09:00 Kukjin Kim :
> On 05/11/15 10:27, Krzysztof Kozlowski wrote:
>> of_machine_is_compatible() seems to be preferred over soc_is_exynos4().
>>
>> Signed-off-by: Krzysztof Kozlowski
>>
>> ---
>> Changes since v2:
>> 1. New patch, requested by Kukjin Kim.
>> ---
>> arch/arm/m
Hi all,
Today's linux-next merge of the tip tree got a conflict in
tools/testing/selftests/x86/run_x86_tests.sh between commit
c1e6e5cb941b ("selftests, x86: Remove useless run_tests rule") from the
kselftest-fixes tree and commit e22438f8e997 ("x86, selftests: Add a
test for the "sysret_ss_attrs"
On Tue, May 12, 2015 at 01:39:14AM +1000, Alexey Kardashevskiy wrote:
>This is a part of moving TCE table allocation into an iommu_ops
>callback to support multiple IOMMU groups per one VFIO container.
>
>This moves the code which allocates the actual TCE tables to helpers:
>pnv_pci_ioda2_table_all
Hi all,
Today's linux-next merge of the tip tree got a conflict in
tools/testing/selftests/x86/Makefile between commit e9886ace222e
("selftests, x86: Rework x86 target architecture detection") from the
kselftest-fixes tree and commit e22438f8e997 ("x86, selftests: Add a
test for the "sysret_ss_att
On Tue, May 12, 2015 at 01:39:13AM +1000, Alexey Kardashevskiy wrote:
>This moves iommu_table creation to the beginning to make following changes
>easier to review. This starts using table parameters from the iommu_table
>struct.
>
>This should cause no behavioural change.
>
>Signed-off-by: Alexey
On 05/13/15 23:08, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
Hi Bart,
> On Friday, April 03, 2015 06:43:43 PM Bartlomiej Zolnierkiewicz wrote:
>> Hi,
>>
>> This patch series removes the use of Exynos4210 specific support
>> from cpufreq-exynos driver and enables the use of cpufreq-dt driver
>>
On 2015年05月14日 09:09, Jiang Liu wrote:
On 2015/5/13 21:25, Hanjun Guo wrote:
On 2015年05月13日 20:24, Jiang Liu wrote:
On 2015/5/13 17:29, Hanjun Guo wrote:
Hi Jiang,
On 2015年05月05日 10:46, Jiang Liu wrote:
struct pci_controller {
struct acpi_device *companion;
void *iommu;
On 05/14/2015 04:29 AM, Kevin Hilman wrote:
> "Rafael J. Wysocki" writes:
>
> [...]
>
>> Second, quite honestly, I don't see a connection to genpd here.
>
> The connection with genpd is because the *reason* the timer was
> shutdown/stopped is because it shares power with the CPU, which is why
>
On Wed, May 13, 2015 at 03:48:42PM +0200, Ingo Molnar wrote:
>
> Updated patch attached - I've added a few more features to the last
> table, and restructured the explanations, now every feature
> description also lists the Kconfig variable that it's tracking, e.g.:
>
> irq time acct: HAV
On 05/14/2015 01:00 AM, Thomas Huth wrote:
On Tue, 12 May 2015 01:39:12 +1000
Alexey Kardashevskiy wrote:
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without cleari
On Wed, May 13, 2015 at 8:30 PM, Al Viro wrote:
>
> Maybe... I'd like to see the profiles, TBH - especially getxattr() and
> access() frequency on various loads. Sure, make(1) and cc(1) really care
> about stat() very much, but I wouldn't be surprised if something like
> httpd or samba would be
On 05/14/2015 12:22 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:10AM +1000, Alexey Kardashevskiy wrote:
The iommu_table struct keeps a list of IOMMU groups it is used for.
At the moment there is just a single group attached but further
patches will add TCE table sharing. When sharing is
On Thu, May 14, 2015 at 09:01:03AM +0900, Masami Hiramatsu wrote:
> On 2015/05/14 0:41, William Cohen wrote:
> > On 05/13/2015 05:22 AM, Masami Hiramatsu wrote:
> >> On 2015/05/12 21:48, William Cohen wrote:
> >
> >>> Hi Dave,
> >>>
> >>> In some of the previous diagnostic output it looked like th
From: Khalid Aziz
Date: Mon, 27 Apr 2015 16:19:49 -0600
> @@ -342,9 +356,15 @@ static inline pgprot_t pgprot_noncached(pgprot_t prot)
> " andn%0, %4, %0\n"
> " or %0, %5, %0\n"
> " .previous\n"
> + " .section.sun_m7_2i
On 05/14/2015 12:10 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:09AM +1000, Alexey Kardashevskiy wrote:
At the moment the DMA setup code looks for the "ibm,opal-tce-kill" property
which contains the TCE kill register address. Writes to this register
invalidates TCE cache on IODA/IODA2 hu
On Tue, May 12, 2015 at 01:39:08AM +1000, Alexey Kardashevskiy wrote:
>This adds missing locks in iommu_take_ownership()/
>iommu_release_ownership().
>
>This marks all pages busy in iommu_table::it_map in order to catch
>errors if there is an attempt to use this table while ownership over it
>is ta
On 05/14/2015 11:21 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:05AM +1000, Alexey Kardashevskiy wrote:
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is
On Wed, May 13, 2015 at 06:39:53PM -0700, Linus Torvalds wrote:
> On Wed, May 13, 2015 at 3:25 PM, Al Viro wrote:
> > More on top of the current vfs.git#for-next (== the posted patchset
> > with a couple of fixes): more fs/namei.c reorganization and stack footprint
> > reduction (below 1Kb
On 5/13/15 4:49 PM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> The Arria10 SOC uses a completely different SDRAM controller from the
> earlier CycloneV and ArriaV SoCs. The memory size is calculated in
> the bootloader and passed via the device tree. Using this device
> tree s
On Tue, May 12, 2015 at 09:54:07PM +0200, Thomas Gummerer wrote:
>
> Hi,
>
> I noticed that on my machine the screen starts to flicker after I
> suspend and resume my machine, on the main laptop display if an external
> display is attached with kernel v4.1-rc1. I tracked the regression down
> to
On 05/14/2015 10:48 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:04AM +1000, Alexey Kardashevskiy wrote:
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table.
This commit includes a minor nomenclature fixup for boards based on the
Freescale VF610 SoC and which make use of the alternate "RMII1_RXD1"
functionality for pin PTC12. This brings the macro name in-line with
both the datasheet and other similar macros.
Signed-off-by: Cory Tusar
---
arch/arm/b
On Wed, May 13, 2015 at 12:18:26AM +0200, Philippe Reynes wrote:
> According to the imx27 documentation, fec has a 4 Kbyte
> memory space map. Moreover, the actual 16 Kbyte mapping
> overlaps the SCC (Security Controller) memory register
> space. So, we reduce the memory register space to 4 Kbyte.
On 05/14/2015 10:23 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:03AM +1000, Alexey Kardashevskiy wrote:
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where the
On Wed, May 13, 2015 at 10:56:39PM +0200, Arnd Bergmann wrote:
> Building the 842 code on 32-bit ARM currently results in this link
> error:
>
> ERROR: "__aeabi_uldivmod" [lib/842/842_decompress.ko] undefined!
>
> The reason is that the __do_index function performs a 64-bit
> division by a power-
On Wed, May 13, 2015 at 11:23:53AM -0700, Luis R. Rodriguez wrote:
> From: "Luis R. Rodriguez"
>
> We're going to add firmware module signing support, but when we do
> this we end up with the following recursive dependency. Fix this by
> just depending on FW_LOADER, which is typically always enab
On Wed, May 13, 2015 at 04:03:55PM +0100, David Howells wrote:
>
> So what if we want to use a key that's stored in a TPM? I presume then we
> can't use the crypto interface, but must rather use the *key* as the primary
> interface somehow.
Then it has nothing to do with what we're trying to do h
On Thu, 2015-05-14 at 12:34 +1000, Alexey Kardashevskiy wrote:
> On 05/14/2015 09:27 AM, Gavin Shan wrote:
> > On Wed, May 13, 2015 at 02:51:36PM +0200, Thomas Huth wrote:
> >> On Wed, 13 May 2015 16:30:16 +1000
> >> Alexey Kardashevskiy wrote:
> >>
> >>> On 05/13/2015 03:33 PM, Gavin Shan wrote:
max7359_keypad: implement DT bindings
Signed-off-by: Evgeniy A. Dushistov
---
.../devicetree/bindings/input/max7359-keypad.txt | 33
drivers/input/keyboard/max7359_keypad.c| 60 --
2 files changed, 90 insertions(+), 3 deletions(-)
create mode 10064
On 05/14/2015 10:00 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:02AM +1000, Alexey Kardashevskiy wrote:
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential no
On Wed, May 13, 2015 at 6:49 PM, Leonid Yegoshin
wrote:
> Some MIPS CPUs have an aggressive speculative load and may erroneuosly load
> some cache line in the middle of DMA transaction. CPU discards result but
> cache
> doesn't. If DMA happens from device then additional cache invalidation is
>
HI, Dmitry
thanks for your reply :)
On 2015年05月14日 01:41, Dmitry Torokhov wrote:
Hi,
On Wed, Apr 22, 2015 at 06:46:58PM +0800, Pan Xinhui wrote:
mxt_probe() may fail at last step, and the queue_work scheduled by
request_firmware_nowait
may run later and then access some data which is
On 05/11/15 10:27, Krzysztof Kozlowski wrote:
> of_machine_is_compatible() seems to be preferred over soc_is_exynos4().
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
> Changes since v2:
> 1. New patch, requested by Kukjin Kim.
> ---
> arch/arm/mach-exynos/exynos.c | 2 +-
> 1 file changed, 1 i
max7359_keypad: remove code duplication,
max7359_build_keycode do the same thing as matrix_keypad_build_keymap, but
matrix_keypad_build_keymap can also handle DT bindings, so remove
max7359_build_keycode and use matrix_keypad_build_keymap instead. Tested on
beagleboard-xm.
Signed-off-by: Evgen
max7359_keypad: Do not set MAX7359_CFG_INTERRUPT flag.
In datasheet of max7359, there is description of this flag:
0 - INT cleared when FIFO empty,
1 - INT cleared after host read. In this mode, I2C should read
FIFO until interrupt condition removed, or further INT may be lost.
So, if we set thi
On Tue, May 12, 2015 at 01:39:11AM +1000, Alexey Kardashevskiy wrote:
>This replaces direct accesses to TCE table with a helper which
>returns an TCE entry address. This does not make difference now but will
>when multi-level TCE tables get introduces.
>
>No change in behavior is expected.
>
>Signe
On 05/14/2015 09:27 AM, Gavin Shan wrote:
On Wed, May 13, 2015 at 02:51:36PM +0200, Thomas Huth wrote:
On Wed, 13 May 2015 16:30:16 +1000
Alexey Kardashevskiy wrote:
On 05/13/2015 03:33 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:38:54AM +1000, Alexey Kardashevskiy wrote:
At the moment
This patch adds a helper to get bits per pixel value of MIPI DSI pixel format.
The helper takes a parameter in the type 'enum mipi_dsi_pixel_format' and
returns it's bits per pixel value if the parameter is valid, otherwise, it
returns -EINVAL. The helper makes users' life easier to do the convers
On 2015年05月14日 07:11, Dylan Reid wrote:
On Wed, May 13, 2015 at 10:21 AM, Dylan Reid wrote:
On Wed, May 13, 2015 at 9:42 AM, Mark Brown wrote:
On Wed, May 13, 2015 at 09:23:01PM +0800, zhengxing wrote:
On 2015年05月13日 03:22, Mark Brown wrote:
Is it not possible to extend simple card to handl
On Tue, May 12, 2015 at 01:39:10AM +1000, Alexey Kardashevskiy wrote:
>The iommu_table struct keeps a list of IOMMU groups it is used for.
>At the moment there is just a single group attached but further
>patches will add TCE table sharing. When sharing is enabled, TCE cache
>in each PE needs to be
On Tue, May 12, 2015 at 01:39:09AM +1000, Alexey Kardashevskiy wrote:
>At the moment the DMA setup code looks for the "ibm,opal-tce-kill" property
>which contains the TCE kill register address. Writes to this register
>invalidates TCE cache on IODA/IODA2 hub.
>
>This moves the register address from
2015-05-12 21:36 GMT+08:00 Thierry Reding :
> On Fri, Feb 13, 2015 at 01:25:19PM +0800, Liu Ying wrote:
>> Signed-off-by: Liu Ying
>
> This could use a commit message. Describe for example why this is useful
> or when to use it.
Ok, I'll add it in the next version.
>
>> ---
>> v9->v9.5:
>> * Ad
Hi,
On Wed, May 13, 2015 at 04:36:33PM -0700, Tony Lindgren wrote:
> Turns out we can automate the handling for the device_may_wakeup()
> quite a bit by using the kernel wakeup source list.
>
> And as some hardware has separate dedicated wake-up interrupt
> in addition to the IO interrupt, we can
On Tue, May 12, 2015 at 01:39:07AM +1000, Alexey Kardashevskiy wrote:
>This adds tce_iommu_take_ownership() and tce_iommu_release_ownership
>which call in a loop iommu_take_ownership()/iommu_release_ownership()
>for every table on the group. As there is just one now, no change in
>behaviour is expe
On Thu, May 14, 2015 at 10:37:21AM +1000, Dave Chinner wrote:
> On Tue, May 12, 2015 at 11:48:02PM -0700, Jaegeuk Kim wrote:
> > On Wed, May 13, 2015 at 12:02:08PM +1000, Dave Chinner wrote:
> > > On Fri, May 08, 2015 at 09:20:38PM -0700, Jaegeuk Kim wrote:
> > > > This definitions will be used by
On Tue, May 12, 2015 at 01:39:06AM +1000, Alexey Kardashevskiy wrote:
>Modern IBM POWERPC systems support multiple (currently two) TCE tables
>per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
>for TCE tables. Right now just one table is supported.
>
>For IODA, instead of embeddi
The previous patches can be applied, once the corresponding module is
loaded. In general, the patch will do relocation (if necessary) and
obtain/verify function address before we start to enable patch.
There are three different situations in which the coming module notifier
can fail:
1) relocatio
Some MIPS CPUs have an aggressive speculative load and may erroneuosly load
some cache line in the middle of DMA transaction. CPU discards result but cache
doesn't. If DMA happens from device then additional cache invalidation is needed
on that CPU's after DMA.
Found in test.
Signed-off-by: Leoni
d copy of pfmemalloc to avoid accessing
> > page")
> > Reported-by: Felipe Balbi
> > Signed-off-by: Alexander Duyck
>
> Tested this on top of next-20150513 on an ARM/OMAP
> (am335x-boneblack.dts) an it fixes the boot problem for me.
>
> Tested-by: Kevin Hil
If the child process exited between the following code,
the child process will keep zomible status and perf process
will keep "poll" forever
if (done || draining)
break;
---//child process exit, done to 1
err = perf_evlist__poll(rec->evlist,-1);
so, change timeout to 1 second.
---
tools/per
If the child process exited between the following code,
the child process will keep zomible status and perf process
will keep "poll" forever
if (done || draining)
break;
---//child process exit, done to 1
err = perf_evlist__poll(rec->evlist,-1);
so, change timeout to 1 second.
---
tools/per
On Wed, May 13, 2015 at 3:25 PM, Al Viro wrote:
> More on top of the current vfs.git#for-next (== the posted patchset
> with a couple of fixes): more fs/namei.c reorganization and stack footprint
> reduction (below 1Kb now). One interesting piece of that is that we don't
> touch current->
On Thu, May 14, 2015 at 10:31:52AM +1000, Julian Calaby wrote:
> On Thu, May 14, 2015 at 4:23 AM, Luis R. Rodriguez
> wrote:
> > +"Require all firmware to be validly signed", under the same menu.
>
> You reference the relevant Kconfig symbols above, do you want to add
> it here too?
Sure, amende
On 05/13/15 at 09:14P, Josh Poimboeuf wrote:
> On Tue, May 12, 2015 at 10:04:44PM +0800, Minfei Huang wrote:
> > @@ -883,7 +883,7 @@ int klp_register_patch(struct klp_patch *patch)
> > }
> > EXPORT_SYMBOL_GPL(klp_register_patch);
> >
> > -static void klp_module_notify_coming(struct klp_patch *p
On Tue, May 12, 2015 at 01:39:05AM +1000, Alexey Kardashevskiy wrote:
>Modern IBM POWERPC systems support multiple (currently two) TCE tables
>per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
>for TCE tables. Right now just one table is supported.
>
>This defines iommu_table_gro
On 2015/5/13 21:25, Hanjun Guo wrote:
> On 2015年05月13日 20:24, Jiang Liu wrote:
>> On 2015/5/13 17:29, Hanjun Guo wrote:
>>> Hi Jiang,
>>>
>>> On 2015年05月05日 10:46, Jiang Liu wrote:
>>>
>>> struct pci_controller {
>>> struct acpi_device *companion;
>>> void *iommu;
>>> int
Hello,
On (05/13/15 16:35), Tejun Heo wrote:
[..]
> -static inline void threadgroup_lock(struct task_struct *tsk)
> +static inline void threadgroup_change_begin(struct task_struct *tsk)
> {
> - down_write(&tsk->signal->group_rwsem);
> + might_sleep();
I think cgroup_threadgroup_change_be
Fixed a few spelling errors in comments.
Signed-off-by: Colin Cronin
---
drivers/staging/skein/skein_api.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/skein/skein_api.h
b/drivers/staging/skein/skein_api.h
index 171b875..7da8b38 100644
--- a/drivers/
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