Hello Gilad,
You are right; I know about the
methods which NAPI-drivers use,like the
netif_rx_complete() method which reenable interrupts.
However, there is still a question:
There are many network drivers who have NAPI feature, as you described it,
but by default the act as only
hi rafi,
Rafi Gordon <[EMAIL PROTECTED]> writes:
> You don't mention the CPU here directly.
I explained what the CPU does to handle interrupts. Obviously, a
faster CPU will be able to handle more interupts, all circumstances
being equal. How many - in absolute numbers - will depend on what the
Rafi Gordon wrote:
A practical example which had driven me to post this question originally:
I want to know when I should use NAPI (polling) instead of interrupts
in a network
card so that I won't loss interrupts. (and data , as a result).
NAPI is not polling. In fact, you missed the whole po
On ש', 2005-12-03 at 03:17 -0500, Rafi Gordon wrote:
> Hello,
> Thanks for the answer.
>
> > I suppose it is OS-, device-, and driver-dependent.
>
> You don't mention the CPU here directly. I assume the CPU and it's clock speed
> has also to do with the upper limit of interrupts from which on
>
Rafi Gordon wrote:
>Hello,
> Thanks for the answer.
>
>
>
>>I suppose it is OS-, device-, and driver-dependent.
>>
>>
>
>You don't mention the CPU here directly.
>
Are you asking about the hardware or about the entire system? If you are
asking about the hardware, it is reasonable (I don't h
Hello,
Thanks for the answer.
> I suppose it is OS-, device-, and driver-dependent.
You don't mention the CPU here directly. I assume the CPU and it's clock speed
has also to do with the upper limit of interrupts from which on
interrupts will be dropped. Am I right ? From your answer it seems t
Rafi Gordon <[EMAIL PROTECTED]> writes:
> I assume that there is a limit on the maximum number of
> interruprs a CPU can receive without dropping or losing
> interrupts and not handling them.
>
> Is there a way in which I can determine in Linux what is this
> limit (
Hello,
Interrupts are handle by the PIC (Programmable Interrupt Controller) on older
processors and APIC (Advanced Programmable Interrupt Controller) on more
modern processors.
I assume that there is a limit on the maximum number of interruprs
a CPU can r
