Kees,
>> > When a character array without a terminating NUL character has a
>> > static initializer, GCC 15's -Wunterminated-string-initialization
>> > will only warn if the array lacks the "nonstring" attribute[1].
>> > Mark the arrays with __nonstring to and correctly identify the char
>> > ar
Thorsten,
> strncpy() is deprecated for NUL-terminated destination buffers; use
> strscpy() instead.
Applied to 6.16/scsi-staging, thanks!
--
Martin K. Petersen
On Fri, 11 Apr 2025 22:32:15 +0530, Kaustabh Chakraborty wrote:
> Document the compatible string for Exynos7870 - "samsung,exynos7870".
>
> The following devices are also added:
> - Galaxy A2 Core ("samsung,a2corelte")
> - Galaxy J6("samsung,j6lte")
> - Galaxy J7 Prime
Samsung Exynos 7870 (codename: Joshua) is an ARM-v8 system-on-chip that was
announced in 2016. The chipset was found in several popular mid-range to
low-end Samsung phones, released within 2016 to 2019.
This patch series aims to add support for Exynos 7870, starting with the
most basic yet essenti
Document the compatible string for Exynos7870 - "samsung,exynos7870".
The following devices are also added:
- Galaxy A2 Core ("samsung,a2corelte")
- Galaxy J6("samsung,j6lte")
- Galaxy J7 Prime ("samsung,on7xelte")
Signed-off-by: Kaustabh Chakraborty
---
Documentation/
Document the compatible string for Exynos7870 - "samsung,exynos7870".
The following devices are also added:
- Galaxy A2 Core ("samsung,a2corelte")
- Galaxy J6("samsung,j6lte")
- Galaxy J7 Prime ("samsung,on7xelte")
Signed-off-by: Kaustabh Chakraborty
---
Documentation/
Samsung Exynos 7870 (codename: Joshua) is an ARM-v8 system-on-chip that was
announced in 2016. The chipset was found in several popular mid-range to
low-end Samsung phones, released within 2016 to 2019.
This patch series aims to add support for Exynos 7870, starting with the
most basic yet essenti
On Fri, Apr 11, 2025 at 4:27 PM Michal Schmidt wrote:
> On Fri, Apr 11, 2025 at 9:26 AM Lee Jones wrote:
> > On Wed, 09 Apr 2025, Ivan Vecera wrote:
> > > Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> > > provides DPLL and PTP functionality. This series bring first part
> >
On Fri, Apr 11, 2025 at 04:27:08PM +0200, Michal Schmidt wrote:
> On Fri, Apr 11, 2025 at 9:26 AM Lee Jones wrote:
> > On Wed, 09 Apr 2025, Ivan Vecera wrote:
> > > Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> > > provides DPLL and PTP functionality. This series bring first
On Fri, Apr 11, 2025 at 9:26 AM Lee Jones wrote:
> On Wed, 09 Apr 2025, Ivan Vecera wrote:
> > Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> > provides DPLL and PTP functionality. This series bring first part
> > that adds the common MFD driver that provides an access to the
On 11. 04. 25 2:31 odp., Andrew Lunn wrote:
2nd regmap for indirect registers (mailboxes) (pages 10-15) with disabled
locking:
regmap_config {
...
.disable_lock = true,
...
};
Do all registers in pages 10-15 need special locking? Or just a
subset?
Andrew
A
On 11. 04. 25 1:19 odp., Ivan Vecera wrote:
The range for regmap 1: (registers 0x000-0x4FF)
regmap_range_cfg {
.range_min = 0,
.range_max = 10 * 128 - 1, /* 10 pages, 128 registers each */
.selector_reg = 0x7f, /* page selector at each page */
.selector_shift = 0, /
> 2nd regmap for indirect registers (mailboxes) (pages 10-15) with disabled
> locking:
>
> regmap_config {
> ...
> .disable_lock = true,
> ...
> };
Do all registers in pages 10-15 need special locking? Or just a
subset?
Andrew
On 10. 04. 25 7:50 odp., Andy Shevchenko wrote:
On Wed, Apr 9, 2025 at 5:43 PM Ivan Vecera wrote:
Add register definitions for components versions and report them
during probe.
JFYI: disabling regmap lock (independently of having an additional one
or not) is not recommended. With that you
On 10. 04. 25 11:12 odp., Andrew Lunn wrote:
On Thu, Apr 10, 2025 at 08:33:31PM +0200, Ivan Vecera wrote:
On 10. 04. 25 7:36 odp., Andrew Lunn wrote:
Prathosh, could you please bring more light on this?
Just to clarify, the original driver was written specifically with 2-channel
chips in
On 11. 04. 25 9:26 dop., Lee Jones wrote:
On Wed, 09 Apr 2025, Ivan Vecera wrote:
Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
provides DPLL and PTP functionality. This series bring first part
that adds the common MFD driver that provides an access to the bus
that can be ei
On 11. 04. 25 12:57 dop., Jakub Kicinski wrote:
On Thu, 10 Apr 2025 11:18:24 +0200 Ivan Vecera wrote:
On 10. 04. 25 2:17 dop., Jakub Kicinski wrote:
On Wed, 9 Apr 2025 16:42:36 +0200 Ivan Vecera wrote:
Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
provides DPLL and PTP
On Wed, 09 Apr 2025, Ivan Vecera wrote:
> Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> provides DPLL and PTP functionality. This series bring first part
> that adds the common MFD driver that provides an access to the bus
> that can be either I2C or SPI.
>
> The next series
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