Hi Günther and Mickaël Salaün,
On 2025/4/11 01:05, Mickaël Salaün wrote:
This is in my understanding a duplicate of the discussion in
https://lore.kernel.org/all/20250407-kbuild-disable-gcc-plugins-v1-1-5d46ae583...@kernel.org/
Yes, a new patch has been submitted:
https://lore.kernel.org/all/20
Patch to add nf_flow_encap_push(), see patch message.
Added patch to eliminate array of flexible structures warning.
Changed in v11:
- Only push when tuple.out.ifidx == tuple.out.hw_ifidx
- No changes in nft_dev_path_info()
v10 split from patch-set: bridge-fastpath and related improvements v9
E
On Thu, Mar 27, 2025 at 10:59:04AM -0600, Gustavo A. R. Silva wrote:
> -Wflex-array-member-not-at-end was introduced in GCC-14, and we are
> getting ready to enable it, globally.
>
> Use the `DEFINE_RAW_FLEX()` helper for on-stack definitions of
> a flexible structure where the size of the flexibl
On Mon, Apr 07, 2025 at 07:28:29PM +0200, Ivan Vecera wrote:
> Use devlink_alloc() to alloc zl3073x_dev structure and register
> the device as a devlink device. Follow-up patches add support for
> devlink device info reporting and devlink flash interface will
> be later used for flashing firmware a
On 2025/4/8 00:17, Kees Cook wrote:
>> strstarts() is frequently invoked to test if a string has another string
>> as prefix, but its performance is degraded by the strlen() loop contained.
>>
>> Improve its performance by eliminating the strlen() loop.
> So, as Andy already said: no, this is very
On Sat, Mar 15, 2025 at 09:27:36AM -0500, Alex Elder wrote:
> On 3/10/25 5:24 PM, Kees Cook wrote:
> > GCC 15's -Wunterminated-string-initialization warned about truncated
> > name strings. Instead of marking them with the "nonstring" attribute[1],
> > increase their length to correctly include eno
On Tue, 25 Mar 2025, André Draszik wrote:
> Hi,
>
> This series improves support for the Maxim Integrated MAX77759
> companion PMIC for USB Type-C applications using the MFD framework.
>
> This series must be applied in-order, due to interdependencies of some
> of the patches:
> * to avoid use o
On Thu, 10 Apr 2025 11:18:24 +0200 Ivan Vecera wrote:
> On 10. 04. 25 2:17 dop., Jakub Kicinski wrote:
> > On Wed, 9 Apr 2025 16:42:36 +0200 Ivan Vecera wrote:
> >> Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> >> provides DPLL and PTP functionality. This series bring first
Add several macros to access device registers. These macros
defines a couple of static inline functions to ease an access
device registers. There are two types of registers, the 1st type
is a simple one that is defined by an address and size and the 2nd
type is indexed register that is defined by b
On Thu, Apr 10, 2025 at 08:44:43PM +0200, Ivan Vecera wrote:
>
>
> On 10. 04. 25 7:41 odp., Andrew Lunn wrote:
> > > > > + /* Take device lock */
> > > >
> > > > What is a device lock? Why do you need to comment standard
> > > > guards/mutexes?
> > >
> > > Just to inform code reader, this
This adds support to get fractional frequency offset for input pins.
Implement the appropriate callback that performs reference frequency
measurement and reports the frequency offset between the DPLL and
the reference.
Reviewed-by: Michal Schmidt
Co-developed-by: Prathosh Satish
Signed-off-by: P
On Thu, Mar 20, 2025 at 05:56:44PM +0100, Thorsten Blum wrote:
> strncpy() is deprecated for NUL-terminated destination buffers; use
> strscpy() instead. Since kzalloc() already zeroes out the destination
> buffer, the potential NUL-padding by strncpy() is unnecessary. strscpy()
> copies only the r
On 07. 04. 25 7:53 odp., Krzysztof Kozlowski wrote:
On 07/04/2025 19:28, Ivan Vecera wrote:
This adds base MFD driver for Microchip Azurite ZL3073x chip family.
Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v
Add support to get/set frequency from/to input pins. The frequency
for input pins (references) is computed in the device according this
formula:
freq = base_freq * multiplier * (nominator / denominator)
where the base_freq comes from the list of supported base frequencies
and other parameters ar
On 07. 04. 25 10:57 odp., Andrew Lunn wrote:
On Mon, Apr 07, 2025 at 07:28:29PM +0200, Ivan Vecera wrote:
Use devlink_alloc() to alloc zl3073x_dev structure and register
the device as a devlink device. Follow-up patches add support for
devlink device info reporting and devlink flash interface wi
Registers present in page 10 and higher are organized in so-called
register mailboxes. These mailboxes are used to read and write
configuration of particular object (dpll, output, reference & synth).
Each of these register pages contains mask register that is used by
the driver to indicate an inde
On Thu, Apr 10, 2025 at 08:33:31PM +0200, Ivan Vecera wrote:
>
>
> On 10. 04. 25 7:36 odp., Andrew Lunn wrote:
> > > Prathosh, could you please bring more light on this?
> > >
> > > > Just to clarify, the original driver was written specifically with
> > > > 2-channel
> > > > chips in mind (ZL3
Add a common DT schema for DPLL device and associated pin.
The DPLL (device phase-locked loop) is a device used for precise clock
synchronization in networking and telecom hardware.
The device itself is equipped with one or more DPLLs (channels) and
one or more physical input and output pins.
Eac
On 7. Apr 2025, at 20:28, Kees Cook wrote:
> On Wed, Feb 26, 2025 at 07:55:26PM +0100, Thorsten Blum wrote:
>> strncpy() is deprecated for NUL-terminated destination buffers; use
>> strscpy() instead.
>>
>> Compile-tested only.
>>
>> Link: https://github.com/KSPP/linux/issues/90
>> Cc: linux-hard
On 09/04/2025 16:42, Ivan Vecera wrote:
> Add several macros to access device registers. These macros
> defines a couple of static inline functions to ease an access
> device registers. There are two types of registers, the 1st type
> is a simple one that is defined by an address and size and the 2
Add base MFD driver for Microchip Azurite ZL3073x chip family.
These chips provide DPLL and PHC (PTP) functionality and they can
be connected over I2C or SPI bus.
The MFD driver provide basic communication and synchronization
over the bus and common functionality that are used by the DPLL
driver (
Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
provides DPLL and PTP functionality. This series bring first part
that adds the common MFD driver that provides an access to the bus
that can be either I2C or SPI.
The next series will bring the DPLL driver that will covers DPLL
fun
On 10. 04. 25 7:41 odp., Andrew Lunn wrote:
+ /* Take device lock */
What is a device lock? Why do you need to comment standard guards/mutexes?
Just to inform code reader, this is a section that accesses device registers
that are protected by this zl3073x device lock.
I didn't see
On 10. 04. 25 7:50 odp., Andrew Lunn wrote:
On Thu, Apr 10, 2025 at 09:52:39AM +0200, Ivan Vecera wrote:
On 10. 04. 25 9:19 dop., Krzysztof Kozlowski wrote:
On 09/04/2025 17:43, Andy Shevchenko wrote:
+/*
+ * Regmap range configuration
+ *
+ * The device uses 7-bit addressing and has 16 r
Hi Ivan,
yes you are right, the only difference is the number of channels.
Prathosh
-Original Message-
From: Ivan Vecera
Sent: Thursday 10 April 2025 18:36
To: Prathosh Satish - M66066 ; co...@kernel.org
Cc: k...@kernel.org; net...@vger.kernel.org; vadim.fedore...@linux.dev;
arkadiusz
On 10. 04. 25 7:36 odp., Andrew Lunn wrote:
Prathosh, could you please bring more light on this?
Just to clarify, the original driver was written specifically with 2-channel
chips in mind (ZL30732) with 10 input and 20 outputs, which led to some
confusion of using zl3073x as compatible.
How
GCC 15's -Wunterminated-string-initialization warned about truncated
name strings. Instead of marking them with the "nonstring" attribute[1],
increase their length to correctly include enough space for the
terminating NUL character, as they are used with %s format specifiers
when showing resource a
Add .clock_id to zl3073x_dev structure that will be used by later
commits introducing DPLL driver. The clock ID is necessary for DPLL
device registration. To generate such ID use chip ID read during
device initialization for this. For the case where are multiple
zl3073x based chips the chip ID is
Sometimes in communication with the device is necessary to set
certain bit(s) in certain register and then the driver has to
wait until these bits are cleared by the device.
Add the macro for this functionality, it will be used by later
commits.
Signed-off-by: Ivan Vecera
---
v1->v2:
* fixed mac
On Mon, Apr 07, 2025 at 10:33:34PM +0800, Zijun Hu wrote:
> On 2025/4/7 21:51, Andy Shevchenko wrote:
> > First of all, this function is supposed to be run against constant string
> > literals.
>
> for strstarts(s, "prefix"), strlen("prefix") should *NOT* be compile
> time constant. it is a loop
On Mon, Apr 7, 2025 at 8:02 PM Krzysztof Kozlowski wrote:
> On 07/04/2025 19:31, Ivan Vecera wrote:
> > This adds DT bindings schema for DPLL (device phase-locked loop)
> > Reviewed-by: Michal Schmidt
>
> Did this really happen?
We have been through several iterations of the patchset internally.
On Thu, Apr 10, 2025 at 11:21 AM Ivan Vecera wrote:
> On 10. 04. 25 9:17 dop., Krzysztof Kozlowski wrote:
> > On 09/04/2025 16:42, Ivan Vecera wrote:
...
> >> +WARN_ON(idx >= (_num)); \
> >
> > No need to cause panic reboots. Either review your code so
On Wed, Apr 9, 2025 at 5:43 PM Ivan Vecera wrote:
>
> Add register definitions for components versions and report them
> during probe.
JFYI: disabling regmap lock (independently of having an additional one
or not) is not recommended. With that you actually disable the useful
debugging feature of
On Thu, Apr 10, 2025 at 09:52:39AM +0200, Ivan Vecera wrote:
>
>
> On 10. 04. 25 9:19 dop., Krzysztof Kozlowski wrote:
> > On 09/04/2025 17:43, Andy Shevchenko wrote:
> > > > +/*
> > > > + * Regmap range configuration
> > > > + *
> > > > + * The device uses 7-bit addressing and has 16 register pa
On 09/04/2025 08:44, Ivan Vecera wrote:
> On 07. 04. 25 11:09 odp., Andrew Lunn wrote:
>> On Mon, Apr 07, 2025 at 07:28:32PM +0200, Ivan Vecera wrote:
>>> Add register definitions for components versions and report them
>>> during probe.
>>>
>>> Reviewed-by: Michal Schmidt
>>> Signed-off-by: Ivan
On 10/04/2025 12:23, Ivan Vecera wrote:
>
>
> On 10. 04. 25 9:11 dop., Krzysztof Kozlowski wrote:
>> On 09/04/2025 08:44, Ivan Vecera wrote:
>>> On 07. 04. 25 11:09 odp., Andrew Lunn wrote:
On Mon, Apr 07, 2025 at 07:28:32PM +0200, Ivan Vecera wrote:
> Add register definitions for compon
> > > + /* Take device lock */
> >
> > What is a device lock? Why do you need to comment standard guards/mutexes?
>
> Just to inform code reader, this is a section that accesses device registers
> that are protected by this zl3073x device lock.
I didn't see a reply to my question about the big p
> Prathosh, could you please bring more light on this?
>
> > Just to clarify, the original driver was written specifically with
> > 2-channel
> > chips in mind (ZL30732) with 10 input and 20 outputs, which led to some
> > confusion of using zl3073x as compatible.
> > However, the final version
On 10. 04. 25 7:07 odp., prathosh.sat...@microchip.com wrote:
-Original Message-
From: Ivan Vecera
Sent: Thursday 10 April 2025 14:36
To: Conor Dooley ; Prathosh Satish - M66066
Cc: Krzysztof Kozlowski ; net...@vger.kernel.org; Vadim Fedorenko ; Arkadiusz Kubalewski
; Jiri Pirko ;
> Btw. I would be interesting to see a NIC that just exposes an access to I2C
> bus (implements I2C read/write by NIC firmware) instead of exposing complete
> DPLL API from the firmware. Just an idea.
The mellanox driver does expose an standard Linux I2C bus, with the
firmware wiggling the bits on
On Thu, Apr 10, 2025 at 05:33:21PM +0200, Günther Noack wrote:
> Hello!
>
> On Thu, Apr 10, 2025 at 04:11:15PM +0800, WangYuli wrote:
> > [ Compilation failure log: ]
> >
> > *** WARNING *** there are active plugins, do not report this as a bug unless
> > you can reproduce it without enabling an
-Original Message-
From: Ivan Vecera
Sent: Thursday 10 April 2025 14:36
To: Conor Dooley ; Prathosh Satish - M66066
Cc: Krzysztof Kozlowski ; net...@vger.kernel.org; Vadim
Fedorenko ; Arkadiusz Kubalewski
; Jiri Pirko ; Rob Herring
; Krzysztof Kozlowski ; Conor Dooley
; Prathosh Sat
On Wed, 09 Apr 2025, Ivan Vecera wrote:
> Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
> provides DPLL and PTP functionality. This series bring first part
> that adds the common MFD driver that provides an access to the bus
> that can be either I2C or SPI.
>
> The next series
Hello!
On Thu, Apr 10, 2025 at 04:11:15PM +0800, WangYuli wrote:
> [ Compilation failure log: ]
>
> *** WARNING *** there are active plugins, do not report this as a bug unless
> you can reproduce it without enabling an
> y plugins.
> Event | Plugins
> PLUGIN_FINISH_TYP
On 09/04/2025 09:19, Ivan Vecera wrote:
>>> +
>>> +maintainers:
>>> + - Ivan Vecera
>>> +
>>> +properties:
>>> + compatible:
>>> +enum:
>>> + - microchip,zl3073x-i2c
>>> + - microchip,zl3073x-spi
>>
>> 1. No, you do not get two compatibles. Only one.
>
> Will split to two files, o
On Thu, Apr 10, 2025 at 09:45:47AM +0200, Ivan Vecera wrote:
>
>
> On 10. 04. 25 9:06 dop., Krzysztof Kozlowski wrote:
> > On Wed, Apr 09, 2025 at 04:42:38PM GMT, Ivan Vecera wrote:
> > > Add DT bindings for Microchip Azurite DPLL chip family. These chips
> > > provides 2 independent DPLL channel
On 10. 04. 25 3:18 odp., Conor Dooley wrote:
On Thu, Apr 10, 2025 at 09:45:47AM +0200, Ivan Vecera wrote:
On 10. 04. 25 9:06 dop., Krzysztof Kozlowski wrote:
On Wed, Apr 09, 2025 at 04:42:38PM GMT, Ivan Vecera wrote:
Add DT bindings for Microchip Azurite DPLL chip family. These chips
prov
-Wflex-array-member-not-at-end was introduced in GCC-14, and we are
getting ready to enable it, globally.
Use the `DEFINE_RAW_FLEX()` helper for on-stack definitions of
a flexible structure where the size of the flexible-array member
is known at compile-time, and refactor the rest of the code,
acc
On 10. 04. 25 2:19 odp., Krzysztof Kozlowski wrote:
On 10/04/2025 12:28, Ivan Vecera wrote:
2. What is 'x'? Wildcard? If so, drop and use specific compatibles.
Microchip refers to the ZL3073x as a family of compatible DPLL chips
with the same features. There is no need to introduce separa
On 10/04/2025 12:28, Ivan Vecera wrote:
>
2. What is 'x'? Wildcard? If so, drop and use specific compatibles.
>>>
>>> Microchip refers to the ZL3073x as a family of compatible DPLL chips
>>> with the same features. There is no need to introduce separate
>>> compatible string for each of them.
On 10. 04. 25 12:42 odp., Krzysztof Kozlowski wrote:
On 10/04/2025 12:23, Ivan Vecera wrote:
On 10. 04. 25 9:11 dop., Krzysztof Kozlowski wrote:
On 09/04/2025 08:44, Ivan Vecera wrote:
On 07. 04. 25 11:09 odp., Andrew Lunn wrote:
On Mon, Apr 07, 2025 at 07:28:32PM +0200, Ivan Vecera wrot
On 10. 04. 25 9:11 dop., Krzysztof Kozlowski wrote:
On 09/04/2025 08:44, Ivan Vecera wrote:
On 07. 04. 25 11:09 odp., Andrew Lunn wrote:
On Mon, Apr 07, 2025 at 07:28:32PM +0200, Ivan Vecera wrote:
Add register definitions for components versions and report them
during probe.
Reviewed-by:
On 10. 04. 25 9:01 dop., Krzysztof Kozlowski wrote:
On 09/04/2025 09:19, Ivan Vecera wrote:
+
+maintainers:
+ - Ivan Vecera
+
+properties:
+ compatible:
+enum:
+ - microchip,zl3073x-i2c
+ - microchip,zl3073x-spi
1. No, you do not get two compatibles. Only one.
Will split
On 10. 04. 25 2:17 dop., Jakub Kicinski wrote:
On Wed, 9 Apr 2025 16:42:36 +0200 Ivan Vecera wrote:
Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
provides DPLL and PTP functionality. This series bring first part
that adds the common MFD driver that provides an access to t
On 09/04/2025 16:42, Ivan Vecera wrote:
> Add register definitions for components versions and report them
> during probe.
>
> Signed-off-by: Ivan Vecera
> ---
> drivers/mfd/zl3073x-core.c | 36
> 1 file changed, 36 insertions(+)
>
> diff --git a/drivers/mfd
On 09/04/2025 17:43, Andy Shevchenko wrote:
>> +/*
>> + * Regmap range configuration
>> + *
>> + * The device uses 7-bit addressing and has 16 register pages with
>> + * range 0x00-0x7f. The register 0x7f in each page acts as page
>> + * selector where bits 0-3 contains currently selected page.
>>
On 10. 04. 25 9:13 dop., Krzysztof Kozlowski wrote:
On 09/04/2025 16:42, Ivan Vecera wrote:
Add register definitions for components versions and report them
during probe.
Signed-off-by: Ivan Vecera
---
drivers/mfd/zl3073x-core.c | 36
1 file changed, 36
[ Compilation failure log: ]
*** WARNING *** there are active plugins, do not report this as a bug
unless you can reproduce it without enabling an
y plugins.
Event | Plugins
PLUGIN_FINISH_TYPE | randomize_layout_plugin
PLUGIN_FINISH_DECL |
On 10. 04. 25 9:17 dop., Krzysztof Kozlowski wrote:
On 09/04/2025 16:42, Ivan Vecera wrote:
Add several macros to access device registers. These macros
defines a couple of static inline functions to ease an access
device registers. There are two types of registers, the 1st type
is a simple on
On Tue, Apr 8, 2025, at 22:37, Kees Cook wrote:
> On April 8, 2025 2:22:52 AM PDT, Arnd Bergmann wrote:
>>>
>>> indicates that Talos 1.9.1 uses latent_entropy (but we didn't check how
>>> accurate that survey is).
>
> The early RNG for small machines remains pretty bad, so I can
> understand want
On 10. 04. 25 9:19 dop., Krzysztof Kozlowski wrote:
On 09/04/2025 17:43, Andy Shevchenko wrote:
+/*
+ * Regmap range configuration
+ *
+ * The device uses 7-bit addressing and has 16 register pages with
+ * range 0x00-0x7f. The register 0x7f in each page acts as page
+ * selector where bits 0
On 10. 04. 25 9:06 dop., Krzysztof Kozlowski wrote:
On Wed, Apr 09, 2025 at 04:42:38PM GMT, Ivan Vecera wrote:
Add DT bindings for Microchip Azurite DPLL chip family. These chips
provides 2 independent DPLL channels, up to 10 differential or
single-ended inputs and up to 20 differential or 20
On Wed, Apr 09, 2025 at 04:42:38PM GMT, Ivan Vecera wrote:
> Add DT bindings for Microchip Azurite DPLL chip family. These chips
> provides 2 independent DPLL channels, up to 10 differential or
> single-ended inputs and up to 20 differential or 20 single-ended outputs.
> It can be connected via I2C
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